| 209,7 → 209,8 |
|---|
| CT_RN50_POWER, |
| CT_MAC_X800, |
| CT_MAC_G5_9600, |
| CT_SAM440EP |
| CT_SAM440EP, |
| CT_MAC_G4_SILVER |
| }; |
| |
| enum radeon_dvo_chip { |
| 425,7 → 426,7 |
|---|
| uint32_t igp_lane_info; |
| /* displayport */ |
| struct radeon_i2c_chan *dp_i2c_bus; |
| u8 dpcd[8]; |
| u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
| u8 dp_sink_type; |
| int dp_clock; |
| int dp_lane_count; |
| 556,7 → 557,7 |
|---|
| u8 val); |
| extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
| extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); |
| extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); |
| extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
| extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
| |
| extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |