| 46,32 → 46,6 |
|---|
| #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
| #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
| |
| enum radeon_connector_type { |
| CONNECTOR_NONE, |
| CONNECTOR_VGA, |
| CONNECTOR_DVI_I, |
| CONNECTOR_DVI_D, |
| CONNECTOR_DVI_A, |
| CONNECTOR_STV, |
| CONNECTOR_CTV, |
| CONNECTOR_LVDS, |
| CONNECTOR_DIGITAL, |
| CONNECTOR_SCART, |
| CONNECTOR_HDMI_TYPE_A, |
| CONNECTOR_HDMI_TYPE_B, |
| CONNECTOR_0XC, |
| CONNECTOR_0XD, |
| CONNECTOR_DIN, |
| CONNECTOR_DISPLAY_PORT, |
| CONNECTOR_UNSUPPORTED |
| }; |
| |
| enum radeon_dvi_type { |
| DVI_AUTO, |
| DVI_DIGITAL, |
| DVI_ANALOG |
| }; |
| |
| enum radeon_rmx_type { |
| RMX_OFF, |
| RMX_FULL, |
| 88,6 → 62,7 |
|---|
| TV_STD_SCART_PAL, |
| TV_STD_SECAM, |
| TV_STD_PAL_CN, |
| TV_STD_PAL_N, |
| }; |
| |
| /* radeon gpio-based i2c |
| 150,16 → 125,24 |
|---|
| #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
| #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
| #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
| #define RADEON_PLL_USE_POST_DIV (1 << 12) |
| |
| struct radeon_pll { |
| uint16_t reference_freq; |
| uint16_t reference_div; |
| /* reference frequency */ |
| uint32_t reference_freq; |
| |
| /* fixed dividers */ |
| uint32_t reference_div; |
| uint32_t post_div; |
| |
| /* pll in/out limits */ |
| uint32_t pll_in_min; |
| uint32_t pll_in_max; |
| uint32_t pll_out_min; |
| uint32_t pll_out_max; |
| uint16_t xclk; |
| uint32_t best_vco; |
| |
| /* divider limits */ |
| uint32_t min_ref_div; |
| uint32_t max_ref_div; |
| uint32_t min_post_div; |
| 168,7 → 151,12 |
|---|
| uint32_t max_feedback_div; |
| uint32_t min_frac_feedback_div; |
| uint32_t max_frac_feedback_div; |
| uint32_t best_vco; |
| |
| /* flags for the current clock */ |
| uint32_t flags; |
| |
| /* pll id */ |
| uint32_t id; |
| }; |
| |
| struct radeon_i2c_chan { |
| 311,7 → 299,7 |
|---|
| struct radeon_encoder_atom_dig { |
| /* atom dig */ |
| bool coherent_mode; |
| int dig_block; |
| int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */ |
| /* atom lvds */ |
| uint32_t lvds_misc; |
| uint16_t panel_pwr_delay; |
| 334,6 → 322,9 |
|---|
| enum radeon_rmx_type rmx_type; |
| struct drm_display_mode native_mode; |
| void *enc_priv; |
| int hdmi_offset; |
| int hdmi_audio_workaround; |
| int hdmi_buffer_status; |
| }; |
| |
| struct radeon_connector_atom_dig { |
| 392,6 → 383,11 |
|---|
| struct drm_gem_object *obj; |
| }; |
| |
| extern enum radeon_tv_std |
| radeon_combios_get_tv_info(struct radeon_device *rdev); |
| extern enum radeon_tv_std |
| radeon_atombios_get_tv_info(struct radeon_device *rdev); |
| |
| extern void radeon_connector_hotplug(struct drm_connector *connector); |
| extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
| extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, |
| 434,8 → 430,7 |
|---|
| uint32_t *fb_div_p, |
| uint32_t *frac_fb_div_p, |
| uint32_t *ref_div_p, |
| uint32_t *post_div_p, |
| int flags); |
| uint32_t *post_div_p); |
| |
| extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
| uint64_t freq, |
| 443,8 → 438,7 |
|---|
| uint32_t *fb_div_p, |
| uint32_t *frac_fb_div_p, |
| uint32_t *ref_div_p, |
| uint32_t *post_div_p, |
| int flags); |
| uint32_t *post_div_p); |
| |
| extern void radeon_setup_encoder_clones(struct drm_device *dev); |
| |
| 470,7 → 464,6 |
|---|
| |
| extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| struct drm_framebuffer *old_fb); |
| extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); |
| |
| extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
| struct drm_file *file_priv, |