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Regard whitespace Rev 1429 → Rev 1430

/drivers/video/drm/radeon/radeon_legacy_crtc.c
321,11 → 321,13
RADEON_CRTC_DISP_REQ_EN_B));
WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
}
drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
radeon_crtc_load_lut(crtc);
break;
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
case DRM_MODE_DPMS_OFF:
drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
if (radeon_crtc->crtc_id)
WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
else {
401,7 → 403,7
 
/* if scanout was in GTT this really wouldn't work */
/* crtc offset is from display base addr not FB location */
radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 
base -= radeon_crtc->legacy_display_base_addr;
 
580,29 → 582,6
? RADEON_CRTC_V_SYNC_POL
: 0));
 
/* TODO -> Dell Server */
if (0) {
uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 
dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 
/* For CRT on DAC2, don't turn it on if BIOS didn't
enable it, even it's detected.
*/
disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
WREG32(RADEON_DAC_CNTL2, dac2_cntl);
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
}
 
if (radeon_crtc->crtc_id) {
uint32_t crtc2_gen_cntl;
uint32_t disp2_merge_cntl;
724,6 → 703,10
pll = &rdev->clock.p1pll;
 
pll->flags = RADEON_PLL_LEGACY;
if (radeon_new_pll == 1)
pll->algo = PLL_ALGO_NEW;
else
pll->algo = PLL_ALGO_LEGACY;
 
if (mode->clock > 200000) /* range limits??? */
pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;