| 30,8 → 30,7 |
|---|
| #include "radeon.h" |
| |
| |
| static inline void * |
| pci_alloc_consistent(struct pci_dev *hwdev, size_t size, |
| void* pci_alloc_consistent(struct pci_dev *hwdev, size_t size, |
| addr_t *dma_handle) |
| { |
| |
| 174,6 → 173,19 |
|---|
| radeon_bo_unpin(rdev->gart.robj); |
| radeon_bo_unreserve(rdev->gart.robj); |
| rdev->gart.table_addr = gpu_addr; |
| |
| if (!r) { |
| int i; |
| |
| /* We might have dropped some GART table updates while it wasn't |
| * mapped, restore all entries |
| */ |
| for (i = 0; i < rdev->gart.num_gpu_pages; i++) |
| radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]); |
| mb(); |
| radeon_gart_tlb_flush(rdev); |
| } |
| |
| return r; |
| } |
| |
| 237,7 → 249,6 |
|---|
| unsigned t; |
| unsigned p; |
| int i, j; |
| u64 page_base; |
| |
| if (!rdev->gart.ready) { |
| WARN(1, "trying to unbind memory from uninitialized GART !\n"); |
| 248,20 → 259,20 |
|---|
| for (i = 0; i < pages; i++, p++) { |
| if (rdev->gart.pages[p]) { |
| rdev->gart.pages[p] = NULL; |
| rdev->gart.pages_addr[p] = rdev->dummy_page.addr; |
| page_base = rdev->gart.pages_addr[p]; |
| for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
| rdev->gart.pages_entry[t] = rdev->dummy_page.entry; |
| if (rdev->gart.ptr) { |
| radeon_gart_set_page(rdev, t, page_base, |
| RADEON_GART_PAGE_DUMMY); |
| radeon_gart_set_page(rdev, t, |
| rdev->dummy_page.entry); |
| } |
| page_base += RADEON_GPU_PAGE_SIZE; |
| } |
| } |
| } |
| if (rdev->gart.ptr) { |
| mb(); |
| radeon_gart_tlb_flush(rdev); |
| } |
| } |
| |
| /** |
| * radeon_gart_bind - bind pages into the gart page table |
| 283,7 → 294,7 |
|---|
| { |
| unsigned t; |
| unsigned p; |
| uint64_t page_base; |
| uint64_t page_base, page_entry; |
| int i, j; |
| |
| if (!rdev->gart.ready) { |
| 294,18 → 305,21 |
|---|
| p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
| |
| for (i = 0; i < pages; i++, p++) { |
| rdev->gart.pages_addr[p] = dma_addr[i]; |
| rdev->gart.pages[p] = pagelist[i]; |
| page_base = dma_addr[i]; |
| for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
| page_entry = radeon_gart_get_page_entry(page_base, flags); |
| rdev->gart.pages_entry[t] = page_entry; |
| if (rdev->gart.ptr) { |
| page_base = rdev->gart.pages_addr[p]; |
| for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
| radeon_gart_set_page(rdev, t, page_base, flags); |
| radeon_gart_set_page(rdev, t, page_entry); |
| } |
| page_base += RADEON_GPU_PAGE_SIZE; |
| } |
| } |
| } |
| if (rdev->gart.ptr) { |
| mb(); |
| radeon_gart_tlb_flush(rdev); |
| } |
| return 0; |
| } |
| |
| 343,16 → 357,15 |
|---|
| radeon_gart_fini(rdev); |
| return -ENOMEM; |
| } |
| rdev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) * |
| rdev->gart.num_cpu_pages); |
| if (rdev->gart.pages_addr == NULL) { |
| rdev->gart.pages_entry = KernelAlloc(sizeof(uint64_t) * |
| rdev->gart.num_gpu_pages); |
| if (rdev->gart.pages_entry == NULL) { |
| radeon_gart_fini(rdev); |
| return -ENOMEM; |
| } |
| /* set GART entry to point to the dummy page by default */ |
| for (i = 0; i < rdev->gart.num_cpu_pages; i++) { |
| rdev->gart.pages_addr[i] = rdev->dummy_page.addr; |
| } |
| for (i = 0; i < rdev->gart.num_gpu_pages; i++) |
| rdev->gart.pages_entry[i] = rdev->dummy_page.entry; |
| return 0; |
| } |
| |
| 365,15 → 378,15 |
|---|
| */ |
| void radeon_gart_fini(struct radeon_device *rdev) |
| { |
| if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { |
| if (rdev->gart.ready) { |
| /* unbind pages */ |
| radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); |
| } |
| rdev->gart.ready = false; |
| vfree(rdev->gart.pages); |
| vfree(rdev->gart.pages_addr); |
| vfree(rdev->gart.pages_entry); |
| rdev->gart.pages = NULL; |
| rdev->gart.pages_addr = NULL; |
| rdev->gart.pages_entry = NULL; |
| |
| radeon_dummy_page_fini(rdev); |
| } |