| 25,8 → 25,8 |
|---|
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| #include "drmP.h" |
| #include "radeon_drm.h" |
| #include <drm/drmP.h> |
| #include <drm/radeon_drm.h> |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "atom.h" |
| 219,6 → 219,9 |
|---|
| } else { |
| DRM_INFO("Using generic clock info\n"); |
| |
| /* may need to be per card */ |
| rdev->clock.max_pixel_clock = 35000; |
| |
| if (rdev->flags & RADEON_IS_IGP) { |
| p1pll->reference_freq = 1432; |
| p2pll->reference_freq = 1432; |
| 331,7 → 334,7 |
|---|
| |
| if (!rdev->clock.default_sclk) |
| rdev->clock.default_sclk = radeon_get_engine_clock(rdev); |
| if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock) |
| if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock) |
| rdev->clock.default_mclk = radeon_get_memory_clock(rdev); |
| |
| rdev->pm.current_sclk = rdev->clock.default_sclk; |
| 630,7 → 633,7 |
|---|
| tmp &= ~(R300_SCLK_FORCE_VAP); |
| tmp |= RADEON_SCLK_FORCE_CP; |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| udelay(15000); |
| mdelay(15); |
| |
| tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| tmp &= ~(R300_SCLK_FORCE_TCL | |
| 648,12 → 651,12 |
|---|
| tmp |= (RADEON_ENGIN_DYNCLK_MODE | |
| (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); |
| WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); |
| udelay(15000); |
| mdelay(15); |
| |
| tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
| tmp |= RADEON_SCLK_DYN_START_CNTL; |
| WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
| udelay(15000); |
| mdelay(15); |
| |
| /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 |
| to lockup randomly, leave them as set by BIOS. |
| 693,7 → 696,7 |
|---|
| tmp |= RADEON_SCLK_MORE_FORCEON; |
| } |
| WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| udelay(15000); |
| mdelay(15); |
| } |
| |
| /* RV200::A11 A12, RV250::A11 A12 */ |
| 706,7 → 709,7 |
|---|
| tmp |= RADEON_TCL_BYPASS_DISABLE; |
| WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
| } |
| udelay(15000); |
| mdelay(15); |
| |
| /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ |
| tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 719,7 → 722,7 |
|---|
| RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
| |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| udelay(15000); |
| mdelay(15); |
| |
| tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
| 726,7 → 729,7 |
|---|
| RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| |
| WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| udelay(15000); |
| mdelay(15); |
| } |
| } else { |
| /* Turn everything OFF (ForceON to everything) */ |
| 858,7 → 861,7 |
|---|
| } |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| |
| udelay(16000); |
| mdelay(16); |
| |
| if ((rdev->family == CHIP_R300) || |
| (rdev->family == CHIP_R350)) { |
| 867,7 → 870,7 |
|---|
| R300_SCLK_FORCE_GA | |
| R300_SCLK_FORCE_CBA); |
| WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| udelay(16000); |
| mdelay(16); |
| } |
| |
| if (rdev->flags & RADEON_IS_IGP) { |
| 875,7 → 878,7 |
|---|
| tmp &= ~(RADEON_FORCEON_MCLKA | |
| RADEON_FORCEON_YCLKA); |
| WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
| udelay(16000); |
| mdelay(16); |
| } |
| |
| if ((rdev->family == CHIP_RV200) || |
| 884,7 → 887,7 |
|---|
| tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| tmp |= RADEON_SCLK_MORE_FORCEON; |
| WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| udelay(16000); |
| mdelay(16); |
| } |
| |
| tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 897,7 → 900,7 |
|---|
| RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
| |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| udelay(16000); |
| mdelay(16); |
| |
| tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |