| 45,14 → 45,21 |
|---|
| /* |
| * r100,rv100,rs100,rv200,rs200 |
| */ |
| extern int r100_init(struct radeon_device *rdev); |
| extern void r100_fini(struct radeon_device *rdev); |
| extern int r100_suspend(struct radeon_device *rdev); |
| extern int r100_resume(struct radeon_device *rdev); |
| uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
| void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| struct r100_mc_save { |
| u32 GENMO_WT; |
| u32 CRTC_EXT_CNTL; |
| u32 CRTC_GEN_CNTL; |
| u32 CRTC2_GEN_CNTL; |
| u32 CUR_OFFSET; |
| u32 CUR2_OFFSET; |
| }; |
| int r100_init(struct radeon_device *rdev); |
| void r100_fini(struct radeon_device *rdev); |
| int r100_suspend(struct radeon_device *rdev); |
| int r100_resume(struct radeon_device *rdev); |
| void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| int r100_gpu_reset(struct radeon_device *rdev); |
| bool r100_gpu_is_lockup(struct radeon_device *rdev); |
| int r100_asic_reset(struct radeon_device *rdev); |
| u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 73,7 → 80,7 |
|---|
| int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| uint32_t tiling_flags, uint32_t pitch, |
| uint32_t offset, uint32_t obj_size); |
| int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| void r100_bandwidth_update(struct radeon_device *rdev); |
| void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| int r100_ring_test(struct radeon_device *rdev); |
| 82,45 → 89,54 |
|---|
| bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| void r100_hpd_set_polarity(struct radeon_device *rdev, |
| enum radeon_hpd_id hpd); |
| int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
| int r100_debugfs_cp_init(struct radeon_device *rdev); |
| void r100_cp_disable(struct radeon_device *rdev); |
| int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
| void r100_cp_fini(struct radeon_device *rdev); |
| int r100_pci_gart_init(struct radeon_device *rdev); |
| void r100_pci_gart_fini(struct radeon_device *rdev); |
| int r100_pci_gart_enable(struct radeon_device *rdev); |
| void r100_pci_gart_disable(struct radeon_device *rdev); |
| int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
| int r100_gui_wait_for_idle(struct radeon_device *rdev); |
| void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, |
| struct radeon_cp *cp); |
| bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, |
| struct r100_gpu_lockup *lockup, |
| struct radeon_cp *cp); |
| void r100_ib_fini(struct radeon_device *rdev); |
| int r100_ib_init(struct radeon_device *rdev); |
| void r100_irq_disable(struct radeon_device *rdev); |
| void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
| void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
| void r100_vram_init_sizes(struct radeon_device *rdev); |
| int r100_cp_reset(struct radeon_device *rdev); |
| void r100_vga_render_disable(struct radeon_device *rdev); |
| void r100_restore_sanity(struct radeon_device *rdev); |
| int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| struct radeon_bo *robj); |
| int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| const unsigned *auth, unsigned n, |
| radeon_packet0_check_t check); |
| int r100_cs_packet_parse(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| unsigned idx); |
| void r100_enable_bm(struct radeon_device *rdev); |
| void r100_set_common_regs(struct radeon_device *rdev); |
| void r100_bm_disable(struct radeon_device *rdev); |
| extern bool r100_gui_idle(struct radeon_device *rdev); |
| extern void r100_pm_misc(struct radeon_device *rdev); |
| extern void r100_pm_prepare(struct radeon_device *rdev); |
| extern void r100_pm_finish(struct radeon_device *rdev); |
| extern void r100_pm_init_profile(struct radeon_device *rdev); |
| extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); |
| extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); |
| extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); |
| |
| static struct radeon_asic r100_asic = { |
| .init = &r100_init, |
| // .fini = &r100_fini, |
| // .suspend = &r100_suspend, |
| // .resume = &r100_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r100_gpu_reset, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r100_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r100_fence_ring_emit, |
| // .cs_parse = &r100_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = NULL, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| .set_memory_clock = NULL, |
| .get_pcie_lanes = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| .hpd_init = &r100_hpd_init, |
| .hpd_fini = &r100_hpd_fini, |
| .hpd_sense = &r100_hpd_sense, |
| .hpd_set_polarity = &r100_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| |
| /* |
| * r200,rv250,rs300,rv280 |
| */ |
| 129,44 → 145,8 |
|---|
| uint64_t dst_offset, |
| unsigned num_pages, |
| struct radeon_fence *fence); |
| static struct radeon_asic r200_asic = { |
| .init = &r100_init, |
| // .fini = &r100_fini, |
| // .suspend = &r100_suspend, |
| // .resume = &r100_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r100_gpu_reset, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r100_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r100_fence_ring_emit, |
| // .cs_parse = &r100_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = NULL, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| .set_memory_clock = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| .hpd_init = &r100_hpd_init, |
| .hpd_fini = &r100_hpd_fini, |
| .hpd_sense = &r100_hpd_sense, |
| .hpd_set_polarity = &r100_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| void r200_set_safe_registers(struct radeon_device *rdev); |
| |
| |
| /* |
| * r300,r350,rv350,rv380 |
| */ |
| 174,7 → 154,8 |
|---|
| extern void r300_fini(struct radeon_device *rdev); |
| extern int r300_suspend(struct radeon_device *rdev); |
| extern int r300_resume(struct radeon_device *rdev); |
| extern int r300_gpu_reset(struct radeon_device *rdev); |
| extern bool r300_gpu_is_lockup(struct radeon_device *rdev); |
| extern int r300_asic_reset(struct radeon_device *rdev); |
| extern void r300_ring_start(struct radeon_device *rdev); |
| extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| struct radeon_fence *fence); |
| 181,87 → 162,18 |
|---|
| extern int r300_cs_parse(struct radeon_cs_parser *p); |
| extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
| extern void r300_set_reg_safe(struct radeon_device *rdev); |
| extern void r300_mc_program(struct radeon_device *rdev); |
| extern void r300_mc_init(struct radeon_device *rdev); |
| extern void r300_clock_startup(struct radeon_device *rdev); |
| extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
| extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
| extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
| extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
| |
| static struct radeon_asic r300_asic = { |
| .init = &r300_init, |
| // .fini = &r300_fini, |
| // .suspend = &r300_suspend, |
| // .resume = &r300_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| .set_memory_clock = NULL, |
| .get_pcie_lanes = &rv370_get_pcie_lanes, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| .hpd_init = &r100_hpd_init, |
| .hpd_fini = &r100_hpd_fini, |
| .hpd_sense = &r100_hpd_sense, |
| .hpd_set_polarity = &r100_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| |
| |
| static struct radeon_asic r300_asic_pcie = { |
| .init = &r300_init, |
| // .fini = &r300_fini, |
| // .suspend = &r300_suspend, |
| // .resume = &r300_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| .set_memory_clock = NULL, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| .hpd_init = &r100_hpd_init, |
| .hpd_fini = &r100_hpd_fini, |
| .hpd_sense = &r100_hpd_sense, |
| .hpd_set_polarity = &r100_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| |
| /* |
| * r420,r423,rv410 |
| */ |
| 269,45 → 181,12 |
|---|
| extern void r420_fini(struct radeon_device *rdev); |
| extern int r420_suspend(struct radeon_device *rdev); |
| extern int r420_resume(struct radeon_device *rdev); |
| static struct radeon_asic r420_asic = { |
| .init = &r420_init, |
| // .fini = &r420_fini, |
| // .suspend = &r420_suspend, |
| // .resume = &r420_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = &rv370_get_pcie_lanes, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| .hpd_init = &r100_hpd_init, |
| .hpd_fini = &r100_hpd_fini, |
| .hpd_sense = &r100_hpd_sense, |
| .hpd_set_polarity = &r100_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| extern void r420_pm_init_profile(struct radeon_device *rdev); |
| extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
| extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
| extern void r420_pipes_init(struct radeon_device *rdev); |
| |
| |
| /* |
| * rs400,rs480 |
| */ |
| 319,48 → 198,16 |
|---|
| int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| static struct radeon_asic rs400_asic = { |
| .init = &rs400_init, |
| // .fini = &rs400_fini, |
| // .suspend = &rs400_suspend, |
| // .resume = &rs400_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .gart_tlb_flush = &rs400_gart_tlb_flush, |
| .gart_set_page = &rs400_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| .set_memory_clock = NULL, |
| .get_pcie_lanes = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| .hpd_init = &r100_hpd_init, |
| .hpd_fini = &r100_hpd_fini, |
| .hpd_sense = &r100_hpd_sense, |
| .hpd_set_polarity = &r100_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| int rs400_gart_init(struct radeon_device *rdev); |
| int rs400_gart_enable(struct radeon_device *rdev); |
| void rs400_gart_adjust_size(struct radeon_device *rdev); |
| void rs400_gart_disable(struct radeon_device *rdev); |
| void rs400_gart_fini(struct radeon_device *rdev); |
| |
| |
| /* |
| * rs600. |
| */ |
| extern int rs600_asic_reset(struct radeon_device *rdev); |
| extern int rs600_init(struct radeon_device *rdev); |
| extern void rs600_fini(struct radeon_device *rdev); |
| extern int rs600_suspend(struct radeon_device *rdev); |
| 367,6 → 214,7 |
|---|
| extern int rs600_resume(struct radeon_device *rdev); |
| int rs600_irq_set(struct radeon_device *rdev); |
| int rs600_irq_process(struct radeon_device *rdev); |
| void rs600_irq_disable(struct radeon_device *rdev); |
| u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 378,46 → 226,15 |
|---|
| bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| void rs600_hpd_set_polarity(struct radeon_device *rdev, |
| enum radeon_hpd_id hpd); |
| extern void rs600_pm_misc(struct radeon_device *rdev); |
| extern void rs600_pm_prepare(struct radeon_device *rdev); |
| extern void rs600_pm_finish(struct radeon_device *rdev); |
| extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); |
| extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); |
| void rs600_set_safe_registers(struct radeon_device *rdev); |
| |
| static struct radeon_asic rs600_asic = { |
| .init = &rs600_init, |
| // .fini = &rs600_fini, |
| // .suspend = &rs600_suspend, |
| // .resume = &rs600_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .gart_tlb_flush = &rs600_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &rs600_bandwidth_update, |
| .hpd_init = &rs600_hpd_init, |
| .hpd_fini = &rs600_hpd_fini, |
| .hpd_sense = &rs600_hpd_sense, |
| .hpd_set_polarity = &rs600_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| |
| |
| /* |
| * rs690,rs740 |
| */ |
| 428,96 → 245,36 |
|---|
| uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rs690_bandwidth_update(struct radeon_device *rdev); |
| static struct radeon_asic rs690_asic = { |
| .init = &rs690_init, |
| // .fini = &rs690_fini, |
| // .suspend = &rs690_suspend, |
| // .resume = &rs690_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .gart_tlb_flush = &rs400_gart_tlb_flush, |
| .gart_set_page = &rs400_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r300_copy_dma, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &rs690_bandwidth_update, |
| .hpd_init = &rs600_hpd_init, |
| .hpd_fini = &rs600_hpd_fini, |
| .hpd_sense = &rs600_hpd_sense, |
| .hpd_set_polarity = &rs600_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| struct drm_display_mode *mode1, |
| struct drm_display_mode *mode2); |
| |
| |
| /* |
| * rv515 |
| */ |
| struct rv515_mc_save { |
| u32 d1vga_control; |
| u32 d2vga_control; |
| u32 vga_render_control; |
| u32 vga_hdp_control; |
| u32 d1crtc_control; |
| u32 d2crtc_control; |
| }; |
| int rv515_init(struct radeon_device *rdev); |
| void rv515_fini(struct radeon_device *rdev); |
| int rv515_gpu_reset(struct radeon_device *rdev); |
| uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rv515_ring_start(struct radeon_device *rdev); |
| uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rv515_bandwidth_update(struct radeon_device *rdev); |
| int rv515_resume(struct radeon_device *rdev); |
| int rv515_suspend(struct radeon_device *rdev); |
| static struct radeon_asic rv515_asic = { |
| .init = &rv515_init, |
| // .fini = &rv515_fini, |
| // .suspend = &rv515_suspend, |
| // .resume = &rv515_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &rv515_gpu_reset, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &rv515_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = &rv370_get_pcie_lanes, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &rv515_bandwidth_update, |
| .hpd_init = &rs600_hpd_init, |
| .hpd_fini = &rs600_hpd_fini, |
| .hpd_sense = &rs600_hpd_sense, |
| .hpd_set_polarity = &rs600_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
| void rv515_vga_render_disable(struct radeon_device *rdev); |
| void rv515_set_safe_registers(struct radeon_device *rdev); |
| void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
| void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
| void rv515_clock_startup(struct radeon_device *rdev); |
| void rv515_debugfs(struct radeon_device *rdev); |
| |
| |
| /* |
| 525,43 → 282,6 |
|---|
| */ |
| int r520_init(struct radeon_device *rdev); |
| int r520_resume(struct radeon_device *rdev); |
| static struct radeon_asic r520_asic = { |
| .init = &r520_init, |
| // .fini = &rv515_fini, |
| // .suspend = &rv515_suspend, |
| // .resume = &r520_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &rv515_gpu_reset, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &rv515_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = &rv370_get_pcie_lanes, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &rv515_bandwidth_update, |
| .hpd_init = &rs600_hpd_init, |
| .hpd_fini = &rs600_hpd_fini, |
| .hpd_sense = &rs600_hpd_sense, |
| .hpd_set_polarity = &rs600_hpd_set_polarity, |
| .ioctl_wait_idle = NULL, |
| }; |
| |
| /* |
| * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
| 580,18 → 300,13 |
|---|
| int r600_cs_parse(struct radeon_cs_parser *p); |
| void r600_fence_ring_emit(struct radeon_device *rdev, |
| struct radeon_fence *fence); |
| int r600_copy_dma(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| unsigned num_pages, |
| struct radeon_fence *fence); |
| int r600_irq_process(struct radeon_device *rdev); |
| int r600_irq_set(struct radeon_device *rdev); |
| int r600_gpu_reset(struct radeon_device *rdev); |
| bool r600_gpu_is_lockup(struct radeon_device *rdev); |
| int r600_asic_reset(struct radeon_device *rdev); |
| int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| uint32_t tiling_flags, uint32_t pitch, |
| uint32_t offset, uint32_t obj_size); |
| int r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| int r600_ib_test(struct radeon_device *rdev); |
| void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| int r600_ring_test(struct radeon_device *rdev); |
| int r600_copy_blit(struct radeon_device *rdev, |
| 603,43 → 318,58 |
|---|
| void r600_hpd_set_polarity(struct radeon_device *rdev, |
| enum radeon_hpd_id hpd); |
| extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
| extern bool r600_gui_idle(struct radeon_device *rdev); |
| extern void r600_pm_misc(struct radeon_device *rdev); |
| extern void r600_pm_init_profile(struct radeon_device *rdev); |
| extern void rs780_pm_init_profile(struct radeon_device *rdev); |
| extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); |
| extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| extern int r600_get_pcie_lanes(struct radeon_device *rdev); |
| bool r600_card_posted(struct radeon_device *rdev); |
| void r600_cp_stop(struct radeon_device *rdev); |
| int r600_cp_start(struct radeon_device *rdev); |
| void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| int r600_cp_resume(struct radeon_device *rdev); |
| void r600_cp_fini(struct radeon_device *rdev); |
| int r600_count_pipe_bits(uint32_t val); |
| int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| int r600_pcie_gart_init(struct radeon_device *rdev); |
| void r600_scratch_init(struct radeon_device *rdev); |
| int r600_blit_init(struct radeon_device *rdev); |
| void r600_blit_fini(struct radeon_device *rdev); |
| int r600_init_microcode(struct radeon_device *rdev); |
| /* r600 irq */ |
| int r600_irq_process(struct radeon_device *rdev); |
| int r600_irq_init(struct radeon_device *rdev); |
| void r600_irq_fini(struct radeon_device *rdev); |
| void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| int r600_irq_set(struct radeon_device *rdev); |
| void r600_irq_suspend(struct radeon_device *rdev); |
| void r600_disable_interrupts(struct radeon_device *rdev); |
| void r600_rlc_stop(struct radeon_device *rdev); |
| /* r600 audio */ |
| int r600_audio_init(struct radeon_device *rdev); |
| int r600_audio_tmds_index(struct drm_encoder *encoder); |
| void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
| int r600_audio_channels(struct radeon_device *rdev); |
| int r600_audio_bits_per_sample(struct radeon_device *rdev); |
| int r600_audio_rate(struct radeon_device *rdev); |
| uint8_t r600_audio_status_bits(struct radeon_device *rdev); |
| uint8_t r600_audio_category_code(struct radeon_device *rdev); |
| void r600_audio_schedule_polling(struct radeon_device *rdev); |
| void r600_audio_enable_polling(struct drm_encoder *encoder); |
| void r600_audio_disable_polling(struct drm_encoder *encoder); |
| void r600_audio_fini(struct radeon_device *rdev); |
| void r600_hdmi_init(struct drm_encoder *encoder); |
| int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
| void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); |
| /* r600 blit */ |
| int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
| void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
| void r600_kms_blit_copy(struct radeon_device *rdev, |
| u64 src_gpu_addr, u64 dst_gpu_addr, |
| int size_bytes); |
| |
| static struct radeon_asic r600_asic = { |
| .init = &r600_init, |
| // .fini = &r600_fini, |
| // .suspend = &r600_suspend, |
| // .resume = &r600_resume, |
| .cp_commit = &r600_cp_commit, |
| .vga_set_state = &r600_vga_set_state, |
| .gpu_reset = &r600_gpu_reset, |
| .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = &r600_ring_test, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| // .irq_set = &r600_irq_set, |
| // .irq_process = &r600_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = &rv370_get_pcie_lanes, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = NULL, |
| .set_surface_reg = r600_set_surface_reg, |
| .clear_surface_reg = r600_clear_surface_reg, |
| .bandwidth_update = &rv515_bandwidth_update, |
| .hpd_init = &r600_hpd_init, |
| .hpd_fini = &r600_hpd_fini, |
| .hpd_sense = &r600_hpd_sense, |
| .hpd_set_polarity = &r600_hpd_set_polarity, |
| // .ioctl_wait_idle = r600_ioctl_wait_idle, |
| }; |
| |
| /* |
| * rv770,rv730,rv710,rv740 |
| */ |
| 647,90 → 377,67 |
|---|
| void rv770_fini(struct radeon_device *rdev); |
| int rv770_suspend(struct radeon_device *rdev); |
| int rv770_resume(struct radeon_device *rdev); |
| int rv770_gpu_reset(struct radeon_device *rdev); |
| void rv770_pm_misc(struct radeon_device *rdev); |
| u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
| void r700_cp_stop(struct radeon_device *rdev); |
| void r700_cp_fini(struct radeon_device *rdev); |
| |
| static struct radeon_asic rv770_asic = { |
| .init = &rv770_init, |
| // .fini = &rv770_fini, |
| // .suspend = &rv770_suspend, |
| // .resume = &rv770_resume, |
| .cp_commit = &r600_cp_commit, |
| .gpu_reset = &rv770_gpu_reset, |
| .vga_set_state = &r600_vga_set_state, |
| .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = &r600_ring_test, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| // .irq_set = &r600_irq_set, |
| // .irq_process = &r600_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = &rv370_get_pcie_lanes, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r600_set_surface_reg, |
| .clear_surface_reg = r600_clear_surface_reg, |
| .bandwidth_update = &rv515_bandwidth_update, |
| .hpd_init = &r600_hpd_init, |
| .hpd_fini = &r600_hpd_fini, |
| .hpd_sense = &r600_hpd_sense, |
| .hpd_set_polarity = &r600_hpd_set_polarity, |
| }; |
| |
| /* |
| * evergreen |
| */ |
| struct evergreen_mc_save { |
| u32 vga_control[6]; |
| u32 vga_render_control; |
| u32 vga_hdp_control; |
| u32 crtc_control[6]; |
| }; |
| void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| int evergreen_init(struct radeon_device *rdev); |
| void evergreen_fini(struct radeon_device *rdev); |
| int evergreen_suspend(struct radeon_device *rdev); |
| int evergreen_resume(struct radeon_device *rdev); |
| int evergreen_gpu_reset(struct radeon_device *rdev); |
| bool evergreen_gpu_is_lockup(struct radeon_device *rdev); |
| int evergreen_asic_reset(struct radeon_device *rdev); |
| void evergreen_bandwidth_update(struct radeon_device *rdev); |
| void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| int evergreen_copy_blit(struct radeon_device *rdev, |
| uint64_t src_offset, uint64_t dst_offset, |
| unsigned num_pages, struct radeon_fence *fence); |
| void evergreen_hpd_init(struct radeon_device *rdev); |
| void evergreen_hpd_fini(struct radeon_device *rdev); |
| bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| void evergreen_hpd_set_polarity(struct radeon_device *rdev, |
| enum radeon_hpd_id hpd); |
| u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| int evergreen_irq_set(struct radeon_device *rdev); |
| int evergreen_irq_process(struct radeon_device *rdev); |
| extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
| extern void evergreen_pm_misc(struct radeon_device *rdev); |
| extern void evergreen_pm_prepare(struct radeon_device *rdev); |
| extern void evergreen_pm_finish(struct radeon_device *rdev); |
| extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); |
| extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); |
| void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| int evergreen_blit_init(struct radeon_device *rdev); |
| void evergreen_blit_fini(struct radeon_device *rdev); |
| /* evergreen blit */ |
| int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
| void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
| void evergreen_kms_blit_copy(struct radeon_device *rdev, |
| u64 src_gpu_addr, u64 dst_gpu_addr, |
| int size_bytes); |
| |
| static struct radeon_asic evergreen_asic = { |
| .init = &evergreen_init, |
| // .fini = &evergreen_fini, |
| // .suspend = &evergreen_suspend, |
| // .resume = &evergreen_resume, |
| .cp_commit = NULL, |
| .gpu_reset = &evergreen_gpu_reset, |
| .vga_set_state = &r600_vga_set_state, |
| .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = NULL, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| // .irq_set = &r600_irq_set, |
| // .irq_process = &r600_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = NULL, |
| .set_surface_reg = r600_set_surface_reg, |
| .clear_surface_reg = r600_clear_surface_reg, |
| .bandwidth_update = &evergreen_bandwidth_update, |
| .hpd_init = &evergreen_hpd_init, |
| .hpd_fini = &evergreen_hpd_fini, |
| .hpd_sense = &evergreen_hpd_sense, |
| .hpd_set_polarity = &evergreen_hpd_set_polarity, |
| }; |
| /* |
| * cayman |
| */ |
| void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| int cayman_init(struct radeon_device *rdev); |
| void cayman_fini(struct radeon_device *rdev); |
| int cayman_suspend(struct radeon_device *rdev); |
| int cayman_resume(struct radeon_device *rdev); |
| bool cayman_gpu_is_lockup(struct radeon_device *rdev); |
| int cayman_asic_reset(struct radeon_device *rdev); |
| |
| #endif |