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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /drivers/video/drm/radeon/radeon_asic.h @ 1411

  → /drivers/video/drm/radeon/radeon_asic.h @ 1412

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Regard whitespace Rev 1411 → Rev 1412

/drivers/video/drm/radeon/radeon_asic.h
93,8 → 93,8
.gart_tlb_flush = &r100_pci_gart_tlb_flush,
.gart_set_page = &r100_pci_gart_set_page,
.cp_commit = &r100_cp_commit,
// .ring_start = &r100_ring_start,
// .ring_test = &r100_ring_test,
.ring_start = &r100_ring_start,
.ring_test = &r100_ring_test,
// .ring_ib_execute = &r100_ring_ib_execute,
// .irq_set = &r100_irq_set,
// .irq_process = &r100_irq_process,
152,9 → 152,9
.gpu_reset = &r300_gpu_reset,
.gart_tlb_flush = &r100_pci_gart_tlb_flush,
.gart_set_page = &r100_pci_gart_set_page,
// .cp_commit = &r100_cp_commit,
// .ring_start = &r300_ring_start,
// .ring_test = &r100_ring_test,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
// .ring_ib_execute = &r100_ring_ib_execute,
// .irq_set = &r100_irq_set,
// .irq_process = &r100_irq_process,
196,9 → 196,9
.gpu_reset = &r300_gpu_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
// .cp_commit = &r100_cp_commit,
// .ring_start = &r300_ring_start,
// .ring_test = &r100_ring_test,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
// .ring_ib_execute = &r100_ring_ib_execute,
// .irq_set = &r100_irq_set,
// .irq_process = &r100_irq_process,
245,9 → 245,9
.gpu_reset = &r300_gpu_reset,
.gart_tlb_flush = &rs400_gart_tlb_flush,
.gart_set_page = &rs400_gart_set_page,
// .cp_commit = &r100_cp_commit,
// .ring_start = &r300_ring_start,
// .ring_test = &r100_ring_test,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
// .ring_ib_execute = &r100_ring_ib_execute,
// .irq_set = &r100_irq_set,
// .irq_process = &r100_irq_process,
304,9 → 304,9
.gpu_reset = &r300_gpu_reset,
.gart_tlb_flush = &rs600_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page,
// .cp_commit = &r100_cp_commit,
// .ring_start = &r300_ring_start,
// .ring_test = &r100_ring_test,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
// .ring_ib_execute = &r100_ring_ib_execute,
// .irq_set = &rs600_irq_set,
// .irq_process = &rs600_irq_process,
350,9 → 350,9
.gpu_reset = &r300_gpu_reset,
.gart_tlb_flush = &rs400_gart_tlb_flush,
.gart_set_page = &rs400_gart_set_page,
// .cp_commit = &r100_cp_commit,
// .ring_start = &r300_ring_start,
// .ring_test = &r100_ring_test,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
// .ring_ib_execute = &r100_ring_ib_execute,
// .irq_set = &rs600_irq_set,
// .irq_process = &rs600_irq_process,
402,9 → 402,9
.gpu_reset = &rv515_gpu_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
// .cp_commit = &r100_cp_commit,
// .ring_start = &rv515_ring_start,
// .ring_test = &r100_ring_test,
.cp_commit = &r100_cp_commit,
.ring_start = &rv515_ring_start,
.ring_test = &r100_ring_test,
// .ring_ib_execute = &r100_ring_ib_execute,
// .irq_set = &rs600_irq_set,
// .irq_process = &rs600_irq_process,
445,9 → 445,9
.gpu_reset = &rv515_gpu_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
// .cp_commit = &r100_cp_commit,
// .ring_start = &rv515_ring_start,
// .ring_test = &r100_ring_test,
.cp_commit = &r100_cp_commit,
.ring_start = &rv515_ring_start,
.ring_test = &r100_ring_test,
// .ring_ib_execute = &r100_ring_ib_execute,
// .irq_set = &rs600_irq_set,
// .irq_process = &rs600_irq_process,