23,30 → 23,20 |
* |
*/ |
|
#include "drmP.h" |
#include "drm.h" |
#include "radeon_drm.h" |
#include <drm/drmP.h> |
#include <drm/radeon_drm.h> |
#include "radeon.h" |
|
#include "r600d.h" |
#include "r600_blit_shaders.h" |
#include "radeon_blit_common.h" |
|
#define DI_PT_RECTLIST 0x11 |
#define DI_INDEX_SIZE_16_BIT 0x0 |
#define DI_SRC_SEL_AUTO_INDEX 0x2 |
|
#define FMT_8 0x1 |
#define FMT_5_6_5 0x8 |
#define FMT_8_8_8_8 0x1a |
#define COLOR_8 0x1 |
#define COLOR_5_6_5 0x8 |
#define COLOR_8_8_8_8 0x1a |
|
/* emits 21 on rv770+, 23 on r600 */ |
static void |
set_render_target(struct radeon_device *rdev, int format, |
int w, int h, u64 gpu_addr) |
{ |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
u32 cb_color_info; |
int pitch, slice; |
|
54,42 → 44,44 |
if (h < 8) |
h = 8; |
|
cb_color_info = ((format << 2) | (1 << 27) | (1 << 8)); |
cb_color_info = CB_FORMAT(format) | |
CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) | |
CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); |
pitch = (w / 8) - 1; |
slice = ((w * h) / 64) - 1; |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, gpu_addr >> 8); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, gpu_addr >> 8); |
|
if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { |
radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
radeon_ring_write(rdev, 2 << 0); |
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
radeon_ring_write(ring, 2 << 0); |
} |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, (pitch << 0) | (slice << 10)); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, 0); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, cb_color_info); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, cb_color_info); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, 0); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, 0); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, 0); |
} |
|
/* emits 5dw */ |
98,6 → 90,7 |
u32 sync_type, u32 size, |
u64 mc_addr) |
{ |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
u32 cp_coher_size; |
|
if (size == 0xffffffff) |
105,11 → 98,11 |
else |
cp_coher_size = ((size + 255) >> 8); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
radeon_ring_write(rdev, sync_type); |
radeon_ring_write(rdev, cp_coher_size); |
radeon_ring_write(rdev, mc_addr >> 8); |
radeon_ring_write(rdev, 10); /* poll interval */ |
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
radeon_ring_write(ring, sync_type); |
radeon_ring_write(ring, cp_coher_size); |
radeon_ring_write(ring, mc_addr >> 8); |
radeon_ring_write(ring, 10); /* poll interval */ |
} |
|
/* emits 21dw + 1 surface sync = 26dw */ |
116,6 → 109,7 |
static void |
set_shaders(struct radeon_device *rdev) |
{ |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
u64 gpu_addr; |
u32 sq_pgm_resources; |
|
124,35 → 118,35 |
|
/* VS */ |
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, gpu_addr >> 8); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, gpu_addr >> 8); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, sq_pgm_resources); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, sq_pgm_resources); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, 0); |
|
/* PS */ |
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, gpu_addr >> 8); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, gpu_addr >> 8); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, sq_pgm_resources | (1 << 28)); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, 2); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, 2); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, 0); |
|
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
162,22 → 156,24 |
static void |
set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
{ |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
u32 sq_vtx_constant_word2; |
|
sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); |
sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | |
SQ_VTXC_STRIDE(16); |
#ifdef __BIG_ENDIAN |
sq_vtx_constant_word2 |= (2 << 30); |
sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32); |
#endif |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
radeon_ring_write(rdev, 0x460); |
radeon_ring_write(rdev, gpu_addr & 0xffffffff); |
radeon_ring_write(rdev, 48 - 1); |
radeon_ring_write(rdev, sq_vtx_constant_word2); |
radeon_ring_write(rdev, 1 << 0); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7)); |
radeon_ring_write(ring, 0x460); |
radeon_ring_write(ring, gpu_addr & 0xffffffff); |
radeon_ring_write(ring, 48 - 1); |
radeon_ring_write(ring, sq_vtx_constant_word2); |
radeon_ring_write(ring, 1 << 0); |
radeon_ring_write(ring, 0); |
radeon_ring_write(ring, 0); |
radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30); |
|
if ((rdev->family == CHIP_RV610) || |
(rdev->family == CHIP_RV620) || |
195,35 → 191,40 |
static void |
set_tex_resource(struct radeon_device *rdev, |
int format, int w, int h, int pitch, |
u64 gpu_addr) |
u64 gpu_addr, u32 size) |
{ |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; |
|
if (h < 1) |
h = 1; |
|
sq_tex_resource_word0 = (1 << 0) | (1 << 3); |
sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | |
((w - 1) << 19)); |
sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) | |
S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); |
sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) | |
S_038000_TEX_WIDTH(w - 1); |
|
sq_tex_resource_word1 = (format << 26); |
sq_tex_resource_word1 |= ((h - 1) << 0); |
sq_tex_resource_word1 = S_038004_DATA_FORMAT(format); |
sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1); |
|
sq_tex_resource_word4 = ((1 << 14) | |
(0 << 16) | |
(1 << 19) | |
(2 << 22) | |
(3 << 25)); |
sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) | |
S_038010_DST_SEL_X(SQ_SEL_X) | |
S_038010_DST_SEL_Y(SQ_SEL_Y) | |
S_038010_DST_SEL_Z(SQ_SEL_Z) | |
S_038010_DST_SEL_W(SQ_SEL_W); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(rdev, sq_tex_resource_word0); |
radeon_ring_write(rdev, sq_tex_resource_word1); |
radeon_ring_write(rdev, gpu_addr >> 8); |
radeon_ring_write(rdev, gpu_addr >> 8); |
radeon_ring_write(rdev, sq_tex_resource_word4); |
radeon_ring_write(rdev, 0); |
radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); |
cp_set_surface_sync(rdev, |
PACKET3_TC_ACTION_ENA, size, gpu_addr); |
|
radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7)); |
radeon_ring_write(ring, 0); |
radeon_ring_write(ring, sq_tex_resource_word0); |
radeon_ring_write(ring, sq_tex_resource_word1); |
radeon_ring_write(ring, gpu_addr >> 8); |
radeon_ring_write(ring, gpu_addr >> 8); |
radeon_ring_write(ring, sq_tex_resource_word4); |
radeon_ring_write(ring, 0); |
radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30); |
} |
|
/* emits 12 */ |
231,20 → 232,21 |
set_scissors(struct radeon_device *rdev, int x1, int y1, |
int x2, int y2) |
{ |
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, (x1 << 0) | (y1 << 16)); |
radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); |
radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); |
radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
} |
|
/* emits 10 */ |
251,23 → 253,24 |
static void |
draw_auto(struct radeon_device *rdev) |
{ |
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, DI_PT_RECTLIST); |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
radeon_ring_write(ring, DI_PT_RECTLIST); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
radeon_ring_write(rdev, |
radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0)); |
radeon_ring_write(ring, |
#ifdef __BIG_ENDIAN |
(2 << 2) | |
#endif |
DI_INDEX_SIZE_16_BIT); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
radeon_ring_write(rdev, 1); |
radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
radeon_ring_write(ring, 1); |
|
radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
radeon_ring_write(rdev, 3); |
radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
radeon_ring_write(ring, 3); |
radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX); |
|
} |
|
275,6 → 278,7 |
static void |
set_default_state(struct radeon_device *rdev) |
{ |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; |
u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; |
int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; |
430,51 → 434,26 |
/* emit an IB pointing at default state */ |
dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
radeon_ring_write(rdev, |
radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
radeon_ring_write(ring, |
#ifdef __BIG_ENDIAN |
(2 << 0) | |
#endif |
(gpu_addr & 0xFFFFFFFC)); |
radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
radeon_ring_write(rdev, dwords); |
radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF); |
radeon_ring_write(ring, dwords); |
|
/* SQ config */ |
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
radeon_ring_write(rdev, sq_config); |
radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
radeon_ring_write(rdev, sq_thread_resource_mgmt); |
radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
radeon_ring_write(ring, sq_config); |
radeon_ring_write(ring, sq_gpr_resource_mgmt_1); |
radeon_ring_write(ring, sq_gpr_resource_mgmt_2); |
radeon_ring_write(ring, sq_thread_resource_mgmt); |
radeon_ring_write(ring, sq_stack_resource_mgmt_1); |
radeon_ring_write(ring, sq_stack_resource_mgmt_2); |
} |
|
static inline uint32_t i2f(uint32_t input) |
{ |
u32 result, i, exponent, fraction; |
|
if ((input & 0x3fff) == 0) |
result = 0; /* 0 is a special case */ |
else { |
exponent = 140; /* exponent biased by 127; */ |
fraction = (input & 0x3fff) << 10; /* cheat and only |
handle numbers below 2^^15 */ |
for (i = 0; i < 14; i++) { |
if (fraction & 0x800000) |
break; |
else { |
fraction = fraction << 1; /* keep |
shifting left until top bit = 1 */ |
exponent = exponent - 1; |
} |
} |
result = exponent << 23 | (fraction & 0x7fffff); /* mask |
off top bit; assumed 1 */ |
} |
return result; |
} |
|
int r600_blit_init(struct radeon_device *rdev) |
{ |
u32 obj_size; |
483,11 → 462,27 |
u32 packet2s[16]; |
int num_packet2s = 0; |
|
/* pin copy shader into vram if already initialized */ |
if (rdev->r600_blit.shader_obj) |
goto done; |
rdev->r600_blit.primitives.set_render_target = set_render_target; |
rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync; |
rdev->r600_blit.primitives.set_shaders = set_shaders; |
rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource; |
rdev->r600_blit.primitives.set_tex_resource = set_tex_resource; |
rdev->r600_blit.primitives.set_scissors = set_scissors; |
rdev->r600_blit.primitives.draw_auto = draw_auto; |
rdev->r600_blit.primitives.set_default_state = set_default_state; |
|
mutex_init(&rdev->r600_blit.mutex); |
rdev->r600_blit.ring_size_common = 8; /* sync semaphore */ |
rdev->r600_blit.ring_size_common += 40; /* shaders + def state */ |
rdev->r600_blit.ring_size_common += 5; /* done copy */ |
rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */ |
|
rdev->r600_blit.ring_size_per_loop = 76; |
/* set_render_target emits 2 extra dwords on rv6xx */ |
if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) |
rdev->r600_blit.ring_size_per_loop += 2; |
|
rdev->r600_blit.max_dim = 8192; |
|
rdev->r600_blit.state_offset = 0; |
|
if (rdev->family >= CHIP_RV770) |
512,13 → 507,28 |
obj_size += r6xx_ps_size * 4; |
obj_size = ALIGN(obj_size, 256); |
|
r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
&rdev->r600_blit.shader_obj); |
/* pin copy shader into vram if not already initialized */ |
if (rdev->r600_blit.shader_obj == NULL) { |
r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, |
RADEON_GEM_DOMAIN_VRAM, |
NULL, &rdev->r600_blit.shader_obj); |
if (r) { |
DRM_ERROR("r600 failed to allocate shader\n"); |
return r; |
} |
|
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
if (unlikely(r != 0)) |
return r; |
r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
&rdev->r600_blit.shader_gpu_addr); |
radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
if (r) { |
dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
return r; |
} |
} |
|
DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", |
obj_size, |
rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); |
547,20 → 557,7 |
radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
|
done: |
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
if (unlikely(r != 0)) |
return r; |
r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
&rdev->r600_blit.shader_gpu_addr); |
radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
if (r) { |
dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
return r; |
} |
// radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
|
|
return 0; |
} |
|
582,263 → 579,176 |
radeon_bo_unref(&rdev->r600_blit.shader_obj); |
} |
|
static int r600_vb_ib_get(struct radeon_device *rdev) |
static unsigned r600_blit_create_rect(unsigned num_gpu_pages, |
int *width, int *height, int max_dim) |
{ |
int r; |
r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); |
if (r) { |
DRM_ERROR("failed to get IB for vertex buffer\n"); |
return r; |
} |
unsigned max_pages; |
unsigned pages = num_gpu_pages; |
int w, h; |
|
rdev->r600_blit.vb_total = 64*1024; |
rdev->r600_blit.vb_used = 0; |
return 0; |
if (num_gpu_pages == 0) { |
/* not supposed to be called with no pages, but just in case */ |
h = 0; |
w = 0; |
pages = 0; |
WARN_ON(1); |
} else { |
int rect_order = 2; |
h = RECT_UNIT_H; |
while (num_gpu_pages / rect_order) { |
h *= 2; |
rect_order *= 4; |
if (h >= max_dim) { |
h = max_dim; |
break; |
} |
} |
max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H); |
if (pages > max_pages) |
pages = max_pages; |
w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h; |
w = (w / RECT_UNIT_W) * RECT_UNIT_W; |
pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H); |
BUG_ON(pages == 0); |
} |
|
static void r600_vb_ib_put(struct radeon_device *rdev) |
{ |
radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); |
radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
|
DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages); |
|
/* return width and height only of the caller wants it */ |
if (height) |
*height = h; |
if (width) |
*width = w; |
|
return pages; |
} |
|
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) |
|
int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, |
struct radeon_fence **fence, struct radeon_sa_bo **vb, |
struct radeon_semaphore **sem) |
{ |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
int r; |
int ring_size, line_size; |
int max_size; |
/* loops of emits 64 + fence emit possible */ |
int dwords_per_loop = 76, num_loops; |
int ring_size; |
int num_loops = 0; |
int dwords_per_loop = rdev->r600_blit.ring_size_per_loop; |
|
r = r600_vb_ib_get(rdev); |
if (r) |
/* num loops */ |
while (num_gpu_pages) { |
num_gpu_pages -= |
r600_blit_create_rect(num_gpu_pages, NULL, NULL, |
rdev->r600_blit.max_dim); |
num_loops++; |
} |
|
/* 48 bytes for vertex per loop */ |
r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb, |
(num_loops*48)+256, 256, true); |
if (r) { |
return r; |
} |
|
/* set_render_target emits 2 extra dwords on rv6xx */ |
if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) |
dwords_per_loop += 2; |
r = radeon_semaphore_create(rdev, sem); |
if (r) { |
radeon_sa_bo_free(rdev, vb, NULL); |
return r; |
} |
|
/* 8 bpp vs 32 bpp for xfer unit */ |
if (size_bytes & 3) |
line_size = 8192; |
else |
line_size = 8192*4; |
|
max_size = 8192 * line_size; |
|
/* major loops cover the max size transfer */ |
num_loops = ((size_bytes + max_size) / max_size); |
/* minor loops cover the extra non aligned bits */ |
num_loops += ((size_bytes % line_size) ? 1 : 0); |
/* calculate number of loops correctly */ |
ring_size = num_loops * dwords_per_loop; |
/* set default + shaders */ |
ring_size += 40; /* shaders + def state */ |
ring_size += 10; /* fence emit for VB IB */ |
ring_size += 5; /* done copy */ |
ring_size += 10; /* fence emit for done copy */ |
r = radeon_ring_lock(rdev, ring_size); |
if (r) |
ring_size += rdev->r600_blit.ring_size_common; |
r = radeon_ring_lock(rdev, ring, ring_size); |
if (r) { |
radeon_sa_bo_free(rdev, vb, NULL); |
radeon_semaphore_free(rdev, sem, NULL); |
return r; |
} |
|
set_default_state(rdev); /* 14 */ |
set_shaders(rdev); /* 26 */ |
if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) { |
radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring, |
RADEON_RING_TYPE_GFX_INDEX); |
radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX); |
} else { |
radeon_semaphore_free(rdev, sem, NULL); |
} |
|
rdev->r600_blit.primitives.set_default_state(rdev); |
rdev->r600_blit.primitives.set_shaders(rdev); |
return 0; |
} |
|
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) |
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, |
struct radeon_sa_bo *vb, struct radeon_semaphore *sem) |
{ |
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
int r; |
|
if (rdev->r600_blit.vb_ib) |
r600_vb_ib_put(rdev); |
r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
if (r) { |
radeon_ring_unlock_undo(rdev, ring); |
return; |
} |
|
if (fence) |
r = radeon_fence_emit(rdev, fence); |
|
radeon_ring_unlock_commit(rdev); |
radeon_ring_unlock_commit(rdev, ring); |
radeon_sa_bo_free(rdev, &vb, *fence); |
radeon_semaphore_free(rdev, &sem, *fence); |
} |
|
void r600_kms_blit_copy(struct radeon_device *rdev, |
u64 src_gpu_addr, u64 dst_gpu_addr, |
int size_bytes) |
unsigned num_gpu_pages, |
struct radeon_sa_bo *vb) |
{ |
int max_bytes; |
u64 vb_gpu_addr; |
u32 *vb; |
u32 *vb_cpu_addr; |
|
DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, |
size_bytes, rdev->r600_blit.vb_used); |
vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); |
if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { |
max_bytes = 8192; |
DRM_DEBUG("emitting copy %16llx %16llx %d\n", |
src_gpu_addr, dst_gpu_addr, num_gpu_pages); |
vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb); |
vb_gpu_addr = radeon_sa_bo_gpu_addr(vb); |
|
while (size_bytes) { |
int cur_size = size_bytes; |
int src_x = src_gpu_addr & 255; |
int dst_x = dst_gpu_addr & 255; |
int h = 1; |
src_gpu_addr = src_gpu_addr & ~255ULL; |
dst_gpu_addr = dst_gpu_addr & ~255ULL; |
while (num_gpu_pages) { |
int w, h; |
unsigned size_in_bytes; |
unsigned pages_per_loop = |
r600_blit_create_rect(num_gpu_pages, &w, &h, |
rdev->r600_blit.max_dim); |
|
if (!src_x && !dst_x) { |
h = (cur_size / max_bytes); |
if (h > 8192) |
h = 8192; |
if (h == 0) |
h = 1; |
else |
cur_size = max_bytes; |
} else { |
if (cur_size > max_bytes) |
cur_size = max_bytes; |
if (cur_size > (max_bytes - dst_x)) |
cur_size = (max_bytes - dst_x); |
if (cur_size > (max_bytes - src_x)) |
cur_size = (max_bytes - src_x); |
} |
size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE; |
DRM_DEBUG("rectangle w=%d h=%d\n", w, h); |
|
if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
// WARN_ON(1); |
} |
vb_cpu_addr[0] = 0; |
vb_cpu_addr[1] = 0; |
vb_cpu_addr[2] = 0; |
vb_cpu_addr[3] = 0; |
|
vb[0] = i2f(dst_x); |
vb[1] = 0; |
vb[2] = i2f(src_x); |
vb[3] = 0; |
vb_cpu_addr[4] = 0; |
vb_cpu_addr[5] = int2float(h); |
vb_cpu_addr[6] = 0; |
vb_cpu_addr[7] = int2float(h); |
|
vb[4] = i2f(dst_x); |
vb[5] = i2f(h); |
vb[6] = i2f(src_x); |
vb[7] = i2f(h); |
vb_cpu_addr[8] = int2float(w); |
vb_cpu_addr[9] = int2float(h); |
vb_cpu_addr[10] = int2float(w); |
vb_cpu_addr[11] = int2float(h); |
|
vb[8] = i2f(dst_x + cur_size); |
vb[9] = i2f(h); |
vb[10] = i2f(src_x + cur_size); |
vb[11] = i2f(h); |
|
/* src 9 */ |
set_tex_resource(rdev, FMT_8, |
src_x + cur_size, h, src_x + cur_size, |
src_gpu_addr); |
|
/* 5 */ |
cp_set_surface_sync(rdev, |
PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
|
/* dst 23 */ |
set_render_target(rdev, COLOR_8, |
dst_x + cur_size, h, |
dst_gpu_addr); |
|
/* scissors 12 */ |
set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); |
|
/* 14 */ |
vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
set_vtx_resource(rdev, vb_gpu_addr); |
|
/* draw 10 */ |
draw_auto(rdev); |
|
/* 5 */ |
cp_set_surface_sync(rdev, |
rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8, |
w, h, w, src_gpu_addr, size_in_bytes); |
rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8, |
w, h, dst_gpu_addr); |
rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h); |
rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr); |
rdev->r600_blit.primitives.draw_auto(rdev); |
rdev->r600_blit.primitives.cp_set_surface_sync(rdev, |
PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
cur_size * h, dst_gpu_addr); |
size_in_bytes, dst_gpu_addr); |
|
vb += 12; |
rdev->r600_blit.vb_used += 12 * 4; |
|
src_gpu_addr += cur_size * h; |
dst_gpu_addr += cur_size * h; |
size_bytes -= cur_size * h; |
vb_cpu_addr += 12; |
vb_gpu_addr += 4*12; |
src_gpu_addr += size_in_bytes; |
dst_gpu_addr += size_in_bytes; |
num_gpu_pages -= pages_per_loop; |
} |
} else { |
max_bytes = 8192 * 4; |
|
while (size_bytes) { |
int cur_size = size_bytes; |
int src_x = (src_gpu_addr & 255); |
int dst_x = (dst_gpu_addr & 255); |
int h = 1; |
src_gpu_addr = src_gpu_addr & ~255ULL; |
dst_gpu_addr = dst_gpu_addr & ~255ULL; |
|
if (!src_x && !dst_x) { |
h = (cur_size / max_bytes); |
if (h > 8192) |
h = 8192; |
if (h == 0) |
h = 1; |
else |
cur_size = max_bytes; |
} else { |
if (cur_size > max_bytes) |
cur_size = max_bytes; |
if (cur_size > (max_bytes - dst_x)) |
cur_size = (max_bytes - dst_x); |
if (cur_size > (max_bytes - src_x)) |
cur_size = (max_bytes - src_x); |
} |
|
if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
// WARN_ON(1); |
} |
|
vb[0] = i2f(dst_x / 4); |
vb[1] = 0; |
vb[2] = i2f(src_x / 4); |
vb[3] = 0; |
|
vb[4] = i2f(dst_x / 4); |
vb[5] = i2f(h); |
vb[6] = i2f(src_x / 4); |
vb[7] = i2f(h); |
|
vb[8] = i2f((dst_x + cur_size) / 4); |
vb[9] = i2f(h); |
vb[10] = i2f((src_x + cur_size) / 4); |
vb[11] = i2f(h); |
|
/* src 9 */ |
set_tex_resource(rdev, FMT_8_8_8_8, |
(src_x + cur_size) / 4, |
h, (src_x + cur_size) / 4, |
src_gpu_addr); |
/* 5 */ |
cp_set_surface_sync(rdev, |
PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
|
/* dst 23 */ |
set_render_target(rdev, COLOR_8_8_8_8, |
(dst_x + cur_size) / 4, h, |
dst_gpu_addr); |
|
/* scissors 12 */ |
set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); |
|
/* Vertex buffer setup 14 */ |
vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
set_vtx_resource(rdev, vb_gpu_addr); |
|
/* draw 10 */ |
draw_auto(rdev); |
|
/* 5 */ |
cp_set_surface_sync(rdev, |
PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
cur_size * h, dst_gpu_addr); |
|
/* 78 ring dwords per loop */ |
vb += 12; |
rdev->r600_blit.vb_used += 12 * 4; |
|
src_gpu_addr += cur_size * h; |
dst_gpu_addr += cur_size * h; |
size_bytes -= cur_size * h; |
} |
} |
} |
|
|
|