| 1871,7 → 1871,27 |
|---|
| } |
| } |
| |
| int r600_copy_blit(struct radeon_device *rdev, |
| uint64_t src_offset, uint64_t dst_offset, |
| unsigned num_pages, struct radeon_fence *fence) |
| { |
| int r; |
| |
| mutex_lock(&rdev->r600_blit.mutex); |
| rdev->r600_blit.vb_ib = NULL; |
| r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); |
| if (r) { |
| // if (rdev->r600_blit.vb_ib) |
| // radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
| mutex_unlock(&rdev->r600_blit.mutex); |
| return r; |
| } |
| r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); |
| r600_blit_done_copy(rdev, fence); |
| mutex_unlock(&rdev->r600_blit.mutex); |
| return 0; |
| } |
| |
| int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| uint32_t tiling_flags, uint32_t pitch, |
| uint32_t offset, uint32_t obj_size) |
| 1909,7 → 1929,27 |
|---|
| return r; |
| } |
| r600_gpu_init(rdev); |
| r = r600_blit_init(rdev); |
| if (r) { |
| // r600_blit_fini(rdev); |
| rdev->asic->copy = NULL; |
| dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
| } |
| |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| |
| /* Enable IRQ */ |
| r = r600_irq_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| // radeon_irq_kms_fini(rdev); |
| return r; |
| } |
| r600_irq_set(rdev); |
| |
| r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| if (r) |
| return r; |
| 2028,19 → 2068,19 |
|---|
| rdev->accel_working = false; |
| } |
| if (rdev->accel_working) { |
| // r = radeon_ib_pool_init(rdev); |
| // if (r) { |
| // DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); |
| // rdev->accel_working = false; |
| // } |
| // r = r600_ib_test(rdev); |
| // if (r) { |
| // DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
| // rdev->accel_working = false; |
| // } |
| r = radeon_ib_pool_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| rdev->accel_working = false; |
| } else { |
| r = r600_ib_test(rdev); |
| if (r) { |
| dev_err(rdev->dev, "IB test failed (%d).\n", r); |
| rdev->accel_working = false; |
| } |
| if (r) |
| return r; /* TODO error handling */ |
| } |
| } |
| |
| return 0; |
| } |
| |
| 2423,8 → 2463,6 |
|---|
| u32 hdmi1, hdmi2; |
| u32 d1grph = 0, d2grph = 0; |
| |
| ENTER(); |
| |
| if (!rdev->irq.installed) { |
| WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
| return -EINVAL; |
| 2530,8 → 2568,6 |
|---|
| WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
| } |
| |
| LEAVE(); |
| |
| return 0; |
| } |
| |
| 2825,11 → 2861,11 |
|---|
| case 177: /* CP_INT in IB1 */ |
| case 178: /* CP_INT in IB2 */ |
| DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
| // radeon_fence_process(rdev); |
| radeon_fence_process(rdev); |
| break; |
| case 181: /* CP EOP event */ |
| DRM_DEBUG("IH: CP EOP\n"); |
| // radeon_fence_process(rdev); |
| radeon_fence_process(rdev); |
| break; |
| case 233: /* GUI IDLE */ |
| DRM_DEBUG("IH: GUI idle\n"); |