| 173,10 → 173,10 |
|---|
| rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
| return rv370_pcie_gart_enable(rdev); |
| } |
| // return r100_pci_gart_enable(rdev); |
| return r100_pci_gart_enable(rdev); |
| } |
| |
| #if 0 |
| |
| /* |
| * MC |
| */ |
| 184,9 → 184,9 |
|---|
| { |
| int r; |
| |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| // if (r100_debugfs_rbbm_init(rdev)) { |
| // DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| // } |
| |
| r300_gpu_init(rdev); |
| r100_pci_gart_disable(rdev); |
| 264,6 → 264,8 |
|---|
| } |
| |
| |
| #if 0 |
| |
| /* |
| * Global GPU functions |
| */ |
| 311,6 → 313,8 |
|---|
| return r; |
| } |
| |
| #endif |
| |
| void r300_ring_start(struct radeon_device *rdev) |
| { |
| unsigned gb_tile_config; |
| 714,6 → 718,7 |
|---|
| } |
| |
| |
| #if 0 |
| /* |
| * CS functions |
| */ |
| 968,6 → 973,8 |
|---|
| } |
| } |
| |
| #endif |
| |
| static const unsigned r300_reg_safe_bm[159] = { |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF, |
| 1011,6 → 1018,8 |
|---|
| 0x0003FC01, 0xFFFFFFF8, 0xFE800B19, |
| }; |
| |
| #if 0 |
| |
| static int r300_packet0_check(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| unsigned idx, unsigned reg) |
| 1524,6 → 1533,8 |
|---|
| return 0; |
| } |
| |
| #endif |
| |
| int r300_init(struct radeon_device *rdev) |
| { |
| rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
| 1532,4 → 1543,3 |
|---|
| } |
| |
| |
| #endif |