| 34,8 → 34,6 |
|---|
| #include "r100d.h" |
| #include "r200_reg_safe.h" |
| |
| #if 0 |
| |
| #include "r100_track.h" |
| |
| static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) |
| 81,7 → 79,6 |
|---|
| vtx_size += 3; |
| return vtx_size; |
| } |
| #endif |
| |
| int r200_copy_dma(struct radeon_device *rdev, |
| uint64_t src_offset, |
| 124,11 → 121,11 |
|---|
| if (fence) { |
| r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
| } |
| radeon_ring_unlock_commit(rdev, ring); |
| radeon_ring_unlock_commit(rdev, ring, false); |
| return r; |
| } |
| #if 0 |
| |
| |
| static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) |
| { |
| int vtx_size, i, tex_size; |
| 188,7 → 185,7 |
|---|
| track->zb.robj = reloc->robj; |
| track->zb.offset = idx_value; |
| track->zb_dirty = true; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
| break; |
| case RADEON_RB3D_COLOROFFSET: |
| r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
| 201,7 → 198,7 |
|---|
| track->cb[0].robj = reloc->robj; |
| track->cb[0].offset = idx_value; |
| track->cb_dirty = true; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
| break; |
| case R200_PP_TXOFFSET_0: |
| case R200_PP_TXOFFSET_1: |
| 218,16 → 215,16 |
|---|
| return r; |
| } |
| if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| if (reloc->tiling_flags & RADEON_TILING_MACRO) |
| tile_flags |= R200_TXO_MACRO_TILE; |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| if (reloc->tiling_flags & RADEON_TILING_MICRO) |
| tile_flags |= R200_TXO_MICRO_TILE; |
| |
| tmp = idx_value & ~(0x7 << 2); |
| tmp |= tile_flags; |
| ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = tmp + ((u32)reloc->gpu_offset); |
| } else |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
| track->textures[i].robj = reloc->robj; |
| track->tex_dirty = true; |
| break; |
| 271,7 → 268,7 |
|---|
| return r; |
| } |
| track->textures[i].cube_info[face - 1].offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
| track->textures[i].cube_info[face - 1].robj = reloc->robj; |
| track->tex_dirty = true; |
| break; |
| 290,9 → 287,9 |
|---|
| } |
| |
| if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| if (reloc->tiling_flags & RADEON_TILING_MACRO) |
| tile_flags |= RADEON_COLOR_TILE_ENABLE; |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| if (reloc->tiling_flags & RADEON_TILING_MICRO) |
| tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
| |
| tmp = idx_value & ~(0x7 << 16); |
| 365,7 → 362,7 |
|---|
| radeon_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
| break; |
| case RADEON_PP_CNTL: |
| { |
| 543,7 → 540,6 |
|---|
| } |
| return 0; |
| } |
| #endif |
| |
| void r200_set_safe_registers(struct radeon_device *rdev) |
| { |