30,13 → 30,15 |
#include "radeon_drm.h" |
#include "radeon_reg.h" |
#include "radeon.h" |
#include "radeon_asic.h" |
|
#include "r100d.h" |
#include "r200_reg_safe.h" |
|
//#include "r100_track.h" |
#if 0 |
|
#if 0 |
#include "r100_track.h" |
|
static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) |
{ |
int vtx_size, i; |
81,6 → 83,51 |
return vtx_size; |
} |
|
int r200_copy_dma(struct radeon_device *rdev, |
uint64_t src_offset, |
uint64_t dst_offset, |
unsigned num_pages, |
struct radeon_fence *fence) |
{ |
uint32_t size; |
uint32_t cur_size; |
int i, num_loops; |
int r = 0; |
|
/* radeon pitch is /64 */ |
size = num_pages << PAGE_SHIFT; |
num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
if (r) { |
DRM_ERROR("radeon: moving bo (%d).\n", r); |
return r; |
} |
/* Must wait for 2D idle & clean before DMA or hangs might happen */ |
radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
radeon_ring_write(rdev, (1 << 16)); |
for (i = 0; i < num_loops; i++) { |
cur_size = size; |
if (cur_size > 0x1FFFFF) { |
cur_size = 0x1FFFFF; |
} |
size -= cur_size; |
radeon_ring_write(rdev, PACKET0(0x720, 2)); |
radeon_ring_write(rdev, src_offset); |
radeon_ring_write(rdev, dst_offset); |
radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
src_offset += cur_size; |
dst_offset += cur_size; |
} |
radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
if (fence) { |
r = radeon_fence_emit(rdev, fence); |
} |
radeon_ring_unlock_commit(rdev); |
return r; |
} |
|
|
static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) |
{ |
int vtx_size, i, tex_size; |
139,6 → 186,7 |
} |
track->zb.robj = reloc->robj; |
track->zb.offset = idx_value; |
track->zb_dirty = true; |
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
break; |
case RADEON_RB3D_COLOROFFSET: |
151,6 → 199,7 |
} |
track->cb[0].robj = reloc->robj; |
track->cb[0].offset = idx_value; |
track->cb_dirty = true; |
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
break; |
case R200_PP_TXOFFSET_0: |
169,6 → 218,7 |
} |
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
track->textures[i].robj = reloc->robj; |
track->tex_dirty = true; |
break; |
case R200_PP_CUBIC_OFFSET_F1_0: |
case R200_PP_CUBIC_OFFSET_F2_0: |
212,9 → 262,12 |
track->textures[i].cube_info[face - 1].offset = idx_value; |
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
track->textures[i].cube_info[face - 1].robj = reloc->robj; |
track->tex_dirty = true; |
break; |
case RADEON_RE_WIDTH_HEIGHT: |
track->maxy = ((idx_value >> 16) & 0x7FF); |
track->cb_dirty = true; |
track->zb_dirty = true; |
break; |
case RADEON_RB3D_COLORPITCH: |
r = r100_cs_packet_next_reloc(p, &reloc); |
235,9 → 288,11 |
ib[idx] = tmp; |
|
track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
track->cb_dirty = true; |
break; |
case RADEON_RB3D_DEPTHPITCH: |
track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
track->zb_dirty = true; |
break; |
case RADEON_RB3D_CNTL: |
switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
267,6 → 322,8 |
} |
|
track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
track->cb_dirty = true; |
track->zb_dirty = true; |
break; |
case RADEON_RB3D_ZSTENCILCNTL: |
switch (idx_value & 0xf) { |
284,6 → 341,7 |
default: |
break; |
} |
track->zb_dirty = true; |
break; |
case RADEON_RB3D_ZPASS_ADDR: |
r = r100_cs_packet_next_reloc(p, &reloc); |
300,6 → 358,7 |
uint32_t temp = idx_value >> 4; |
for (i = 0; i < track->num_texture; i++) |
track->textures[i].enabled = !!(temp & (1 << i)); |
track->tex_dirty = true; |
} |
break; |
case RADEON_SE_VF_CNTL: |
324,6 → 383,7 |
i = (reg - R200_PP_TXSIZE_0) / 32; |
track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
track->tex_dirty = true; |
break; |
case R200_PP_TXPITCH_0: |
case R200_PP_TXPITCH_1: |
333,6 → 393,7 |
case R200_PP_TXPITCH_5: |
i = (reg - R200_PP_TXPITCH_0) / 32; |
track->textures[i].pitch = idx_value + 32; |
track->tex_dirty = true; |
break; |
case R200_PP_TXFILTER_0: |
case R200_PP_TXFILTER_1: |
349,6 → 410,7 |
tmp = (idx_value >> 27) & 0x7; |
if (tmp == 2 || tmp == 6) |
track->textures[i].roundup_h = false; |
track->tex_dirty = true; |
break; |
case R200_PP_TXMULTI_CTL_0: |
case R200_PP_TXMULTI_CTL_1: |
370,6 → 432,8 |
/* 2D, 3D, CUBE */ |
switch (tmp) { |
case 0: |
case 3: |
case 4: |
case 5: |
case 6: |
case 7: |
385,6 → 449,7 |
track->textures[i].tex_coord_type = 1; |
break; |
} |
track->tex_dirty = true; |
break; |
case R200_PP_TXFORMAT_0: |
case R200_PP_TXFORMAT_1: |
400,11 → 465,14 |
track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
} |
if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE) |
track->textures[i].lookup_disable = true; |
switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
case R200_TXFORMAT_I8: |
case R200_TXFORMAT_RGB332: |
case R200_TXFORMAT_Y8: |
track->textures[i].cpp = 1; |
track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
break; |
case R200_TXFORMAT_AI88: |
case R200_TXFORMAT_ARGB1555: |
416,6 → 484,7 |
case R200_TXFORMAT_DVDU88: |
case R200_TXFORMAT_AVYU4444: |
track->textures[i].cpp = 2; |
track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
break; |
case R200_TXFORMAT_ARGB8888: |
case R200_TXFORMAT_RGBA8888: |
423,6 → 492,7 |
case R200_TXFORMAT_BGR111110: |
case R200_TXFORMAT_LDVDU8888: |
track->textures[i].cpp = 4; |
track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
break; |
case R200_TXFORMAT_DXT1: |
track->textures[i].cpp = 1; |
436,6 → 506,7 |
} |
track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
track->tex_dirty = true; |
break; |
case R200_PP_CUBIC_FACES_0: |
case R200_PP_CUBIC_FACES_1: |
449,6 → 520,7 |
track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
} |
track->tex_dirty = true; |
break; |
default: |
printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |