| 50,6 → 50,24 |
|---|
| #define VMID(x) (((x) & 0x7) << 0) |
| #define SRBM_STATUS 0x0E50 |
| |
| #define SRBM_SOFT_RESET 0x0E60 |
| #define SOFT_RESET_BIF (1 << 1) |
| #define SOFT_RESET_CG (1 << 2) |
| #define SOFT_RESET_DC (1 << 5) |
| #define SOFT_RESET_DMA1 (1 << 6) |
| #define SOFT_RESET_GRBM (1 << 8) |
| #define SOFT_RESET_HDP (1 << 9) |
| #define SOFT_RESET_IH (1 << 10) |
| #define SOFT_RESET_MC (1 << 11) |
| #define SOFT_RESET_RLC (1 << 13) |
| #define SOFT_RESET_ROM (1 << 14) |
| #define SOFT_RESET_SEM (1 << 15) |
| #define SOFT_RESET_VMC (1 << 17) |
| #define SOFT_RESET_DMA (1 << 20) |
| #define SOFT_RESET_TST (1 << 21) |
| #define SOFT_RESET_REGBB (1 << 22) |
| #define SOFT_RESET_ORB (1 << 23) |
| |
| #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
| #define REQUEST_TYPE(x) (((x) & 0xf) << 0) |
| #define RESPONSE_TYPE_MASK 0x000000F0 |
| 80,7 → 98,18 |
|---|
| #define VM_CONTEXT0_CNTL 0x1410 |
| #define ENABLE_CONTEXT (1 << 0) |
| #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
| #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) |
| #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
| #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) |
| #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) |
| #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) |
| #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) |
| #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) |
| #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) |
| #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) |
| #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) |
| #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) |
| #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) |
| #define VM_CONTEXT1_CNTL 0x1414 |
| #define VM_CONTEXT0_CNTL2 0x1430 |
| #define VM_CONTEXT1_CNTL2 0x1434 |
| 588,5 → 617,61 |
|---|
| #define PACKET3_SET_APPEND_CNT 0x75 |
| #define PACKET3_ME_WRITE 0x7A |
| |
| /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ |
| #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ |
| #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ |
| |
| #define DMA_RB_CNTL 0xd000 |
| # define DMA_RB_ENABLE (1 << 0) |
| # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ |
| # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ |
| # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) |
| # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ |
| # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ |
| #define DMA_RB_BASE 0xd004 |
| #define DMA_RB_RPTR 0xd008 |
| #define DMA_RB_WPTR 0xd00c |
| |
| #define DMA_RB_RPTR_ADDR_HI 0xd01c |
| #define DMA_RB_RPTR_ADDR_LO 0xd020 |
| |
| #define DMA_IB_CNTL 0xd024 |
| # define DMA_IB_ENABLE (1 << 0) |
| # define DMA_IB_SWAP_ENABLE (1 << 4) |
| # define CMD_VMID_FORCE (1 << 31) |
| #define DMA_IB_RPTR 0xd028 |
| #define DMA_CNTL 0xd02c |
| # define TRAP_ENABLE (1 << 0) |
| # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) |
| # define SEM_WAIT_INT_ENABLE (1 << 2) |
| # define DATA_SWAP_ENABLE (1 << 3) |
| # define FENCE_SWAP_ENABLE (1 << 4) |
| # define CTXEMPTY_INT_ENABLE (1 << 28) |
| #define DMA_STATUS_REG 0xd034 |
| # define DMA_IDLE (1 << 0) |
| #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 |
| #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 |
| #define DMA_TILING_CONFIG 0xd0b8 |
| #define DMA_MODE 0xd0bc |
| |
| #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ |
| (((t) & 0x1) << 23) | \ |
| (((s) & 0x1) << 22) | \ |
| (((n) & 0xFFFFF) << 0)) |
| |
| #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ |
| (((vmid) & 0xF) << 20) | \ |
| (((n) & 0xFFFFF) << 0)) |
| |
| /* async DMA Packet types */ |
| #define DMA_PACKET_WRITE 0x2 |
| #define DMA_PACKET_COPY 0x3 |
| #define DMA_PACKET_INDIRECT_BUFFER 0x4 |
| #define DMA_PACKET_SEMAPHORE 0x5 |
| #define DMA_PACKET_FENCE 0x6 |
| #define DMA_PACKET_TRAP 0x7 |
| #define DMA_PACKET_SRBM_WRITE 0x9 |
| #define DMA_PACKET_CONSTANT_FILL 0xd |
| #define DMA_PACKET_NOP 0xf |
| |
| #endif |
| |