| 268,6 → 268,17 |
|---|
| } |
| rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; |
| rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; |
| |
| /* FIXME use something else than big hammer but after few days can not |
| * seem to find good combination so reset SDMA blocks as it seems we |
| * do not shut them down properly. This fix hibernation and does not |
| * affect suspend to ram. |
| */ |
| WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1); |
| (void)RREG32(SRBM_SOFT_RESET); |
| udelay(50); |
| WREG32(SRBM_SOFT_RESET, 0); |
| (void)RREG32(SRBM_SOFT_RESET); |
| } |
| |
| /** |
| 283,6 → 294,33 |
|---|
| } |
| |
| /** |
| * cik_sdma_ctx_switch_enable - enable/disable sdma engine preemption |
| * |
| * @rdev: radeon_device pointer |
| * @enable: enable/disable preemption. |
| * |
| * Halt or unhalt the async dma engines (CIK). |
| */ |
| static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable) |
| { |
| uint32_t reg_offset, value; |
| int i; |
| |
| for (i = 0; i < 2; i++) { |
| if (i == 0) |
| reg_offset = SDMA0_REGISTER_OFFSET; |
| else |
| reg_offset = SDMA1_REGISTER_OFFSET; |
| value = RREG32(SDMA0_CNTL + reg_offset); |
| if (enable) |
| value |= AUTO_CTXSW_ENABLE; |
| else |
| value &= ~AUTO_CTXSW_ENABLE; |
| WREG32(SDMA0_CNTL + reg_offset, value); |
| } |
| } |
| |
| /** |
| * cik_sdma_enable - stop the async dma engines |
| * |
| * @rdev: radeon_device pointer |
| 312,6 → 350,8 |
|---|
| me_cntl |= SDMA_HALT; |
| WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); |
| } |
| |
| cik_sdma_ctx_switch_enable(rdev, enable); |
| } |
| |
| /** |
| 816,7 → 856,6 |
|---|
| for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
| if (flags & R600_PTE_SYSTEM) { |
| value = radeon_vm_map_gart(rdev, addr); |
| value &= 0xFFFFFFFFFFFFF000ULL; |
| } else if (flags & R600_PTE_VALID) { |
| value = addr; |
| } else { |
| 903,6 → 942,9 |
|---|
| void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| unsigned vm_id, uint64_t pd_addr) |
| { |
| u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | |
| SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ |
| |
| radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| if (vm_id < 8) { |
| radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); |
| 943,5 → 985,12 |
|---|
| radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
| radeon_ring_write(ring, 1 << vm_id); |
| |
| radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); |
| radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
| radeon_ring_write(ring, 0); |
| radeon_ring_write(ring, 0); /* reference */ |
| radeon_ring_write(ring, 0); /* mask */ |
| radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ |
| } |
| |