/drivers/video/drm/radeon/cursor.S |
---|
File deleted |
/drivers/video/drm/radeon/Makefile |
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3,7 → 3,7 |
CC = gcc |
LD = ld |
AS = as |
FASM = e:/fasm/fasm.exe |
FASM = fasm.exe |
DEFINES = -D__KERNEL__ -DCONFIG_X86_32 |
/drivers/video/drm/radeon/Makefile.lto |
---|
42,23 → 42,24 |
NAME_SRC= \ |
pci.c \ |
$(DRM_TOPDIR)/drm_mm.c \ |
$(DRM_TOPDIR)/drm_irq.c \ |
$(DRM_TOPDIR)/drm_edid.c \ |
$(DRM_TOPDIR)/drm_modes.c \ |
$(DRM_TOPDIR)/drm_crtc.c \ |
$(DRM_TOPDIR)/drm_crtc_helper.c \ |
$(DRM_TOPDIR)/drm_dp_i2c_helper.c \ |
$(DRM_TOPDIR)/drm_edid.c \ |
$(DRM_TOPDIR)/drm_fb_helper.c \ |
$(DRM_TOPDIR)/drm_dp_i2c_helper.c \ |
$(DRM_TOPDIR)/drm_irq.c \ |
$(DRM_TOPDIR)/drm_mm.c \ |
$(DRM_TOPDIR)/drm_modes.c \ |
$(DRM_TOPDIR)/drm_pci.c \ |
$(DRM_TOPDIR)/drm_stub.c \ |
$(DRM_TOPDIR)/i2c/i2c-core.c \ |
$(DRM_TOPDIR)/i2c/i2c-algo-bit.c \ |
tracker/bitmap.c \ |
r700_vs.c \ |
r600_video.c \ |
radeon_device.c \ |
evergreen.c \ |
evergreen_blit_shaders.c \ |
evergreen_blit_kms.c \ |
evergreen_hdmi.c \ |
cayman_blit_shaders.c \ |
radeon_clocks.c \ |
atom.c \ |
72,6 → 73,8 |
radeon_connectors.c \ |
atombios_crtc.c \ |
atombios_dp.c \ |
atombios_encoders.c \ |
atombios_i2c.c \ |
radeon_encoders.c \ |
radeon_fence.c \ |
radeon_gem.c \ |
84,6 → 87,8 |
radeon_gart.c \ |
radeon_ring.c \ |
radeon_object_kos.c \ |
radeon_sa.c \ |
radeon_semaphore.c \ |
radeon_pm.c \ |
r100.c \ |
r200.c \ |
92,7 → 97,6 |
rv515.c \ |
r520.c \ |
r600.c \ |
r600_audio.c \ |
r600_blit_kms.c \ |
r600_blit_shaders.c \ |
r600_hdmi.c \ |
104,6 → 108,8 |
rdisplay.c \ |
rdisplay_kms.c \ |
cmdline.c \ |
si.c \ |
si_blit_shaders.c \ |
fwblob.asm |
FW_BINS= \ |
/drivers/video/drm/radeon/atombios_crtc.c |
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1696,8 → 1696,7 |
return ATOM_PPLL2; |
DRM_ERROR("unable to allocate a PPLL\n"); |
return ATOM_PPLL_INVALID; |
} else { |
if (ASIC_IS_AVIVO(rdev)) { |
} else if (ASIC_IS_AVIVO(rdev)) { |
/* in DP mode, the DP ref clock can come from either PPLL |
* depending on the asic: |
* DCE3: PPLL1 or PPLL2 |
1715,10 → 1714,20 |
} |
/* all other cases */ |
pll_in_use = radeon_get_pll_use_mask(crtc); |
/* the order shouldn't matter here, but we probably |
* need this until we have atomic modeset |
*/ |
if (rdev->flags & RADEON_IS_IGP) { |
if (!(pll_in_use & (1 << ATOM_PPLL1))) |
return ATOM_PPLL1; |
if (!(pll_in_use & (1 << ATOM_PPLL2))) |
return ATOM_PPLL2; |
} else { |
if (!(pll_in_use & (1 << ATOM_PPLL2))) |
return ATOM_PPLL2; |
if (!(pll_in_use & (1 << ATOM_PPLL1))) |
return ATOM_PPLL1; |
} |
DRM_ERROR("unable to allocate a PPLL\n"); |
return ATOM_PPLL_INVALID; |
} else { |
1726,7 → 1735,6 |
return radeon_crtc->crtc_id; |
} |
} |
} |
void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
{ |
/drivers/video/drm/radeon/evergreen.c |
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1285,7 → 1285,7 |
WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); |
for (i = 0; i < rdev->num_crtc; i++) { |
if (save->crtc_enabled) { |
if (save->crtc_enabled[i]) { |
if (ASIC_IS_DCE6(rdev)) { |
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); |
tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; |
/drivers/video/drm/radeon/evergreend.h |
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91,6 → 91,10 |
#define FB_READ_EN (1 << 0) |
#define FB_WRITE_EN (1 << 1) |
#define CP_STRMOUT_CNTL 0x84FC |
#define CP_COHER_CNTL 0x85F0 |
#define CP_COHER_SIZE 0x85F4 |
#define CP_COHER_BASE 0x85F8 |
#define CP_STALLED_STAT1 0x8674 |
#define CP_STALLED_STAT2 0x8678 |
/drivers/video/drm/radeon/pci.c |
---|
676,35 → 676,7 |
region->end = res->end; |
} |
static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
u32 *val) |
{ |
*val = PciRead32(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
u32 val) |
{ |
PciWrite32(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
static inline int pci_read_config_word(struct pci_dev *dev, int where, |
u16 *val) |
{ |
*val = PciRead16(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_write_config_word(struct pci_dev *dev, int where, |
u16 val) |
{ |
PciWrite16(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
int pci_enable_rom(struct pci_dev *pdev) |
{ |
struct resource *res = pdev->resource + PCI_ROM_RESOURCE; |
/drivers/video/drm/radeon/radeon_benchmark.c |
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41,7 → 41,7 |
struct radeon_fence *fence = NULL; |
int i, r; |
start_jiffies = jiffies; |
start_jiffies = GetTimerTicks(); |
for (i = 0; i < n; i++) { |
switch (flag) { |
case RADEON_BENCHMARK_COPY_DMA: |
/drivers/video/drm/radeon/radeon_device.c |
---|
1452,13 → 1452,6 |
return err; |
}; |
void drm_vblank_post_modeset(struct drm_device *dev, int crtc) |
{}; |
void drm_vblank_pre_modeset(struct drm_device *dev, int crtc) |
{}; |
#define PCI_CLASS_REVISION 0x08 |
#define PCI_CLASS_DISPLAY_VGA 0x0300 |
/drivers/video/drm/radeon/radeon_fence.c |
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351,7 → 351,7 |
/* change last activity so nobody else think there is a lockup */ |
for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
rdev->fence_drv[i].last_activity = jiffies; |
rdev->fence_drv[i].last_activity = GetTimerTicks(); |
} |
/* mark the ring as not ready any more */ |
811,7 → 811,7 |
for (i = 0; i < RADEON_NUM_RINGS; ++i) |
rdev->fence_drv[ring].sync_seq[i] = 0; |
atomic64_set(&rdev->fence_drv[ring].last_seq, 0); |
rdev->fence_drv[ring].last_activity = jiffies; |
rdev->fence_drv[ring].last_activity = GetTimerTicks(); |
rdev->fence_drv[ring].initialized = false; |
} |
/drivers/video/drm/radeon/si.c |
---|
2474,6 → 2474,7 |
/* check config regs */ |
switch (reg) { |
case GRBM_GFX_INDEX: |
case CP_STRMOUT_CNTL: |
case VGT_VTX_VECT_EJECT_REG: |
case VGT_CACHE_INVALIDATION: |
case VGT_ESGS_RING_SIZE: |
/drivers/video/drm/radeon/sid.h |
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424,6 → 424,7 |
# define RDERR_INT_ENABLE (1 << 0) |
# define GUI_IDLE_INT_ENABLE (1 << 19) |
#define CP_STRMOUT_CNTL 0x84FC |
#define SCRATCH_REG0 0x8500 |
#define SCRATCH_REG1 0x8504 |
#define SCRATCH_REG2 0x8508 |