| 37,6 → 37,106 |
|---|
| #include <drm/i915_drm.h> |
| #include "i915_drv.h" |
| |
| static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) |
| { |
| /* paranoia */ |
| if (!mode->crtc_htotal) |
| return 1; |
| |
| return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal); |
| } |
| |
| static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) |
| { |
| struct drm_device *dev = crtc->base.dev; |
| const struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
| enum pipe pipe = crtc->pipe; |
| long timeout = msecs_to_jiffies_timeout(1); |
| int scanline, min, max, vblank_start; |
| DEFINE_WAIT(wait); |
| |
| WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex)); |
| |
| vblank_start = mode->crtc_vblank_start; |
| if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| vblank_start = DIV_ROUND_UP(vblank_start, 2); |
| |
| /* FIXME needs to be calibrated sensibly */ |
| min = vblank_start - usecs_to_scanlines(mode, 100); |
| max = vblank_start - 1; |
| |
| if (min <= 0 || max <= 0) |
| return false; |
| |
| // if (WARN_ON(drm_vblank_get(dev, pipe))) |
| // return false; |
| |
| // local_irq_disable(); |
| |
| // trace_i915_pipe_update_start(crtc, min, max); |
| |
| for (;;) { |
| /* |
| * prepare_to_wait() has a memory barrier, which guarantees |
| * other CPUs can see the task state update by the time we |
| * read the scanline. |
| */ |
| prepare_to_wait(&crtc->vbl_wait, &wait, TASK_UNINTERRUPTIBLE); |
| |
| scanline = intel_get_crtc_scanline(crtc); |
| if (scanline < min || scanline > max) |
| break; |
| |
| if (timeout <= 0) { |
| DRM_ERROR("Potential atomic update failure on pipe %c\n", |
| pipe_name(crtc->pipe)); |
| break; |
| } |
| |
| // local_irq_enable(); |
| |
| schedule_timeout(timeout); |
| timeout = 0; |
| // local_irq_disable(); |
| } |
| |
| finish_wait(&crtc->vbl_wait, &wait); |
| |
| // drm_vblank_put(dev, pipe); |
| |
| *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
| |
| // trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count); |
| |
| return true; |
| } |
| |
| static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) |
| { |
| struct drm_device *dev = crtc->base.dev; |
| enum pipe pipe = crtc->pipe; |
| u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
| |
| // trace_i915_pipe_update_end(crtc, end_vbl_count); |
| |
| // local_irq_enable(); |
| |
| if (start_vbl_count != end_vbl_count) |
| DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n", |
| pipe_name(pipe), start_vbl_count, end_vbl_count); |
| } |
| |
| static void intel_update_primary_plane(struct intel_crtc *crtc) |
| { |
| struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| int reg = DSPCNTR(crtc->plane); |
| |
| if (crtc->primary_enabled) |
| I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
| else |
| I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
| } |
| |
| static void |
| vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
| struct drm_framebuffer *fb, |
| 48,11 → 148,14 |
|---|
| struct drm_device *dev = dplane->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_plane *intel_plane = to_intel_plane(dplane); |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int pipe = intel_plane->pipe; |
| int plane = intel_plane->plane; |
| u32 sprctl; |
| unsigned long sprsurf_offset, linear_offset; |
| int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| u32 start_vbl_count; |
| bool atomic_update; |
| |
| sprctl = I915_READ(SPCNTR(pipe, plane)); |
| |
| 115,7 → 218,8 |
|---|
| |
| sprctl |= SP_ENABLE; |
| |
| intel_update_sprite_watermarks(dplane, crtc, src_w, pixel_size, true, |
| intel_update_sprite_watermarks(dplane, crtc, src_w, src_h, |
| pixel_size, true, |
| src_w != crtc_w || src_h != crtc_h); |
| |
| /* Sizes are 0 based */ |
| 124,9 → 228,6 |
|---|
| crtc_w--; |
| crtc_h--; |
| |
| I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
| I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
| |
| linear_offset = y * fb->pitches[0] + x * pixel_size; |
| sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, |
| obj->tiling_mode, |
| 134,6 → 235,13 |
|---|
| fb->pitches[0]); |
| linear_offset -= sprsurf_offset; |
| |
| atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
| |
| intel_update_primary_plane(intel_crtc); |
| |
| I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
| I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
| |
| if (obj->tiling_mode != I915_TILING_NONE) |
| I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
| else |
| 143,7 → 251,11 |
|---|
| I915_WRITE(SPCNTR(pipe, plane), sprctl); |
| I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
| sprsurf_offset); |
| POSTING_READ(SPSURF(pipe, plane)); |
| |
| intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
| |
| if (atomic_update) |
| intel_pipe_update_end(intel_crtc, start_vbl_count); |
| } |
| |
| static void |
| 152,16 → 264,27 |
|---|
| struct drm_device *dev = dplane->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_plane *intel_plane = to_intel_plane(dplane); |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int pipe = intel_plane->pipe; |
| int plane = intel_plane->plane; |
| u32 start_vbl_count; |
| bool atomic_update; |
| |
| atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
| |
| intel_update_primary_plane(intel_crtc); |
| |
| I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & |
| ~SP_ENABLE); |
| /* Activate double buffered register update */ |
| I915_WRITE(SPSURF(pipe, plane), 0); |
| POSTING_READ(SPSURF(pipe, plane)); |
| |
| intel_update_sprite_watermarks(dplane, crtc, 0, 0, false, false); |
| intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
| |
| if (atomic_update) |
| intel_pipe_update_end(intel_crtc, start_vbl_count); |
| |
| intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); |
| } |
| |
| static int |
| 226,10 → 349,13 |
|---|
| struct drm_device *dev = plane->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_plane *intel_plane = to_intel_plane(plane); |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int pipe = intel_plane->pipe; |
| u32 sprctl, sprscale = 0; |
| unsigned long sprsurf_offset, linear_offset; |
| int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| u32 start_vbl_count; |
| bool atomic_update; |
| |
| sprctl = I915_READ(SPRCTL(pipe)); |
| |
| 281,7 → 407,8 |
|---|
| if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| sprctl |= SPRITE_PIPE_CSC_ENABLE; |
| |
| intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true, |
| intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size, |
| true, |
| src_w != crtc_w || src_h != crtc_h); |
| |
| /* Sizes are 0 based */ |
| 293,9 → 420,6 |
|---|
| if (crtc_w != src_w || crtc_h != src_h) |
| sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
| |
| I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
| I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
| |
| linear_offset = y * fb->pitches[0] + x * pixel_size; |
| sprsurf_offset = |
| intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
| 302,6 → 426,13 |
|---|
| pixel_size, fb->pitches[0]); |
| linear_offset -= sprsurf_offset; |
| |
| atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
| |
| intel_update_primary_plane(intel_crtc); |
| |
| I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
| I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
| |
| /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
| * register */ |
| if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 317,7 → 448,11 |
|---|
| I915_WRITE(SPRCTL(pipe), sprctl); |
| I915_WRITE(SPRSURF(pipe), |
| i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); |
| POSTING_READ(SPRSURF(pipe)); |
| |
| intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
| |
| if (atomic_update) |
| intel_pipe_update_end(intel_crtc, start_vbl_count); |
| } |
| |
| static void |
| 326,8 → 461,15 |
|---|
| struct drm_device *dev = plane->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_plane *intel_plane = to_intel_plane(plane); |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int pipe = intel_plane->pipe; |
| u32 start_vbl_count; |
| bool atomic_update; |
| |
| atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
| |
| intel_update_primary_plane(intel_crtc); |
| |
| I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
| /* Can't leave the scaler enabled... */ |
| if (intel_plane->can_scale) |
| 334,8 → 476,12 |
|---|
| I915_WRITE(SPRSCALE(pipe), 0); |
| /* Activate double buffered register update */ |
| I915_WRITE(SPRSURF(pipe), 0); |
| POSTING_READ(SPRSURF(pipe)); |
| |
| intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
| |
| if (atomic_update) |
| intel_pipe_update_end(intel_crtc, start_vbl_count); |
| |
| /* |
| * Avoid underruns when disabling the sprite. |
| * FIXME remove once watermark updates are done properly. |
| 342,7 → 488,7 |
|---|
| */ |
| intel_wait_for_vblank(dev, pipe); |
| |
| intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false); |
| intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false); |
| } |
| |
| static int |
| 410,10 → 556,13 |
|---|
| struct drm_device *dev = plane->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_plane *intel_plane = to_intel_plane(plane); |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int pipe = intel_plane->pipe; |
| unsigned long dvssurf_offset, linear_offset; |
| u32 dvscntr, dvsscale; |
| int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| u32 start_vbl_count; |
| bool atomic_update; |
| |
| dvscntr = I915_READ(DVSCNTR(pipe)); |
| |
| 459,7 → 608,8 |
|---|
| dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
| dvscntr |= DVS_ENABLE; |
| |
| intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true, |
| intel_update_sprite_watermarks(plane, crtc, src_w, src_h, |
| pixel_size, true, |
| src_w != crtc_w || src_h != crtc_h); |
| |
| /* Sizes are 0 based */ |
| 472,9 → 622,6 |
|---|
| if (crtc_w != src_w || crtc_h != src_h) |
| dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
| |
| I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
| I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
| |
| linear_offset = y * fb->pitches[0] + x * pixel_size; |
| dvssurf_offset = |
| intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
| 481,6 → 628,13 |
|---|
| pixel_size, fb->pitches[0]); |
| linear_offset -= dvssurf_offset; |
| |
| atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
| |
| intel_update_primary_plane(intel_crtc); |
| |
| I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
| I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
| |
| if (obj->tiling_mode != I915_TILING_NONE) |
| I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
| else |
| 491,7 → 645,11 |
|---|
| I915_WRITE(DVSCNTR(pipe), dvscntr); |
| I915_WRITE(DVSSURF(pipe), |
| i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); |
| POSTING_READ(DVSSURF(pipe)); |
| |
| intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
| |
| if (atomic_update) |
| intel_pipe_update_end(intel_crtc, start_vbl_count); |
| } |
| |
| static void |
| 500,15 → 658,26 |
|---|
| struct drm_device *dev = plane->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_plane *intel_plane = to_intel_plane(plane); |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int pipe = intel_plane->pipe; |
| u32 start_vbl_count; |
| bool atomic_update; |
| |
| atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); |
| |
| intel_update_primary_plane(intel_crtc); |
| |
| I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); |
| /* Disable the scaler */ |
| I915_WRITE(DVSSCALE(pipe), 0); |
| /* Flush double buffered register updates */ |
| I915_WRITE(DVSSURF(pipe), 0); |
| POSTING_READ(DVSSURF(pipe)); |
| |
| intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
| |
| if (atomic_update) |
| intel_pipe_update_end(intel_crtc, start_vbl_count); |
| |
| /* |
| * Avoid underruns when disabling the sprite. |
| * FIXME remove once watermark updates are done properly. |
| 515,25 → 684,15 |
|---|
| */ |
| intel_wait_for_vblank(dev, pipe); |
| |
| intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false); |
| intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false); |
| } |
| |
| static void |
| intel_enable_primary(struct drm_crtc *crtc) |
| intel_post_enable_primary(struct drm_crtc *crtc) |
| { |
| struct drm_device *dev = crtc->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int reg = DSPCNTR(intel_crtc->plane); |
| |
| if (intel_crtc->primary_enabled) |
| return; |
| |
| intel_crtc->primary_enabled = true; |
| |
| I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
| intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
| |
| /* |
| * FIXME IPS should be fine as long as one plane is |
| * enabled, but in practice it seems to have problems |
| 540,10 → 699,7 |
|---|
| * when going from primary only to sprite only and vice |
| * versa. |
| */ |
| if (intel_crtc->config.ips_enabled) { |
| intel_wait_for_vblank(dev, intel_crtc->pipe); |
| hsw_enable_ips(intel_crtc); |
| } |
| |
| mutex_lock(&dev->struct_mutex); |
| intel_update_fbc(dev); |
| 551,18 → 707,12 |
|---|
| } |
| |
| static void |
| intel_disable_primary(struct drm_crtc *crtc) |
| intel_pre_disable_primary(struct drm_crtc *crtc) |
| { |
| struct drm_device *dev = crtc->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int reg = DSPCNTR(intel_crtc->plane); |
| |
| if (!intel_crtc->primary_enabled) |
| return; |
| |
| intel_crtc->primary_enabled = false; |
| |
| mutex_lock(&dev->struct_mutex); |
| if (dev_priv->fbc.plane == intel_crtc->plane) |
| intel_disable_fbc(dev); |
| 575,9 → 725,6 |
|---|
| * versa. |
| */ |
| hsw_disable_ips(intel_crtc); |
| |
| I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
| intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
| } |
| |
| static int |
| 667,11 → 814,12 |
|---|
| struct drm_device *dev = plane->dev; |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| struct intel_plane *intel_plane = to_intel_plane(plane); |
| enum pipe pipe = intel_crtc->pipe; |
| struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| struct drm_i915_gem_object *obj = intel_fb->obj; |
| struct drm_i915_gem_object *old_obj = intel_plane->obj; |
| int ret; |
| bool disable_primary = false; |
| bool primary_enabled; |
| bool visible; |
| int hscale, vscale; |
| int max_scale, min_scale; |
| 842,8 → 990,8 |
|---|
| * If the sprite is completely covering the primary plane, |
| * we can disable the primary and save power. |
| */ |
| disable_primary = drm_rect_equals(&dst, &clip) && !colorkey_enabled(intel_plane); |
| WARN_ON(disable_primary && !visible && intel_crtc->active); |
| primary_enabled = !drm_rect_equals(&dst, &clip) || colorkey_enabled(intel_plane); |
| WARN_ON(!primary_enabled && !visible && intel_crtc->active); |
| |
| mutex_lock(&dev->struct_mutex); |
| |
| 854,6 → 1002,8 |
|---|
| */ |
| ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
| |
| i915_gem_track_fb(old_obj, obj, |
| INTEL_FRONTBUFFER_SPRITE(pipe)); |
| mutex_unlock(&dev->struct_mutex); |
| |
| if (ret) |
| 870,13 → 1020,15 |
|---|
| intel_plane->obj = obj; |
| |
| if (intel_crtc->active) { |
| /* |
| * Be sure to re-enable the primary before the sprite is no longer |
| * covering it fully. |
| */ |
| if (!disable_primary) |
| intel_enable_primary(crtc); |
| bool primary_was_enabled = intel_crtc->primary_enabled; |
| |
| intel_crtc->primary_enabled = primary_enabled; |
| |
| // if (primary_was_enabled != primary_enabled) |
| |
| if (primary_was_enabled && !primary_enabled) |
| intel_pre_disable_primary(crtc); |
| |
| if (visible) |
| intel_plane->update_plane(plane, crtc, fb, obj, |
| crtc_x, crtc_y, crtc_w, crtc_h, |
| 884,8 → 1036,8 |
|---|
| else |
| intel_plane->disable_plane(plane, crtc); |
| |
| if (disable_primary) |
| intel_disable_primary(crtc); |
| if (!primary_was_enabled && primary_enabled) |
| intel_post_enable_primary(crtc); |
| } |
| |
| /* Unpin old obj after new one is active to avoid ugliness */ |
| 913,6 → 1065,7 |
|---|
| struct drm_device *dev = plane->dev; |
| struct intel_plane *intel_plane = to_intel_plane(plane); |
| struct intel_crtc *intel_crtc; |
| enum pipe pipe; |
| |
| if (!plane->fb) |
| return 0; |
| 921,10 → 1074,17 |
|---|
| return -EINVAL; |
| |
| intel_crtc = to_intel_crtc(plane->crtc); |
| pipe = intel_crtc->pipe; |
| |
| if (intel_crtc->active) { |
| intel_enable_primary(plane->crtc); |
| bool primary_was_enabled = intel_crtc->primary_enabled; |
| |
| intel_crtc->primary_enabled = true; |
| |
| intel_plane->disable_plane(plane, plane->crtc); |
| |
| if (!primary_was_enabled && intel_crtc->primary_enabled) |
| intel_post_enable_primary(plane->crtc); |
| } |
| |
| if (intel_plane->obj) { |
| 933,6 → 1093,8 |
|---|
| |
| mutex_lock(&dev->struct_mutex); |
| intel_unpin_fb_obj(intel_plane->obj); |
| i915_gem_track_fb(intel_plane->obj, NULL, |
| INTEL_FRONTBUFFER_SPRITE(pipe)); |
| mutex_unlock(&dev->struct_mutex); |
| |
| intel_plane->obj = NULL; |
| 953,7 → 1115,6 |
|---|
| struct drm_file *file_priv) |
| { |
| struct drm_intel_sprite_colorkey *set = data; |
| struct drm_mode_object *obj; |
| struct drm_plane *plane; |
| struct intel_plane *intel_plane; |
| int ret = 0; |
| 967,13 → 1128,12 |
|---|
| |
| drm_modeset_lock_all(dev); |
| |
| obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); |
| if (!obj) { |
| plane = drm_plane_find(dev, set->plane_id); |
| if (!plane) { |
| ret = -ENOENT; |
| goto out_unlock; |
| } |
| |
| plane = obj_to_plane(obj); |
| intel_plane = to_intel_plane(plane); |
| ret = intel_plane->update_colorkey(plane, set); |
| |
| 986,7 → 1146,6 |
|---|
| struct drm_file *file_priv) |
| { |
| struct drm_intel_sprite_colorkey *get = data; |
| struct drm_mode_object *obj; |
| struct drm_plane *plane; |
| struct intel_plane *intel_plane; |
| int ret = 0; |
| 996,13 → 1155,12 |
|---|
| |
| drm_modeset_lock_all(dev); |
| |
| obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); |
| if (!obj) { |
| plane = drm_plane_find(dev, get->plane_id); |
| if (!plane) { |
| ret = -ENOENT; |
| goto out_unlock; |
| } |
| |
| plane = obj_to_plane(obj); |
| intel_plane = to_intel_plane(plane); |
| intel_plane->get_colorkey(plane, get); |
| |