49,7 → 49,7 |
(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | |
(bar << IOSF_BAR_SHIFT); |
|
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); |
|
if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n", |
75,28 → 75,28 |
return 0; |
} |
|
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr) |
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr) |
{ |
u32 val = 0; |
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
|
mutex_lock(&dev_priv->dpio_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
mutex_lock(&dev_priv->sb_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, |
SB_CRRDDA_NP, addr, &val); |
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
|
return val; |
} |
|
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) |
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val) |
{ |
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
|
mutex_lock(&dev_priv->dpio_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
mutex_lock(&dev_priv->sb_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, |
SB_CRWRDA_NP, addr, &val); |
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
} |
|
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) |
103,7 → 103,7 |
{ |
u32 val = 0; |
|
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT, |
SB_CRRDDA_NP, reg, &val); |
|
return val; |
111,7 → 111,7 |
|
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT, |
SB_CRWRDA_NP, reg, &val); |
} |
|
121,10 → 121,10 |
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
|
mutex_lock(&dev_priv->dpio_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, |
mutex_lock(&dev_priv->sb_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC, |
SB_CRRDDA_NP, addr, &val); |
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
|
return val; |
} |
132,7 → 132,7 |
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC, |
SB_CRRDDA_NP, reg, &val); |
return val; |
} |
139,7 → 139,7 |
|
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC, |
SB_CRWRDA_NP, reg, &val); |
} |
|
146,7 → 146,7 |
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK, |
SB_CRRDDA_NP, reg, &val); |
return val; |
} |
153,7 → 153,7 |
|
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK, |
SB_CRWRDA_NP, reg, &val); |
} |
|
160,7 → 160,7 |
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU, |
SB_CRRDDA_NP, reg, &val); |
return val; |
} |
167,7 → 167,7 |
|
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU, |
SB_CRWRDA_NP, reg, &val); |
} |
|
174,7 → 174,7 |
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE, |
SB_CRRDDA_NP, reg, &val); |
return val; |
} |
181,7 → 181,7 |
|
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE, |
SB_CRWRDA_NP, reg, &val); |
} |
|
213,7 → 213,7 |
enum intel_sbi_destination destination) |
{ |
u32 value = 0; |
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); |
|
if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
100)) { |
243,7 → 243,7 |
{ |
u32 tmp; |
|
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); |
|
if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
100)) { |