29,12 → 29,21 |
* IOSF sideband, see VLV2_SidebandMsg_HAS.docx and |
* VLV_VLV2_PUNIT_HAS_0.8.docx |
*/ |
|
/* Standard MMIO read, non-posted */ |
#define SB_MRD_NP 0x00 |
/* Standard MMIO write, non-posted */ |
#define SB_MWR_NP 0x01 |
/* Private register read, double-word addressing, non-posted */ |
#define SB_CRRDDA_NP 0x06 |
/* Private register write, double-word addressing, non-posted */ |
#define SB_CRWRDA_NP 0x07 |
|
static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
u32 port, u32 opcode, u32 addr, u32 *val) |
{ |
u32 cmd, be = 0xf, bar = 0; |
bool is_read = (opcode == PUNIT_OPCODE_REG_READ || |
opcode == DPIO_OPCODE_REG_READ); |
bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP); |
|
cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | |
(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | |
74,7 → 83,7 |
|
mutex_lock(&dev_priv->dpio_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
PUNIT_OPCODE_REG_READ, addr, &val); |
SB_CRRDDA_NP, addr, &val); |
mutex_unlock(&dev_priv->dpio_lock); |
|
return val; |
86,7 → 95,7 |
|
mutex_lock(&dev_priv->dpio_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
PUNIT_OPCODE_REG_WRITE, addr, &val); |
SB_CRWRDA_NP, addr, &val); |
mutex_unlock(&dev_priv->dpio_lock); |
} |
|
95,7 → 104,7 |
u32 val = 0; |
|
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
PUNIT_OPCODE_REG_READ, reg, &val); |
SB_CRRDDA_NP, reg, &val); |
|
return val; |
} |
103,7 → 112,7 |
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT, |
PUNIT_OPCODE_REG_WRITE, reg, &val); |
SB_CRWRDA_NP, reg, &val); |
} |
|
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
114,7 → 123,7 |
|
mutex_lock(&dev_priv->dpio_lock); |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, |
PUNIT_OPCODE_REG_READ, addr, &val); |
SB_CRRDDA_NP, addr, &val); |
mutex_unlock(&dev_priv->dpio_lock); |
|
return val; |
124,7 → 133,7 |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
PUNIT_OPCODE_REG_READ, reg, &val); |
SB_CRRDDA_NP, reg, &val); |
return val; |
} |
|
131,7 → 140,7 |
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, |
PUNIT_OPCODE_REG_WRITE, reg, &val); |
SB_CRWRDA_NP, reg, &val); |
} |
|
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) |
138,7 → 147,7 |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
PUNIT_OPCODE_REG_READ, reg, &val); |
SB_CRRDDA_NP, reg, &val); |
return val; |
} |
|
145,7 → 154,7 |
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, |
PUNIT_OPCODE_REG_WRITE, reg, &val); |
SB_CRWRDA_NP, reg, &val); |
} |
|
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) |
152,7 → 161,7 |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
PUNIT_OPCODE_REG_READ, reg, &val); |
SB_CRRDDA_NP, reg, &val); |
return val; |
} |
|
159,7 → 168,7 |
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, |
PUNIT_OPCODE_REG_WRITE, reg, &val); |
SB_CRWRDA_NP, reg, &val); |
} |
|
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) |
166,7 → 175,7 |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
PUNIT_OPCODE_REG_READ, reg, &val); |
SB_CRRDDA_NP, reg, &val); |
return val; |
} |
|
173,7 → 182,7 |
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, |
PUNIT_OPCODE_REG_WRITE, reg, &val); |
SB_CRWRDA_NP, reg, &val); |
} |
|
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) |
181,7 → 190,15 |
u32 val = 0; |
|
vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), |
DPIO_OPCODE_REG_READ, reg, &val); |
SB_MRD_NP, reg, &val); |
|
/* |
* FIXME: There might be some registers where all 1's is a valid value, |
* so ideally we should check the register offset instead... |
*/ |
WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n", |
pipe_name(pipe), reg, val); |
|
return val; |
} |
|
188,7 → 205,7 |
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), |
DPIO_OPCODE_REG_WRITE, reg, &val); |
SB_MWR_NP, reg, &val); |
} |
|
/* SBI access */ |
253,13 → 270,13 |
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) |
{ |
u32 val = 0; |
vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, |
DPIO_OPCODE_REG_READ, reg, &val); |
vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, |
reg, &val); |
return val; |
} |
|
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) |
{ |
vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, |
DPIO_OPCODE_REG_WRITE, reg, &val); |
vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, |
reg, &val); |
} |