284,6 → 284,13 |
1 << PIPE_C | 1 << PIPE_B); |
} |
|
static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) |
{ |
if (IS_BROADWELL(dev_priv)) |
gen8_irq_power_well_pre_disable(dev_priv, |
1 << PIPE_C | 1 << PIPE_B); |
} |
|
static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
struct i915_power_well *power_well) |
{ |
309,6 → 316,14 |
} |
} |
|
static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, |
struct i915_power_well *power_well) |
{ |
if (power_well->data == SKL_DISP_PW_2) |
gen8_irq_power_well_pre_disable(dev_priv, |
1 << PIPE_C | 1 << PIPE_B); |
} |
|
static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
struct i915_power_well *power_well, bool enable) |
{ |
334,6 → 349,7 |
|
} else { |
if (enable_requested) { |
hsw_power_well_pre_disable(dev_priv); |
I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
POSTING_READ(HSW_PWR_WELL_DRIVER); |
DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
456,15 → 472,19 |
*/ |
} |
|
static void gen9_set_dc_state_debugmask_memory_up( |
struct drm_i915_private *dev_priv) |
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) |
{ |
uint32_t val; |
uint32_t val, mask; |
|
mask = DC_STATE_DEBUG_MASK_MEMORY_UP; |
|
if (IS_BROXTON(dev_priv)) |
mask |= DC_STATE_DEBUG_MASK_CORES; |
|
/* The below bit doesn't need to be cleared ever afterwards */ |
val = I915_READ(DC_STATE_DEBUG); |
if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { |
val |= DC_STATE_DEBUG_MASK_MEMORY_UP; |
if ((val & mask) != mask) { |
val |= mask; |
I915_WRITE(DC_STATE_DEBUG, val); |
POSTING_READ(DC_STATE_DEBUG); |
} |
525,9 → 545,6 |
else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5) |
state = DC_STATE_EN_UPTO_DC5; |
|
if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK) |
gen9_set_dc_state_debugmask_memory_up(dev_priv); |
|
val = I915_READ(DC_STATE_EN); |
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", |
val & mask, state); |
577,7 → 594,8 |
bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
SKL_DISP_PW_2); |
|
WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); |
WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev), |
"Platform doesn't support DC5.\n"); |
WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); |
WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); |
|
613,7 → 631,8 |
{ |
struct drm_device *dev = dev_priv->dev; |
|
WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); |
WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev), |
"Platform doesn't support DC6.\n"); |
WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); |
WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
"Backlight is not disabled.\n"); |
640,7 → 659,8 |
{ |
assert_can_disable_dc5(dev_priv); |
|
if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1) |
if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
i915.enable_dc != 0 && i915.enable_dc != 1) |
assert_can_disable_dc6(dev_priv); |
|
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
668,7 → 688,6 |
static void skl_set_power_well(struct drm_i915_private *dev_priv, |
struct i915_power_well *power_well, bool enable) |
{ |
struct drm_device *dev = dev_priv->dev; |
uint32_t tmp, fuse_status; |
uint32_t req_mask, state_mask; |
bool is_enabled, enable_requested, check_fuse_status = false; |
706,6 → 725,9 |
state_mask = SKL_POWER_WELL_STATE(power_well->data); |
is_enabled = tmp & state_mask; |
|
if (!enable && enable_requested) |
skl_power_well_pre_disable(dev_priv, power_well); |
|
if (enable) { |
if (!enable_requested) { |
WARN((tmp & state_mask) && |
712,17 → 734,6 |
!I915_READ(HSW_PWR_WELL_BIOS), |
"Invalid for power well status to be enabled, unless done by the BIOS, \ |
when request is to disable!\n"); |
if (power_well->data == SKL_DISP_PW_2) { |
/* |
* DDI buffer programming unnecessary during |
* driver-load/resume as it's already done |
* during modeset initialization then. It's |
* also invalid here as encoder list is still |
* uninitialized. |
*/ |
if (!dev_priv->power_domains.initializing) |
intel_prepare_ddi(dev); |
} |
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
} |
|
828,7 → 839,8 |
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, |
struct i915_power_well *power_well) |
{ |
if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1) |
if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
i915.enable_dc != 0 && i915.enable_dc != 1) |
skl_enable_dc6(dev_priv); |
else |
gen9_enable_dc5(dev_priv); |
840,7 → 852,8 |
if (power_well->count > 0) { |
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
} else { |
if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && |
if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
i915.enable_dc != 0 && |
i915.enable_dc != 1) |
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); |
else |
993,6 → 1006,9 |
valleyview_disable_display_irqs(dev_priv); |
spin_unlock_irq(&dev_priv->irq_lock); |
|
/* make sure we're done processing display irqs */ |
synchronize_irq(dev_priv->dev->irq); |
|
vlv_power_sequencer_reset(dev_priv); |
} |
|
1941,7 → 1957,7 |
{ |
struct i915_power_well *well; |
|
if (!IS_SKYLAKE(dev_priv)) |
if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) |
return; |
|
well = lookup_power_well(dev_priv, SKL_DISP_PW_1); |
1955,7 → 1971,7 |
{ |
struct i915_power_well *well; |
|
if (!IS_SKYLAKE(dev_priv)) |
if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) |
return; |
|
well = lookup_power_well(dev_priv, SKL_DISP_PW_1); |
2125,8 → 2141,8 |
|
skl_init_cdclk(dev_priv); |
|
if (dev_priv->csr.dmc_payload) |
intel_csr_load_program(dev_priv); |
if (dev_priv->csr.dmc_payload && intel_csr_load_program(dev_priv)) |
gen9_set_dc_state_debugmask(dev_priv); |
} |
|
static void skl_display_core_uninit(struct drm_i915_private *dev_priv) |