76,7 → 76,7 |
u32 tmp; |
|
power_domain = intel_display_port_power_domain(encoder); |
if (!intel_display_power_enabled(dev_priv, power_domain)) |
if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
return false; |
|
tmp = I915_READ(lvds_encoder->reg); |
823,8 → 823,7 |
struct intel_encoder *encoder; |
struct intel_lvds_encoder *lvds_encoder; |
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
base.head) { |
for_each_intel_encoder(dev, encoder) { |
if (encoder->type == INTEL_OUTPUT_LVDS) { |
lvds_encoder = to_lvds_encoder(&encoder->base); |
|
900,6 → 899,17 |
int pipe; |
u8 pin; |
|
/* |
* Unlock registers and just leave them unlocked. Do this before |
* checking quirk lists to avoid bogus WARNINGs. |
*/ |
if (HAS_PCH_SPLIT(dev)) { |
I915_WRITE(PCH_PP_CONTROL, |
I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); |
} else { |
I915_WRITE(PP_CONTROL, |
I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); |
} |
if (!intel_lvds_supported(dev)) |
return; |
|
1098,21 → 1108,10 |
lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) & |
LVDS_A3_POWER_MASK; |
|
/* |
* Unlock registers and just |
* leave them unlocked |
*/ |
if (HAS_PCH_SPLIT(dev)) { |
I915_WRITE(PCH_PP_CONTROL, |
I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); |
} else { |
I915_WRITE(PP_CONTROL, |
I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); |
} |
drm_connector_register(connector); |
|
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
intel_panel_setup_backlight(connector); |
intel_panel_setup_backlight(connector, INVALID_PIPE); |
|
return; |
|