135,7 → 135,7 |
#include <drm/drmP.h> |
#include <drm/i915_drm.h> |
#include "intel_drv.h" |
#include "i915_drv.h" |
#include "intel_mocs.h" |
|
#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
189,13 → 189,28 |
#define GEN8_CTX_FORCE_RESTORE (1<<2) |
#define GEN8_CTX_L3LLC_COHERENT (1<<5) |
#define GEN8_CTX_PRIVILEGE (1<<8) |
|
#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ |
const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ |
} |
|
#define ASSIGN_CTX_PML4(ppgtt, reg_state) { \ |
reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ |
} |
|
enum { |
ADVANCED_CONTEXT = 0, |
LEGACY_CONTEXT, |
LEGACY_32B_CONTEXT, |
ADVANCED_AD_CONTEXT, |
LEGACY_64B_CONTEXT |
}; |
#define GEN8_CTX_MODE_SHIFT 3 |
#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 |
#define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ |
LEGACY_64B_CONTEXT :\ |
LEGACY_32B_CONTEXT) |
enum { |
FAULT_AND_HANG = 0, |
FAULT_AND_HALT, /* Debug only */ |
203,10 → 218,13 |
FAULT_AND_CONTINUE /* Unsupported */ |
}; |
#define GEN8_CTX_ID_SHIFT 32 |
#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
|
static int intel_lr_context_pin(struct intel_engine_cs *ring, |
struct intel_context *ctx); |
static int intel_lr_context_pin(struct drm_i915_gem_request *rq); |
static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
struct drm_i915_gem_object *default_ctx_obj); |
|
|
/** |
* intel_sanitize_enable_execlists() - sanitize i915.enable_execlists |
* @dev: DRM device. |
213,8 → 231,7 |
* @enable_execlists: value of i915.enable_execlists module parameter. |
* |
* Only certain platforms support Execlists (the prerequisites being |
* support for Logical Ring Contexts and Aliasing PPGTT or better), |
* and only when enabled via module parameter. |
* support for Logical Ring Contexts and Aliasing PPGTT or better). |
* |
* Return: 1 if Execlists is supported and has to be enabled. |
*/ |
222,6 → 239,12 |
{ |
WARN_ON(i915.enable_ppgtt == -1); |
|
/* On platforms with execlist available, vGPU will only |
* support execlist mode, no ring buffer mode. |
*/ |
if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev)) |
return 1; |
|
if (INTEL_INFO(dev)->gen >= 9) |
return 1; |
|
249,7 → 272,8 |
*/ |
u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
{ |
u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); |
u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) + |
LRC_PPHWSP_PN * PAGE_SIZE; |
|
/* LRCA is required to be 4K aligned so the more significant 20 bits |
* are globally unique */ |
256,15 → 280,28 |
return lrca >> 12; |
} |
|
static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj) |
static bool disable_lite_restore_wa(struct intel_engine_cs *ring) |
{ |
struct drm_device *dev = ring->dev; |
|
return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || |
(IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) && |
(ring->id == VCS || ring->id == VCS2); |
} |
|
uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
struct intel_engine_cs *ring) |
{ |
struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; |
uint64_t desc; |
uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); |
uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj) + |
LRC_PPHWSP_PN * PAGE_SIZE; |
|
WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); |
|
desc = GEN8_CTX_VALID; |
desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; |
desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT; |
if (IS_GEN8(ctx_obj->base.dev)) |
desc |= GEN8_CTX_L3LLC_COHERENT; |
desc |= GEN8_CTX_PRIVILEGE; |
desc |= lrca; |
274,143 → 311,109 |
* signalling between Command Streamers */ |
/* desc |= GEN8_CTX_FORCE_RESTORE; */ |
|
/* WaEnableForceRestoreInCtxtDescForVCS:skl */ |
/* WaEnableForceRestoreInCtxtDescForVCS:bxt */ |
if (disable_lite_restore_wa(ring)) |
desc |= GEN8_CTX_FORCE_RESTORE; |
|
return desc; |
} |
|
static void execlists_elsp_write(struct intel_engine_cs *ring, |
struct drm_i915_gem_object *ctx_obj0, |
struct drm_i915_gem_object *ctx_obj1) |
static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
struct drm_i915_gem_request *rq1) |
{ |
|
struct intel_engine_cs *ring = rq0->ring; |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint64_t temp = 0; |
uint32_t desc[4]; |
unsigned long flags; |
uint64_t desc[2]; |
|
/* XXX: You must always write both descriptors in the order below. */ |
if (ctx_obj1) |
temp = execlists_ctx_descriptor(ctx_obj1); |
else |
temp = 0; |
desc[1] = (u32)(temp >> 32); |
desc[0] = (u32)temp; |
|
temp = execlists_ctx_descriptor(ctx_obj0); |
desc[3] = (u32)(temp >> 32); |
desc[2] = (u32)temp; |
|
/* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes |
* are in progress. |
* |
* The other problem is that we can't just call gen6_gt_force_wake_get() |
* because that function calls intel_runtime_pm_get(), which might sleep. |
* Instead, we do the runtime_pm_get/put when creating/destroying requests. |
*/ |
spin_lock_irqsave(&dev_priv->uncore.lock, flags); |
if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) { |
if (dev_priv->uncore.fw_rendercount++ == 0) |
dev_priv->uncore.funcs.force_wake_get(dev_priv, |
FORCEWAKE_RENDER); |
if (dev_priv->uncore.fw_mediacount++ == 0) |
dev_priv->uncore.funcs.force_wake_get(dev_priv, |
FORCEWAKE_MEDIA); |
if (INTEL_INFO(dev)->gen >= 9) { |
if (dev_priv->uncore.fw_blittercount++ == 0) |
dev_priv->uncore.funcs.force_wake_get(dev_priv, |
FORCEWAKE_BLITTER); |
} |
if (rq1) { |
desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring); |
rq1->elsp_submitted++; |
} else { |
if (dev_priv->uncore.forcewake_count++ == 0) |
dev_priv->uncore.funcs.force_wake_get(dev_priv, |
FORCEWAKE_ALL); |
desc[1] = 0; |
} |
spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); |
|
I915_WRITE(RING_ELSP(ring), desc[1]); |
I915_WRITE(RING_ELSP(ring), desc[0]); |
I915_WRITE(RING_ELSP(ring), desc[3]); |
/* The context is automatically loaded after the following */ |
I915_WRITE(RING_ELSP(ring), desc[2]); |
desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring); |
rq0->elsp_submitted++; |
|
/* ELSP is a wo register, so use another nearby reg for posting instead */ |
POSTING_READ(RING_EXECLIST_STATUS(ring)); |
/* You must always write both descriptors in the order below. */ |
spin_lock(&dev_priv->uncore.lock); |
intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); |
I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1])); |
I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1])); |
|
/* Release Force Wakeup (see the big comment above). */ |
spin_lock_irqsave(&dev_priv->uncore.lock, flags); |
if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) { |
if (--dev_priv->uncore.fw_rendercount == 0) |
dev_priv->uncore.funcs.force_wake_put(dev_priv, |
FORCEWAKE_RENDER); |
if (--dev_priv->uncore.fw_mediacount == 0) |
dev_priv->uncore.funcs.force_wake_put(dev_priv, |
FORCEWAKE_MEDIA); |
if (INTEL_INFO(dev)->gen >= 9) { |
if (--dev_priv->uncore.fw_blittercount == 0) |
dev_priv->uncore.funcs.force_wake_put(dev_priv, |
FORCEWAKE_BLITTER); |
} |
} else { |
if (--dev_priv->uncore.forcewake_count == 0) |
dev_priv->uncore.funcs.force_wake_put(dev_priv, |
FORCEWAKE_ALL); |
} |
I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0])); |
/* The context is automatically loaded after the following */ |
I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0])); |
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); |
/* ELSP is a wo register, use another nearby reg for posting */ |
POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring)); |
intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); |
spin_unlock(&dev_priv->uncore.lock); |
} |
|
static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, |
struct drm_i915_gem_object *ring_obj, |
u32 tail) |
static int execlists_update_context(struct drm_i915_gem_request *rq) |
{ |
struct intel_engine_cs *ring = rq->ring; |
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; |
struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj; |
struct page *page; |
uint32_t *reg_state; |
|
page = i915_gem_object_get_page(ctx_obj, 1); |
BUG_ON(!ctx_obj); |
WARN_ON(!i915_gem_obj_is_pinned(ctx_obj)); |
WARN_ON(!i915_gem_obj_is_pinned(rb_obj)); |
|
page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
reg_state = kmap_atomic(page); |
|
reg_state[CTX_RING_TAIL+1] = tail; |
reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); |
reg_state[CTX_RING_TAIL+1] = rq->tail; |
reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj); |
|
if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
/* True 32b PPGTT with dynamic page allocation: update PDP |
* registers and point the unallocated PDPs to scratch page. |
* PML4 is allocated during ppgtt init, so this is not needed |
* in 48-bit mode. |
*/ |
ASSIGN_CTX_PDP(ppgtt, reg_state, 3); |
ASSIGN_CTX_PDP(ppgtt, reg_state, 2); |
ASSIGN_CTX_PDP(ppgtt, reg_state, 1); |
ASSIGN_CTX_PDP(ppgtt, reg_state, 0); |
} |
|
kunmap_atomic(reg_state); |
|
return 0; |
} |
|
static void execlists_submit_contexts(struct intel_engine_cs *ring, |
struct intel_context *to0, u32 tail0, |
struct intel_context *to1, u32 tail1) |
static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
struct drm_i915_gem_request *rq1) |
{ |
struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state; |
struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf; |
struct drm_i915_gem_object *ctx_obj1 = NULL; |
struct intel_ringbuffer *ringbuf1 = NULL; |
execlists_update_context(rq0); |
|
BUG_ON(!ctx_obj0); |
WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); |
WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj)); |
if (rq1) |
execlists_update_context(rq1); |
|
execlists_update_context(ctx_obj0, ringbuf0->obj, tail0); |
|
if (to1) { |
ringbuf1 = to1->engine[ring->id].ringbuf; |
ctx_obj1 = to1->engine[ring->id].state; |
BUG_ON(!ctx_obj1); |
WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); |
WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj)); |
|
execlists_update_context(ctx_obj1, ringbuf1->obj, tail1); |
execlists_elsp_write(rq0, rq1); |
} |
|
execlists_elsp_write(ring, ctx_obj0, ctx_obj1); |
} |
|
static void execlists_context_unqueue(struct intel_engine_cs *ring) |
{ |
struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL; |
struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL; |
struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; |
|
assert_spin_locked(&ring->execlist_lock); |
|
/* |
* If irqs are not active generate a warning as batches that finish |
* without the irqs may get lost and a GPU Hang may occur. |
*/ |
WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); |
|
if (list_empty(&ring->execlist_queue)) |
return; |
|
433,26 → 436,40 |
} |
} |
|
if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { |
/* |
* WaIdleLiteRestore: make sure we never cause a lite |
* restore with HEAD==TAIL |
*/ |
if (req0->elsp_submitted) { |
/* |
* Apply the wa NOOPS to prevent ring:HEAD == req:TAIL |
* as we resubmit the request. See gen8_emit_request() |
* for where we prepare the padding after the end of the |
* request. |
*/ |
struct intel_ringbuffer *ringbuf; |
|
ringbuf = req0->ctx->engine[ring->id].ringbuf; |
req0->tail += 8; |
req0->tail &= ringbuf->size - 1; |
} |
} |
|
WARN_ON(req1 && req1->elsp_submitted); |
|
execlists_submit_contexts(ring, req0->ctx, req0->tail, |
req1 ? req1->ctx : NULL, |
req1 ? req1->tail : 0); |
|
req0->elsp_submitted++; |
if (req1) |
req1->elsp_submitted++; |
execlists_submit_requests(req0, req1); |
} |
|
static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
u32 request_id) |
{ |
struct intel_ctx_submit_request *head_req; |
struct drm_i915_gem_request *head_req; |
|
assert_spin_locked(&ring->execlist_lock); |
|
head_req = list_first_entry_or_null(&ring->execlist_queue, |
struct intel_ctx_submit_request, |
struct drm_i915_gem_request, |
execlist_link); |
|
if (head_req != NULL) { |
475,19 → 492,19 |
} |
|
/** |
* intel_execlists_handle_ctx_events() - handle Context Switch interrupts |
* intel_lrc_irq_handler() - handle Context Switch interrupts |
* @ring: Engine Command Streamer to handle. |
* |
* Check the unread Context Status Buffers and manage the submission of new |
* contexts to the ELSP accordingly. |
*/ |
void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring) |
void intel_lrc_irq_handler(struct intel_engine_cs *ring) |
{ |
struct drm_i915_private *dev_priv = ring->dev->dev_private; |
u32 status_pointer; |
u8 read_pointer; |
u8 write_pointer; |
u32 status; |
u32 status = 0; |
u32 status_id; |
u32 submit_contexts = 0; |
|
494,19 → 511,20 |
status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); |
|
read_pointer = ring->next_context_status_buffer; |
write_pointer = status_pointer & 0x07; |
write_pointer = status_pointer & GEN8_CSB_PTR_MASK; |
if (read_pointer > write_pointer) |
write_pointer += 6; |
write_pointer += GEN8_CSB_ENTRIES; |
|
spin_lock(&ring->execlist_lock); |
|
while (read_pointer < write_pointer) { |
read_pointer++; |
status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + |
(read_pointer % 6) * 8); |
status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + |
(read_pointer % 6) * 8 + 4); |
status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % GEN8_CSB_ENTRIES)); |
status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % GEN8_CSB_ENTRIES)); |
|
if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) |
continue; |
|
if (status & GEN8_CTX_STATUS_PREEMPTED) { |
if (status & GEN8_CTX_STATUS_LITE_RESTORE) { |
if (execlists_check_remove_request(ring, status_id)) |
522,55 → 540,51 |
} |
} |
|
if (submit_contexts != 0) |
if (disable_lite_restore_wa(ring)) { |
/* Prevent a ctx to preempt itself */ |
if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) && |
(submit_contexts != 0)) |
execlists_context_unqueue(ring); |
} else if (submit_contexts != 0) { |
execlists_context_unqueue(ring); |
} |
|
spin_unlock(&ring->execlist_lock); |
|
WARN(submit_contexts > 2, "More than two context complete events?\n"); |
ring->next_context_status_buffer = write_pointer % 6; |
ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; |
|
I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), |
((u32)ring->next_context_status_buffer & 0x07) << 8); |
_MASKED_FIELD(GEN8_CSB_PTR_MASK << 8, |
((u32)ring->next_context_status_buffer & |
GEN8_CSB_PTR_MASK) << 8)); |
} |
|
static int execlists_context_queue(struct intel_engine_cs *ring, |
struct intel_context *to, |
u32 tail) |
static int execlists_context_queue(struct drm_i915_gem_request *request) |
{ |
struct intel_ctx_submit_request *req = NULL, *cursor; |
struct drm_i915_private *dev_priv = ring->dev->dev_private; |
unsigned long flags; |
struct intel_engine_cs *ring = request->ring; |
struct drm_i915_gem_request *cursor; |
int num_elements = 0; |
|
req = kzalloc(sizeof(*req), GFP_KERNEL); |
if (req == NULL) |
return -ENOMEM; |
req->ctx = to; |
i915_gem_context_reference(req->ctx); |
if (request->ctx != ring->default_context) |
intel_lr_context_pin(request); |
|
if (to != ring->default_context) |
intel_lr_context_pin(ring, to); |
i915_gem_request_reference(request); |
|
req->ring = ring; |
req->tail = tail; |
spin_lock_irq(&ring->execlist_lock); |
|
intel_runtime_pm_get(dev_priv); |
|
spin_lock_irqsave(&ring->execlist_lock, flags); |
|
list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
if (++num_elements > 2) |
break; |
|
if (num_elements > 2) { |
struct intel_ctx_submit_request *tail_req; |
struct drm_i915_gem_request *tail_req; |
|
tail_req = list_last_entry(&ring->execlist_queue, |
struct intel_ctx_submit_request, |
struct drm_i915_gem_request, |
execlist_link); |
|
if (to == tail_req->ctx) { |
if (request->ctx == tail_req->ctx) { |
WARN(tail_req->elsp_submitted != 0, |
"More than 2 already-submitted reqs queued\n"); |
list_del(&tail_req->execlist_link); |
579,18 → 593,18 |
} |
} |
|
list_add_tail(&req->execlist_link, &ring->execlist_queue); |
list_add_tail(&request->execlist_link, &ring->execlist_queue); |
if (num_elements == 0) |
execlists_context_unqueue(ring); |
|
spin_unlock_irqrestore(&ring->execlist_lock, flags); |
spin_unlock_irq(&ring->execlist_lock); |
|
return 0; |
} |
|
static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf) |
static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
{ |
struct intel_engine_cs *ring = ringbuf->ring; |
struct intel_engine_cs *ring = req->ring; |
uint32_t flush_domains; |
int ret; |
|
598,7 → 612,7 |
if (ring->gpu_caches_dirty) |
flush_domains = I915_GEM_GPU_DOMAINS; |
|
ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains); |
ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
if (ret) |
return ret; |
|
606,10 → 620,10 |
return 0; |
} |
|
static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, |
static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
struct list_head *vmas) |
{ |
struct intel_engine_cs *ring = ringbuf->ring; |
const unsigned other_rings = ~intel_ring_flag(req->ring); |
struct i915_vma *vma; |
uint32_t flush_domains = 0; |
bool flush_chipset = false; |
618,9 → 632,11 |
list_for_each_entry(vma, vmas, exec_list) { |
struct drm_i915_gem_object *obj = vma->obj; |
|
ret = i915_gem_object_sync(obj, ring); |
if (obj->active & other_rings) { |
ret = i915_gem_object_sync(obj, req->ring, &req); |
if (ret) |
return ret; |
} |
|
if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) |
flush_chipset |= i915_gem_clflush_object(obj, false); |
634,10 → 650,205 |
/* Unconditionally invalidate gpu caches and ensure that we do flush |
* any residual writes from the previous batch. |
*/ |
return logical_ring_invalidate_all_caches(ringbuf); |
return logical_ring_invalidate_all_caches(req); |
} |
|
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
{ |
int ret; |
|
request->ringbuf = request->ctx->engine[request->ring->id].ringbuf; |
|
if (request->ctx != request->ring->default_context) { |
ret = intel_lr_context_pin(request); |
if (ret) |
return ret; |
} |
|
return 0; |
} |
|
static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
int bytes) |
{ |
struct intel_ringbuffer *ringbuf = req->ringbuf; |
struct intel_engine_cs *ring = req->ring; |
struct drm_i915_gem_request *target; |
unsigned space; |
int ret; |
|
if (intel_ring_space(ringbuf) >= bytes) |
return 0; |
|
/* The whole point of reserving space is to not wait! */ |
WARN_ON(ringbuf->reserved_in_use); |
|
list_for_each_entry(target, &ring->request_list, list) { |
/* |
* The request queue is per-engine, so can contain requests |
* from multiple ringbuffers. Here, we must ignore any that |
* aren't from the ringbuffer we're considering. |
*/ |
if (target->ringbuf != ringbuf) |
continue; |
|
/* Would completion of this request free enough space? */ |
space = __intel_ring_space(target->postfix, ringbuf->tail, |
ringbuf->size); |
if (space >= bytes) |
break; |
} |
|
if (WARN_ON(&target->list == &ring->request_list)) |
return -ENOSPC; |
|
ret = i915_wait_request(target); |
if (ret) |
return ret; |
|
ringbuf->space = space; |
return 0; |
} |
|
/* |
* intel_logical_ring_advance_and_submit() - advance the tail and submit the workload |
* @request: Request to advance the logical ringbuffer of. |
* |
* The tail is updated in our logical ringbuffer struct, not in the actual context. What |
* really happens during submission is that the context and current tail will be placed |
* on a queue waiting for the ELSP to be ready to accept a new context submission. At that |
* point, the tail *inside* the context is updated and the ELSP written to. |
*/ |
static void |
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
{ |
struct intel_engine_cs *ring = request->ring; |
struct drm_i915_private *dev_priv = request->i915; |
|
intel_logical_ring_advance(request->ringbuf); |
|
request->tail = request->ringbuf->tail; |
|
if (intel_ring_stopped(ring)) |
return; |
|
if (dev_priv->guc.execbuf_client) |
i915_guc_submit(dev_priv->guc.execbuf_client, request); |
else |
execlists_context_queue(request); |
} |
|
static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
{ |
uint32_t __iomem *virt; |
int rem = ringbuf->size - ringbuf->tail; |
|
virt = ringbuf->virtual_start + ringbuf->tail; |
rem /= 4; |
while (rem--) |
iowrite32(MI_NOOP, virt++); |
|
ringbuf->tail = 0; |
intel_ring_update_space(ringbuf); |
} |
|
static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
{ |
struct intel_ringbuffer *ringbuf = req->ringbuf; |
int remain_usable = ringbuf->effective_size - ringbuf->tail; |
int remain_actual = ringbuf->size - ringbuf->tail; |
int ret, total_bytes, wait_bytes = 0; |
bool need_wrap = false; |
|
if (ringbuf->reserved_in_use) |
total_bytes = bytes; |
else |
total_bytes = bytes + ringbuf->reserved_size; |
|
if (unlikely(bytes > remain_usable)) { |
/* |
* Not enough space for the basic request. So need to flush |
* out the remainder and then wait for base + reserved. |
*/ |
wait_bytes = remain_actual + total_bytes; |
need_wrap = true; |
} else { |
if (unlikely(total_bytes > remain_usable)) { |
/* |
* The base request will fit but the reserved space |
* falls off the end. So only need to to wait for the |
* reserved size after flushing out the remainder. |
*/ |
wait_bytes = remain_actual + ringbuf->reserved_size; |
need_wrap = true; |
} else if (total_bytes > ringbuf->space) { |
/* No wrapping required, just waiting. */ |
wait_bytes = total_bytes; |
} |
} |
|
if (wait_bytes) { |
ret = logical_ring_wait_for_space(req, wait_bytes); |
if (unlikely(ret)) |
return ret; |
|
if (need_wrap) |
__wrap_ring_buffer(ringbuf); |
} |
|
return 0; |
} |
|
/** |
* intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands |
* |
* @req: The request to start some new work for |
* @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
* |
* The ringbuffer might not be ready to accept the commands right away (maybe it needs to |
* be wrapped, or wait a bit for the tail to be updated). This function takes care of that |
* and also preallocates a request (every workload submission is still mediated through |
* requests, same as it did with legacy ringbuffer submission). |
* |
* Return: non-zero if the ringbuffer is not ready to be written to. |
*/ |
int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
{ |
struct drm_i915_private *dev_priv; |
int ret; |
|
WARN_ON(req == NULL); |
dev_priv = req->ring->dev->dev_private; |
|
ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
dev_priv->mm.interruptible); |
if (ret) |
return ret; |
|
ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
if (ret) |
return ret; |
|
req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
return 0; |
} |
|
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
{ |
/* |
* The first call merely notes the reserve request and is common for |
* all back ends. The subsequent localised _begin() call actually |
* ensures that the reservation is available. Without the begin, if |
* the request creator immediately submitted the request without |
* adding any commands to it then there might not actually be |
* sufficient room for the submission commands. |
*/ |
intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); |
|
return intel_logical_ring_begin(request, 0); |
} |
|
/** |
* execlists_submission() - submit a batchbuffer for execution, Execlists style |
* @dev: DRM device. |
* @file: DRM file. |
647,7 → 858,7 |
* @vmas: list of vmas. |
* @batch_obj: the batchbuffer to submit. |
* @exec_start: batchbuffer start virtual address pointer. |
* @flags: translated execbuffer call flags. |
* @dispatch_flags: translated execbuffer call flags. |
* |
* This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts |
* away the submission details of the execbuffer ioctl call. |
654,16 → 865,15 |
* |
* Return: non-zero if the submission fails. |
*/ |
int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, |
struct intel_engine_cs *ring, |
struct intel_context *ctx, |
int intel_execlists_submission(struct i915_execbuffer_params *params, |
struct drm_i915_gem_execbuffer2 *args, |
struct list_head *vmas, |
struct drm_i915_gem_object *batch_obj, |
u64 exec_start, u32 flags) |
struct list_head *vmas) |
{ |
struct drm_device *dev = params->dev; |
struct intel_engine_cs *ring = params->ring; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf; |
u64 exec_start; |
int instp_mode; |
u32 instp_mask; |
int ret; |
694,33 → 904,18 |
return -EINVAL; |
} |
|
if (args->num_cliprects != 0) { |
DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); |
return -EINVAL; |
} else { |
if (args->DR4 == 0xffffffff) { |
DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); |
args->DR4 = 0; |
} |
|
if (args->DR1 || args->DR4 || args->cliprects_ptr) { |
DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); |
return -EINVAL; |
} |
} |
|
if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
DRM_DEBUG("sol reset is gen7 only\n"); |
return -EINVAL; |
} |
|
ret = execlists_move_to_gpu(ringbuf, vmas); |
ret = execlists_move_to_gpu(params->request, vmas); |
if (ret) |
return ret; |
|
if (ring == &dev_priv->ring[RCS] && |
instp_mode != dev_priv->relative_constants_mode) { |
ret = intel_logical_ring_begin(ringbuf, 4); |
ret = intel_logical_ring_begin(params->request, 4); |
if (ret) |
return ret; |
|
733,21 → 928,24 |
dev_priv->relative_constants_mode = instp_mode; |
} |
|
ret = ring->emit_bb_start(ringbuf, exec_start, flags); |
exec_start = params->batch_obj_vm_offset + |
args->batch_start_offset; |
|
ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
if (ret) |
return ret; |
|
i915_gem_execbuffer_move_to_active(vmas, ring); |
i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
|
i915_gem_execbuffer_move_to_active(vmas, params->request); |
i915_gem_execbuffer_retire_commands(params); |
|
return 0; |
} |
|
void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
{ |
struct intel_ctx_submit_request *req, *tmp; |
struct drm_i915_private *dev_priv = ring->dev->dev_private; |
unsigned long flags; |
struct drm_i915_gem_request *req, *tmp; |
struct list_head retired_list; |
|
WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
755,9 → 953,9 |
return; |
|
INIT_LIST_HEAD(&retired_list); |
spin_lock_irqsave(&ring->execlist_lock, flags); |
spin_lock_irq(&ring->execlist_lock); |
list_replace_init(&ring->execlist_retired_req_list, &retired_list); |
spin_unlock_irqrestore(&ring->execlist_lock, flags); |
spin_unlock_irq(&ring->execlist_lock); |
|
list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { |
struct intel_context *ctx = req->ctx; |
765,11 → 963,9 |
ctx->engine[ring->id].state; |
|
if (ctx_obj && (ctx != ring->default_context)) |
intel_lr_context_unpin(ring, ctx); |
intel_runtime_pm_put(dev_priv); |
i915_gem_context_unreference(req->ctx); |
intel_lr_context_unpin(req); |
list_del(&req->execlist_link); |
kfree(req); |
i915_gem_request_unreference(req); |
} |
} |
|
795,15 → 991,15 |
I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
} |
|
int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf) |
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
{ |
struct intel_engine_cs *ring = ringbuf->ring; |
struct intel_engine_cs *ring = req->ring; |
int ret; |
|
if (!ring->gpu_caches_dirty) |
return 0; |
|
ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS); |
ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
if (ret) |
return ret; |
|
811,66 → 1007,66 |
return 0; |
} |
|
/** |
* intel_logical_ring_advance_and_submit() - advance the tail and submit the workload |
* @ringbuf: Logical Ringbuffer to advance. |
* |
* The tail is updated in our logical ringbuffer struct, not in the actual context. What |
* really happens during submission is that the context and current tail will be placed |
* on a queue waiting for the ELSP to be ready to accept a new context submission. At that |
* point, the tail *inside* the context is updated and the ELSP written to. |
*/ |
void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) |
static int intel_lr_context_do_pin(struct intel_engine_cs *ring, |
struct drm_i915_gem_object *ctx_obj, |
struct intel_ringbuffer *ringbuf) |
{ |
struct intel_engine_cs *ring = ringbuf->ring; |
struct intel_context *ctx = ringbuf->FIXME_lrc_ctx; |
|
intel_logical_ring_advance(ringbuf); |
|
if (intel_ring_stopped(ring)) |
return; |
|
execlists_context_queue(ring, ctx, ringbuf->tail); |
} |
|
static int intel_lr_context_pin(struct intel_engine_cs *ring, |
struct intel_context *ctx) |
{ |
struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; |
struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int ret = 0; |
|
WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
if (ctx->engine[ring->id].unpin_count++ == 0) { |
ret = i915_gem_obj_ggtt_pin(ctx_obj, |
GEN8_LR_CONTEXT_ALIGN, 0); |
ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, |
PIN_OFFSET_BIAS | GUC_WOPCM_TOP); |
if (ret) |
goto reset_unpin_count; |
return ret; |
|
ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); |
if (ret) |
goto unpin_ctx_obj; |
} |
|
ctx_obj->dirty = true; |
|
/* Invalidate GuC TLB. */ |
if (i915.enable_guc_submission) |
I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
|
return ret; |
|
unpin_ctx_obj: |
i915_gem_object_ggtt_unpin(ctx_obj); |
reset_unpin_count: |
ctx->engine[ring->id].unpin_count = 0; |
|
return ret; |
} |
|
void intel_lr_context_unpin(struct intel_engine_cs *ring, |
struct intel_context *ctx) |
static int intel_lr_context_pin(struct drm_i915_gem_request *rq) |
{ |
struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; |
struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
int ret = 0; |
struct intel_engine_cs *ring = rq->ring; |
struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; |
struct intel_ringbuffer *ringbuf = rq->ringbuf; |
|
if (rq->ctx->engine[ring->id].pin_count++ == 0) { |
ret = intel_lr_context_do_pin(ring, ctx_obj, ringbuf); |
if (ret) |
goto reset_pin_count; |
} |
return ret; |
|
reset_pin_count: |
rq->ctx->engine[ring->id].pin_count = 0; |
return ret; |
} |
|
void intel_lr_context_unpin(struct drm_i915_gem_request *rq) |
{ |
struct intel_engine_cs *ring = rq->ring; |
struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; |
struct intel_ringbuffer *ringbuf = rq->ringbuf; |
|
if (ctx_obj) { |
WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
if (--ctx->engine[ring->id].unpin_count == 0) { |
if (--rq->ctx->engine[ring->id].pin_count == 0) { |
intel_unpin_ringbuffer_obj(ringbuf); |
i915_gem_object_ggtt_unpin(ctx_obj); |
} |
877,165 → 1073,307 |
} |
} |
|
static int logical_ring_alloc_seqno(struct intel_engine_cs *ring, |
struct intel_context *ctx) |
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
{ |
int ret; |
int ret, i; |
struct intel_engine_cs *ring = req->ring; |
struct intel_ringbuffer *ringbuf = req->ringbuf; |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct i915_workarounds *w = &dev_priv->workarounds; |
|
if (ring->outstanding_lazy_seqno) |
if (WARN_ON_ONCE(w->count == 0)) |
return 0; |
|
if (ring->preallocated_lazy_request == NULL) { |
struct drm_i915_gem_request *request; |
ring->gpu_caches_dirty = true; |
ret = logical_ring_flush_all_caches(req); |
if (ret) |
return ret; |
|
request = kmalloc(sizeof(*request), GFP_KERNEL); |
if (request == NULL) |
return -ENOMEM; |
ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
if (ret) |
return ret; |
|
if (ctx != ring->default_context) { |
ret = intel_lr_context_pin(ring, ctx); |
if (ret) { |
kfree(request); |
intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); |
for (i = 0; i < w->count; i++) { |
intel_logical_ring_emit(ringbuf, w->reg[i].addr); |
intel_logical_ring_emit(ringbuf, w->reg[i].value); |
} |
intel_logical_ring_emit(ringbuf, MI_NOOP); |
|
intel_logical_ring_advance(ringbuf); |
|
ring->gpu_caches_dirty = true; |
ret = logical_ring_flush_all_caches(req); |
if (ret) |
return ret; |
|
return 0; |
} |
} |
|
/* Hold a reference to the context this request belongs to |
* (we will need it when the time comes to emit/retire the |
* request). |
#define wa_ctx_emit(batch, index, cmd) \ |
do { \ |
int __index = (index)++; \ |
if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ |
return -ENOSPC; \ |
} \ |
batch[__index] = (cmd); \ |
} while (0) |
|
|
/* |
* In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after |
* PIPE_CONTROL instruction. This is required for the flush to happen correctly |
* but there is a slight complication as this is applied in WA batch where the |
* values are only initialized once so we cannot take register value at the |
* beginning and reuse it further; hence we save its value to memory, upload a |
* constant value with bit21 set and then we restore it back with the saved value. |
* To simplify the WA, a constant value is formed by using the default value |
* of this register. This shouldn't be a problem because we are only modifying |
* it for a short period and this batch in non-premptible. We can ofcourse |
* use additional instructions that read the actual value of the register |
* at that time and set our bit of interest but it makes the WA complicated. |
* |
* This WA is also required for Gen9 so extracting as a function avoids |
* code duplication. |
*/ |
request->ctx = ctx; |
i915_gem_context_reference(request->ctx); |
static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring, |
uint32_t *const batch, |
uint32_t index) |
{ |
uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); |
|
ring->preallocated_lazy_request = request; |
/* |
* WaDisableLSQCROPERFforOCL:skl |
* This WA is implemented in skl_init_clock_gating() but since |
* this batch updates GEN8_L3SQCREG4 with default value we need to |
* set this bit here to retain the WA during flush. |
*/ |
if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0) |
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
|
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
MI_SRM_LRM_GLOBAL_GTT)); |
wa_ctx_emit(batch, index, GEN8_L3SQCREG4); |
wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); |
wa_ctx_emit(batch, index, 0); |
|
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
wa_ctx_emit(batch, index, GEN8_L3SQCREG4); |
wa_ctx_emit(batch, index, l3sqc4_flush); |
|
wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | |
PIPE_CONTROL_DC_FLUSH_ENABLE)); |
wa_ctx_emit(batch, index, 0); |
wa_ctx_emit(batch, index, 0); |
wa_ctx_emit(batch, index, 0); |
wa_ctx_emit(batch, index, 0); |
|
wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
MI_SRM_LRM_GLOBAL_GTT)); |
wa_ctx_emit(batch, index, GEN8_L3SQCREG4); |
wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); |
wa_ctx_emit(batch, index, 0); |
|
return index; |
} |
|
return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
uint32_t offset, |
uint32_t start_alignment) |
{ |
return wa_ctx->offset = ALIGN(offset, start_alignment); |
} |
|
static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, |
int bytes) |
static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, |
uint32_t offset, |
uint32_t size_alignment) |
{ |
struct intel_engine_cs *ring = ringbuf->ring; |
struct drm_i915_gem_request *request; |
u32 seqno = 0; |
int ret; |
wa_ctx->size = offset - wa_ctx->offset; |
|
if (ringbuf->last_retired_head != -1) { |
ringbuf->head = ringbuf->last_retired_head; |
ringbuf->last_retired_head = -1; |
|
ringbuf->space = intel_ring_space(ringbuf); |
if (ringbuf->space >= bytes) |
WARN(wa_ctx->size % size_alignment, |
"wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", |
wa_ctx->size, size_alignment); |
return 0; |
} |
|
list_for_each_entry(request, &ring->request_list, list) { |
if (__intel_ring_space(request->tail, ringbuf->tail, |
ringbuf->size) >= bytes) { |
seqno = request->seqno; |
break; |
} |
} |
/** |
* gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA |
* |
* @ring: only applicable for RCS |
* @wa_ctx: structure representing wa_ctx |
* offset: specifies start of the batch, should be cache-aligned. This is updated |
* with the offset value received as input. |
* size: size of the batch in DWORDS but HW expects in terms of cachelines |
* @batch: page in which WA are loaded |
* @offset: This field specifies the start of the batch, it should be |
* cache-aligned otherwise it is adjusted accordingly. |
* Typically we only have one indirect_ctx and per_ctx batch buffer which are |
* initialized at the beginning and shared across all contexts but this field |
* helps us to have multiple batches at different offsets and select them based |
* on a criteria. At the moment this batch always start at the beginning of the page |
* and at this point we don't have multiple wa_ctx batch buffers. |
* |
* The number of WA applied are not known at the beginning; we use this field |
* to return the no of DWORDS written. |
* |
* It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
* so it adds NOOPs as padding to make it cacheline aligned. |
* MI_BATCH_BUFFER_END will be added to perctx batch and both of them together |
* makes a complete batch buffer. |
* |
* Return: non-zero if we exceed the PAGE_SIZE limit. |
*/ |
|
if (seqno == 0) |
return -ENOSPC; |
static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, |
struct i915_wa_ctx_bb *wa_ctx, |
uint32_t *const batch, |
uint32_t *offset) |
{ |
uint32_t scratch_addr; |
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
|
ret = i915_wait_seqno(ring, seqno); |
if (ret) |
return ret; |
/* WaDisableCtxRestoreArbitration:bdw,chv */ |
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
|
i915_gem_retire_requests_ring(ring); |
ringbuf->head = ringbuf->last_retired_head; |
ringbuf->last_retired_head = -1; |
|
ringbuf->space = intel_ring_space(ringbuf); |
return 0; |
/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
if (IS_BROADWELL(ring->dev)) { |
int rc = gen8_emit_flush_coherentl3_wa(ring, batch, index); |
if (rc < 0) |
return rc; |
index = rc; |
} |
|
static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, |
int bytes) |
{ |
struct intel_engine_cs *ring = ringbuf->ring; |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
unsigned long end; |
int ret; |
/* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
/* Actual scratch location is at 128 bytes offset */ |
scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES; |
|
ret = logical_ring_wait_request(ringbuf, bytes); |
if (ret != -ENOSPC) |
return ret; |
wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | |
PIPE_CONTROL_GLOBAL_GTT_IVB | |
PIPE_CONTROL_CS_STALL | |
PIPE_CONTROL_QW_WRITE)); |
wa_ctx_emit(batch, index, scratch_addr); |
wa_ctx_emit(batch, index, 0); |
wa_ctx_emit(batch, index, 0); |
wa_ctx_emit(batch, index, 0); |
|
/* Force the context submission in case we have been skipping it */ |
intel_logical_ring_advance_and_submit(ringbuf); |
/* Pad to end of cacheline */ |
while (index % CACHELINE_DWORDS) |
wa_ctx_emit(batch, index, MI_NOOP); |
|
/* With GEM the hangcheck timer should kick us out of the loop, |
* leaving it early runs the risk of corrupting GEM state (due |
* to running on almost untested codepaths). But on resume |
* timers don't work yet, so prevent a complete hang in that |
* case by choosing an insanely large timeout. */ |
end = jiffies + 60 * HZ; |
/* |
* MI_BATCH_BUFFER_END is not required in Indirect ctx BB because |
* execution depends on the length specified in terms of cache lines |
* in the register CTX_RCS_INDIRECT_CTX |
*/ |
|
do { |
ringbuf->head = I915_READ_HEAD(ring); |
ringbuf->space = intel_ring_space(ringbuf); |
if (ringbuf->space >= bytes) { |
ret = 0; |
break; |
return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); |
} |
|
msleep(1); |
/** |
* gen8_init_perctx_bb() - initialize per ctx batch with WA |
* |
* @ring: only applicable for RCS |
* @wa_ctx: structure representing wa_ctx |
* offset: specifies start of the batch, should be cache-aligned. |
* size: size of the batch in DWORDS but HW expects in terms of cachelines |
* @batch: page in which WA are loaded |
* @offset: This field specifies the start of this batch. |
* This batch is started immediately after indirect_ctx batch. Since we ensure |
* that indirect_ctx ends on a cacheline this batch is aligned automatically. |
* |
* The number of DWORDS written are returned using this field. |
* |
* This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding |
* to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. |
*/ |
static int gen8_init_perctx_bb(struct intel_engine_cs *ring, |
struct i915_wa_ctx_bb *wa_ctx, |
uint32_t *const batch, |
uint32_t *offset) |
{ |
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
|
ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
dev_priv->mm.interruptible); |
if (ret) |
break; |
/* WaDisableCtxRestoreArbitration:bdw,chv */ |
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
|
if (time_after(jiffies, end)) { |
ret = -EBUSY; |
break; |
} |
} while (1); |
wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
|
return ret; |
return wa_ctx_end(wa_ctx, *offset = index, 1); |
} |
|
static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) |
static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, |
struct i915_wa_ctx_bb *wa_ctx, |
uint32_t *const batch, |
uint32_t *offset) |
{ |
uint32_t __iomem *virt; |
int rem = ringbuf->size - ringbuf->tail; |
int ret; |
struct drm_device *dev = ring->dev; |
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
|
if (ringbuf->space < rem) { |
int ret = logical_ring_wait_for_space(ringbuf, rem); |
/* WaDisableCtxRestoreArbitration:skl,bxt */ |
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || |
(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) |
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
|
if (ret) |
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
ret = gen8_emit_flush_coherentl3_wa(ring, batch, index); |
if (ret < 0) |
return ret; |
index = ret; |
|
/* Pad to end of cacheline */ |
while (index % CACHELINE_DWORDS) |
wa_ctx_emit(batch, index, MI_NOOP); |
|
return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); |
} |
|
virt = ringbuf->virtual_start + ringbuf->tail; |
rem /= 4; |
while (rem--) |
iowrite32(MI_NOOP, virt++); |
static int gen9_init_perctx_bb(struct intel_engine_cs *ring, |
struct i915_wa_ctx_bb *wa_ctx, |
uint32_t *const batch, |
uint32_t *offset) |
{ |
struct drm_device *dev = ring->dev; |
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
|
ringbuf->tail = 0; |
ringbuf->space = intel_ring_space(ringbuf); |
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || |
(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { |
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
wa_ctx_emit(batch, index, |
_MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); |
wa_ctx_emit(batch, index, MI_NOOP); |
} |
|
return 0; |
/* WaDisableCtxRestoreArbitration:skl,bxt */ |
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || |
(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) |
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
|
wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
|
return wa_ctx_end(wa_ctx, *offset = index, 1); |
} |
|
static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) |
static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) |
{ |
int ret; |
|
if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
ret = logical_ring_wrap_buffer(ringbuf); |
if (unlikely(ret)) |
return ret; |
ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size)); |
if (!ring->wa_ctx.obj) { |
DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); |
return -ENOMEM; |
} |
|
if (unlikely(ringbuf->space < bytes)) { |
ret = logical_ring_wait_for_space(ringbuf, bytes); |
if (unlikely(ret)) |
ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); |
if (ret) { |
DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", |
ret); |
drm_gem_object_unreference(&ring->wa_ctx.obj->base); |
return ret; |
} |
|
1042,80 → 1380,84 |
return 0; |
} |
|
/** |
* intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands |
* |
* @ringbuf: Logical ringbuffer. |
* @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
* |
* The ringbuffer might not be ready to accept the commands right away (maybe it needs to |
* be wrapped, or wait a bit for the tail to be updated). This function takes care of that |
* and also preallocates a request (every workload submission is still mediated through |
* requests, same as it did with legacy ringbuffer submission). |
* |
* Return: non-zero if the ringbuffer is not ready to be written to. |
*/ |
int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) |
static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring) |
{ |
struct intel_engine_cs *ring = ringbuf->ring; |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
if (ring->wa_ctx.obj) { |
i915_gem_object_ggtt_unpin(ring->wa_ctx.obj); |
drm_gem_object_unreference(&ring->wa_ctx.obj->base); |
ring->wa_ctx.obj = NULL; |
} |
} |
|
static int intel_init_workaround_bb(struct intel_engine_cs *ring) |
{ |
int ret; |
uint32_t *batch; |
uint32_t offset; |
struct page *page; |
struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; |
|
ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
dev_priv->mm.interruptible); |
if (ret) |
return ret; |
WARN_ON(ring->id != RCS); |
|
ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); |
if (ret) |
return ret; |
/* update this when WA for higher Gen are added */ |
if (INTEL_INFO(ring->dev)->gen > 9) { |
DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
INTEL_INFO(ring->dev)->gen); |
return 0; |
} |
|
/* Preallocate the olr before touching the ring */ |
ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx); |
if (ret) |
/* some WA perform writes to scratch page, ensure it is valid */ |
if (ring->scratch.obj == NULL) { |
DRM_ERROR("scratch page not allocated for %s\n", ring->name); |
return -EINVAL; |
} |
|
ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE); |
if (ret) { |
DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); |
return ret; |
|
ringbuf->space -= num_dwords * sizeof(uint32_t); |
return 0; |
} |
|
static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring, |
struct intel_context *ctx) |
{ |
int ret, i; |
struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct i915_workarounds *w = &dev_priv->workarounds; |
page = i915_gem_object_get_page(wa_ctx->obj, 0); |
batch = kmap_atomic(page); |
offset = 0; |
|
if (WARN_ON(w->count == 0)) |
return 0; |
if (INTEL_INFO(ring->dev)->gen == 8) { |
ret = gen8_init_indirectctx_bb(ring, |
&wa_ctx->indirect_ctx, |
batch, |
&offset); |
if (ret) |
goto out; |
|
ring->gpu_caches_dirty = true; |
ret = logical_ring_flush_all_caches(ringbuf); |
ret = gen8_init_perctx_bb(ring, |
&wa_ctx->per_ctx, |
batch, |
&offset); |
if (ret) |
return ret; |
goto out; |
} else if (INTEL_INFO(ring->dev)->gen == 9) { |
ret = gen9_init_indirectctx_bb(ring, |
&wa_ctx->indirect_ctx, |
batch, |
&offset); |
if (ret) |
goto out; |
|
ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2); |
ret = gen9_init_perctx_bb(ring, |
&wa_ctx->per_ctx, |
batch, |
&offset); |
if (ret) |
return ret; |
|
intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); |
for (i = 0; i < w->count; i++) { |
intel_logical_ring_emit(ringbuf, w->reg[i].addr); |
intel_logical_ring_emit(ringbuf, w->reg[i].value); |
goto out; |
} |
intel_logical_ring_emit(ringbuf, MI_NOOP); |
|
intel_logical_ring_advance(ringbuf); |
out: |
kunmap_atomic(batch); |
if (ret) |
lrc_destroy_wa_ctx_obj(ring); |
|
ring->gpu_caches_dirty = true; |
ret = logical_ring_flush_all_caches(ringbuf); |
if (ret) |
return ret; |
|
return 0; |
} |
|
static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1122,14 → 1464,47 |
{ |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
u8 next_context_status_buffer_hw; |
|
lrc_setup_hardware_status_page(ring, |
ring->default_context->engine[ring->id].state); |
|
I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); |
|
if (ring->status_page.obj) { |
I915_WRITE(RING_HWS_PGA(ring->mmio_base), |
(u32)ring->status_page.gfx_addr); |
POSTING_READ(RING_HWS_PGA(ring->mmio_base)); |
} |
|
I915_WRITE(RING_MODE_GEN7(ring), |
_MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
POSTING_READ(RING_MODE_GEN7(ring)); |
|
/* |
* Instead of resetting the Context Status Buffer (CSB) read pointer to |
* zero, we need to read the write pointer from hardware and use its |
* value because "this register is power context save restored". |
* Effectively, these states have been observed: |
* |
* | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | |
* BDW | CSB regs not reset | CSB regs reset | |
* CHT | CSB regs not reset | CSB regs not reset | |
*/ |
next_context_status_buffer_hw = (I915_READ(RING_CONTEXT_STATUS_PTR(ring)) |
& GEN8_CSB_PTR_MASK); |
|
/* |
* When the CSB registers are reset (also after power-up / gpu reset), |
* CSB write pointer is set to all 1's, which is not valid, use '5' in |
* this special case, so the first element read is CSB[0]. |
*/ |
if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) |
next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); |
|
ring->next_context_status_buffer = next_context_status_buffer_hw; |
DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
|
memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
1155,27 → 1530,84 |
*/ |
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
|
ret = intel_init_pipe_control(ring); |
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
|
return init_workarounds_ring(ring); |
} |
|
static int gen9_init_render_ring(struct intel_engine_cs *ring) |
{ |
int ret; |
|
ret = gen8_init_common_ring(ring); |
if (ret) |
return ret; |
|
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
|
return init_workarounds_ring(ring); |
} |
|
static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, |
u64 offset, unsigned flags) |
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
{ |
bool ppgtt = !(flags & I915_DISPATCH_SECURE); |
struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; |
struct intel_engine_cs *ring = req->ring; |
struct intel_ringbuffer *ringbuf = req->ringbuf; |
const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; |
int i, ret; |
|
ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); |
if (ret) |
return ret; |
|
intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); |
for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
|
intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i)); |
intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); |
intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i)); |
intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); |
} |
|
intel_logical_ring_emit(ringbuf, MI_NOOP); |
intel_logical_ring_advance(ringbuf); |
|
return 0; |
} |
|
static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
u64 offset, unsigned dispatch_flags) |
{ |
struct intel_ringbuffer *ringbuf = req->ringbuf; |
bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
int ret; |
|
ret = intel_logical_ring_begin(ringbuf, 4); |
/* Don't rely in hw updating PDPs, specially in lite-restore. |
* Ideally, we should set Force PD Restore in ctx descriptor, |
* but we can't. Force Restore would be a second option, but |
* it is unsafe in case of lite-restore (because the ctx is |
* not idle). PML4 is allocated during ppgtt init so this is |
* not needed in 48-bit.*/ |
if (req->ctx->ppgtt && |
(intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) { |
if (!USES_FULL_48BIT_PPGTT(req->i915) && |
!intel_vgpu_active(req->i915->dev)) { |
ret = intel_logical_ring_emit_pdps(req); |
if (ret) |
return ret; |
} |
|
req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring); |
} |
|
ret = intel_logical_ring_begin(req, 4); |
if (ret) |
return ret; |
|
/* FIXME(BDW): Address space and security selectors. */ |
intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
(ppgtt<<8) | |
(dispatch_flags & I915_DISPATCH_RS ? |
MI_BATCH_RESOURCE_STREAMER : 0)); |
intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); |
intel_logical_ring_emit(ringbuf, MI_NOOP); |
1217,10 → 1649,11 |
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
} |
|
static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, |
static int gen8_emit_flush(struct drm_i915_gem_request *request, |
u32 invalidate_domains, |
u32 unused) |
{ |
struct intel_ringbuffer *ringbuf = request->ringbuf; |
struct intel_engine_cs *ring = ringbuf->ring; |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
1227,21 → 1660,23 |
uint32_t cmd; |
int ret; |
|
ret = intel_logical_ring_begin(ringbuf, 4); |
ret = intel_logical_ring_begin(request, 4); |
if (ret) |
return ret; |
|
cmd = MI_FLUSH_DW + 1; |
|
if (ring == &dev_priv->ring[VCS]) { |
if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
MI_FLUSH_DW_STORE_INDEX | |
MI_FLUSH_DW_OP_STOREDW; |
} else { |
if (invalidate_domains & I915_GEM_DOMAIN_RENDER) |
cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
MI_FLUSH_DW_OP_STOREDW; |
/* We always require a command barrier so that subsequent |
* commands, such as breadcrumb interrupts, are strictly ordered |
* wrt the contents of the write cache being flushed to memory |
* (and thus being coherent from the CPU). |
*/ |
cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
|
if (invalidate_domains & I915_GEM_GPU_DOMAINS) { |
cmd |= MI_INVALIDATE_TLB; |
if (ring == &dev_priv->ring[VCS]) |
cmd |= MI_INVALIDATE_BSD; |
} |
|
intel_logical_ring_emit(ringbuf, cmd); |
1255,12 → 1690,14 |
return 0; |
} |
|
static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, |
static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
u32 invalidate_domains, |
u32 flush_domains) |
{ |
struct intel_ringbuffer *ringbuf = request->ringbuf; |
struct intel_engine_cs *ring = ringbuf->ring; |
u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
bool vf_flush_wa; |
u32 flags = 0; |
int ret; |
|
1269,6 → 1706,7 |
if (flush_domains) { |
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
flags |= PIPE_CONTROL_FLUSH_ENABLE; |
} |
|
if (invalidate_domains) { |
1282,11 → 1720,27 |
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
} |
|
ret = intel_logical_ring_begin(ringbuf, 6); |
/* |
* On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe |
* control. |
*/ |
vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && |
flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; |
|
ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
if (ret) |
return ret; |
|
if (vf_flush_wa) { |
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
intel_logical_ring_emit(ringbuf, 0); |
intel_logical_ring_emit(ringbuf, 0); |
intel_logical_ring_emit(ringbuf, 0); |
intel_logical_ring_emit(ringbuf, 0); |
intel_logical_ring_emit(ringbuf, 0); |
} |
|
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
intel_logical_ring_emit(ringbuf, flags); |
intel_logical_ring_emit(ringbuf, scratch_addr); |
intel_logical_ring_emit(ringbuf, 0); |
1307,17 → 1761,51 |
intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
} |
|
static int gen8_emit_request(struct intel_ringbuffer *ringbuf) |
static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
{ |
|
/* |
* On BXT A steppings there is a HW coherency issue whereby the |
* MI_STORE_DATA_IMM storing the completed request's seqno |
* occasionally doesn't invalidate the CPU cache. Work around this by |
* clflushing the corresponding cacheline whenever the caller wants |
* the coherency to be guaranteed. Note that this cacheline is known |
* to be clean at this point, since we only write it in |
* bxt_a_set_seqno(), where we also do a clflush after the write. So |
* this clflush in practice becomes an invalidate operation. |
*/ |
|
if (!lazy_coherency) |
intel_flush_status_page(ring, I915_GEM_HWS_INDEX); |
|
return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
} |
|
static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
{ |
intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
|
/* See bxt_a_get_seqno() explaining the reason for the clflush. */ |
intel_flush_status_page(ring, I915_GEM_HWS_INDEX); |
} |
|
static int gen8_emit_request(struct drm_i915_gem_request *request) |
{ |
struct intel_ringbuffer *ringbuf = request->ringbuf; |
struct intel_engine_cs *ring = ringbuf->ring; |
u32 cmd; |
int ret; |
|
ret = intel_logical_ring_begin(ringbuf, 6); |
/* |
* Reserve space for 2 NOOPs at the end of each request to be |
* used as a workaround for not being allowed to do lite |
* restore with HEAD==TAIL (WaIdleLiteRestore). |
*/ |
ret = intel_logical_ring_begin(request, 8); |
if (ret) |
return ret; |
|
cmd = MI_STORE_DWORD_IMM_GEN8; |
cmd = MI_STORE_DWORD_IMM_GEN4; |
cmd |= MI_GLOBAL_GTT; |
|
intel_logical_ring_emit(ringbuf, cmd); |
1325,14 → 1813,71 |
(ring->status_page.gfx_addr + |
(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); |
intel_logical_ring_emit(ringbuf, 0); |
intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno); |
intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
intel_logical_ring_emit(ringbuf, MI_NOOP); |
intel_logical_ring_advance_and_submit(ringbuf); |
intel_logical_ring_advance_and_submit(request); |
|
/* |
* Here we add two extra NOOPs as padding to avoid |
* lite restore of a context with HEAD==TAIL. |
*/ |
intel_logical_ring_emit(ringbuf, MI_NOOP); |
intel_logical_ring_emit(ringbuf, MI_NOOP); |
intel_logical_ring_advance(ringbuf); |
|
return 0; |
} |
|
static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
{ |
struct render_state so; |
int ret; |
|
ret = i915_gem_render_state_prepare(req->ring, &so); |
if (ret) |
return ret; |
|
if (so.rodata == NULL) |
return 0; |
|
ret = req->ring->emit_bb_start(req, so.ggtt_offset, |
I915_DISPATCH_SECURE); |
if (ret) |
goto out; |
|
ret = req->ring->emit_bb_start(req, |
(so.ggtt_offset + so.aux_batch_offset), |
I915_DISPATCH_SECURE); |
if (ret) |
goto out; |
|
i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
|
out: |
i915_gem_render_state_fini(&so); |
return ret; |
} |
|
static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
{ |
int ret; |
|
ret = intel_logical_ring_workarounds_emit(req); |
if (ret) |
return ret; |
|
ret = intel_rcs_context_init_mocs(req); |
/* |
* Failing to program the MOCS is non-fatal.The system will not |
* run at peak performance. So generate an error and carry on. |
*/ |
if (ret) |
DRM_ERROR("MOCS failed to program: expect performance issues.\n"); |
|
return intel_lr_context_render_state_init(req); |
} |
|
/** |
* intel_logical_ring_cleanup() - deallocate the Engine Command Streamer |
* |
1350,18 → 1895,19 |
|
intel_logical_ring_stop(ring); |
WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
ring->preallocated_lazy_request = NULL; |
ring->outstanding_lazy_seqno = 0; |
|
if (ring->cleanup) |
ring->cleanup(ring); |
|
i915_cmd_parser_fini_ring(ring); |
i915_gem_batch_pool_fini(&ring->batch_pool); |
|
if (ring->status_page.obj) { |
kunmap(sg_page(ring->status_page.obj->pages->sgl)); |
ring->status_page.obj = NULL; |
} |
|
lrc_destroy_wa_ctx_obj(ring); |
} |
|
static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) |
1374,25 → 1920,33 |
ring->dev = dev; |
INIT_LIST_HEAD(&ring->active_list); |
INIT_LIST_HEAD(&ring->request_list); |
i915_gem_batch_pool_init(dev, &ring->batch_pool); |
init_waitqueue_head(&ring->irq_queue); |
|
INIT_LIST_HEAD(&ring->execlist_queue); |
INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
spin_lock_init(&ring->execlist_lock); |
ring->next_context_status_buffer = 0; |
|
ret = i915_cmd_parser_init_ring(ring); |
if (ret) |
return ret; |
|
if (ring->init) { |
ret = ring->init(ring); |
ret = intel_lr_context_deferred_alloc(ring->default_context, ring); |
if (ret) |
return ret; |
|
/* As this is the default context, always pin it */ |
ret = intel_lr_context_do_pin( |
ring, |
ring->default_context->engine[ring->id].state, |
ring->default_context->engine[ring->id].ringbuf); |
if (ret) { |
DRM_ERROR( |
"Failed to pin and map ringbuffer %s: %d\n", |
ring->name, ret); |
return ret; |
} |
|
ret = intel_lr_context_deferred_create(ring->default_context, ring); |
|
return ret; |
} |
|
1400,6 → 1954,7 |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
int ret; |
|
ring->name = "render ring"; |
ring->id = RCS; |
1411,11 → 1966,19 |
if (HAS_L3_DPF(dev)) |
ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
|
ring->init = gen8_init_render_ring; |
ring->init_context = intel_logical_ring_workarounds_emit; |
if (INTEL_INFO(dev)->gen >= 9) |
ring->init_hw = gen9_init_render_ring; |
else |
ring->init_hw = gen8_init_render_ring; |
ring->init_context = gen8_init_rcs_context; |
ring->cleanup = intel_fini_pipe_control; |
if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
ring->get_seqno = bxt_a_get_seqno; |
ring->set_seqno = bxt_a_set_seqno; |
} else { |
ring->get_seqno = gen8_get_seqno; |
ring->set_seqno = gen8_set_seqno; |
} |
ring->emit_request = gen8_emit_request; |
ring->emit_flush = gen8_emit_flush_render; |
ring->irq_get = gen8_logical_ring_get_irq; |
1422,9 → 1985,31 |
ring->irq_put = gen8_logical_ring_put_irq; |
ring->emit_bb_start = gen8_emit_bb_start; |
|
return logical_ring_init(dev, ring); |
ring->dev = dev; |
|
ret = intel_init_pipe_control(ring); |
if (ret) |
return ret; |
|
ret = intel_init_workaround_bb(ring); |
if (ret) { |
/* |
* We continue even if we fail to initialize WA batch |
* because we only expect rare glitches but nothing |
* critical to prevent us from using GPU |
*/ |
DRM_ERROR("WA batch buffer initialization failed: %d\n", |
ret); |
} |
|
ret = logical_ring_init(dev, ring); |
if (ret) { |
lrc_destroy_wa_ctx_obj(ring); |
} |
|
return ret; |
} |
|
static int logical_bsd_ring_init(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
1438,9 → 2023,14 |
ring->irq_keep_mask = |
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
|
ring->init = gen8_init_common_ring; |
ring->init_hw = gen8_init_common_ring; |
if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
ring->get_seqno = bxt_a_get_seqno; |
ring->set_seqno = bxt_a_set_seqno; |
} else { |
ring->get_seqno = gen8_get_seqno; |
ring->set_seqno = gen8_set_seqno; |
} |
ring->emit_request = gen8_emit_request; |
ring->emit_flush = gen8_emit_flush; |
ring->irq_get = gen8_logical_ring_get_irq; |
1463,7 → 2053,7 |
ring->irq_keep_mask = |
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
|
ring->init = gen8_init_common_ring; |
ring->init_hw = gen8_init_common_ring; |
ring->get_seqno = gen8_get_seqno; |
ring->set_seqno = gen8_set_seqno; |
ring->emit_request = gen8_emit_request; |
1488,9 → 2078,14 |
ring->irq_keep_mask = |
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
|
ring->init = gen8_init_common_ring; |
ring->init_hw = gen8_init_common_ring; |
if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
ring->get_seqno = bxt_a_get_seqno; |
ring->set_seqno = bxt_a_set_seqno; |
} else { |
ring->get_seqno = gen8_get_seqno; |
ring->set_seqno = gen8_set_seqno; |
} |
ring->emit_request = gen8_emit_request; |
ring->emit_flush = gen8_emit_flush; |
ring->irq_get = gen8_logical_ring_get_irq; |
1513,9 → 2108,14 |
ring->irq_keep_mask = |
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
|
ring->init = gen8_init_common_ring; |
ring->init_hw = gen8_init_common_ring; |
if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
ring->get_seqno = bxt_a_get_seqno; |
ring->set_seqno = bxt_a_set_seqno; |
} else { |
ring->get_seqno = gen8_get_seqno; |
ring->set_seqno = gen8_set_seqno; |
} |
ring->emit_request = gen8_emit_request; |
ring->emit_flush = gen8_emit_flush; |
ring->irq_get = gen8_logical_ring_get_irq; |
1568,14 → 2168,8 |
goto cleanup_vebox_ring; |
} |
|
ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
if (ret) |
goto cleanup_bsd2_ring; |
|
return 0; |
|
cleanup_bsd2_ring: |
intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); |
cleanup_vebox_ring: |
intel_logical_ring_cleanup(&dev_priv->ring[VECS]); |
cleanup_blt_ring: |
1588,38 → 2182,49 |
return ret; |
} |
|
int intel_lr_context_render_state_init(struct intel_engine_cs *ring, |
struct intel_context *ctx) |
static u32 |
make_rpcs(struct drm_device *dev) |
{ |
struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
struct render_state so; |
struct drm_i915_file_private *file_priv = ctx->file_priv; |
struct drm_file *file = file_priv ? file_priv->file : NULL; |
int ret; |
u32 rpcs = 0; |
|
ret = i915_gem_render_state_prepare(ring, &so); |
if (ret) |
return ret; |
|
if (so.rodata == NULL) |
/* |
* No explicit RPCS request is needed to ensure full |
* slice/subslice/EU enablement prior to Gen9. |
*/ |
if (INTEL_INFO(dev)->gen < 9) |
return 0; |
|
ret = ring->emit_bb_start(ringbuf, |
so.ggtt_offset, |
I915_DISPATCH_SECURE); |
if (ret) |
goto out; |
/* |
* Starting in Gen9, render power gating can leave |
* slice/subslice/EU in a partially enabled state. We |
* must make an explicit request through RPCS for full |
* enablement. |
*/ |
if (INTEL_INFO(dev)->has_slice_pg) { |
rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
rpcs |= INTEL_INFO(dev)->slice_total << |
GEN8_RPCS_S_CNT_SHIFT; |
rpcs |= GEN8_RPCS_ENABLE; |
} |
|
i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); |
if (INTEL_INFO(dev)->has_subslice_pg) { |
rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
rpcs |= INTEL_INFO(dev)->subslice_per_slice << |
GEN8_RPCS_SS_CNT_SHIFT; |
rpcs |= GEN8_RPCS_ENABLE; |
} |
|
ret = __i915_add_request(ring, file, so.obj, NULL); |
/* intel_logical_ring_add_request moves object to inactive if it |
* fails */ |
out: |
i915_gem_render_state_fini(&so); |
return ret; |
if (INTEL_INFO(dev)->has_eu_pg) { |
rpcs |= INTEL_INFO(dev)->eu_per_subslice << |
GEN8_RPCS_EU_MIN_SHIFT; |
rpcs |= INTEL_INFO(dev)->eu_per_subslice << |
GEN8_RPCS_EU_MAX_SHIFT; |
rpcs |= GEN8_RPCS_ENABLE; |
} |
|
return rpcs; |
} |
|
static int |
populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, |
struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) |
1650,7 → 2255,7 |
|
/* The second page of the context object contains some fields which must |
* be set up prior to the first execution. */ |
page = i915_gem_object_get_page(ctx_obj, 1); |
page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
reg_state = kmap_atomic(page); |
|
/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM |
1665,7 → 2270,9 |
reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; |
reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); |
reg_state[CTX_CONTEXT_CONTROL+1] = |
_MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); |
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | |
CTX_CTRL_RS_CTX_ENABLE); |
reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
reg_state[CTX_RING_HEAD+1] = 0; |
reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); |
1690,9 → 2297,6 |
reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; |
reg_state[CTX_SECOND_BB_STATE+1] = 0; |
if (ring->id == RCS) { |
/* TODO: according to BSpec, the register state context |
* for CHV does not have these. OTOH, these registers do |
* exist in CHV. I'm waiting for a clarification */ |
reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
reg_state[CTX_BB_PER_CTX_PTR+1] = 0; |
reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; |
1699,7 → 2303,22 |
reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; |
reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; |
reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; |
if (ring->wa_ctx.obj) { |
struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; |
uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); |
|
reg_state[CTX_RCS_INDIRECT_CTX+1] = |
(ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | |
(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); |
|
reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = |
CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; |
|
reg_state[CTX_BB_PER_CTX_PTR+1] = |
(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | |
0x01; |
} |
} |
reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); |
reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; |
reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; |
1712,24 → 2331,34 |
reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); |
reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); |
reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); |
reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); |
reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); |
reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); |
reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); |
reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); |
reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); |
reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); |
reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); |
|
if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
/* 64b PPGTT (48bit canonical) |
* PDP0_DESCRIPTOR contains the base address to PML4 and |
* other PDP Descriptors are ignored. |
*/ |
ASSIGN_CTX_PML4(ppgtt, reg_state); |
} else { |
/* 32b PPGTT |
* PDP*_DESCRIPTOR contains the base address of space supported. |
* With dynamic page allocation, PDPs may not be allocated at |
* this point. Point the unallocated PDPs to the scratch page |
*/ |
ASSIGN_CTX_PDP(ppgtt, reg_state, 3); |
ASSIGN_CTX_PDP(ppgtt, reg_state, 2); |
ASSIGN_CTX_PDP(ppgtt, reg_state, 1); |
ASSIGN_CTX_PDP(ppgtt, reg_state, 0); |
} |
|
if (ring->id == RCS) { |
reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; |
reg_state[CTX_R_PWR_CLK_STATE+1] = 0; |
reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; |
reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); |
} |
|
kunmap_atomic(reg_state); |
|
ctx_obj->dirty = 1; |
// set_page_dirty(page); |
i915_gem_object_unpin_pages(ctx_obj); |
|
return 0; |
1759,8 → 2388,8 |
intel_unpin_ringbuffer_obj(ringbuf); |
i915_gem_object_ggtt_unpin(ctx_obj); |
} |
intel_destroy_ringbuffer_obj(ringbuf); |
kfree(ringbuf); |
WARN_ON(ctx->engine[ring->id].pin_count); |
intel_ringbuffer_free(ringbuf); |
drm_gem_object_unreference(&ctx_obj->base); |
} |
} |
1794,12 → 2423,13 |
struct drm_i915_gem_object *default_ctx_obj) |
{ |
struct drm_i915_private *dev_priv = ring->dev->dev_private; |
struct page *page; |
|
/* The status page is offset 0 from the default context object |
* in LRC mode. */ |
ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); |
ring->status_page.page_addr = |
kmap(sg_page(default_ctx_obj->pages->sgl)); |
/* The HWSP is part of the default context object in LRC mode. */ |
ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj) |
+ LRC_PPHWSP_PN * PAGE_SIZE; |
page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN); |
ring->status_page.page_addr = kmap(page); |
ring->status_page.obj = default_ctx_obj; |
|
I915_WRITE(RING_HWS_PGA(ring->mmio_base), |
1808,7 → 2438,7 |
} |
|
/** |
* intel_lr_context_deferred_create() - create the LRC specific bits of a context |
* intel_lr_context_deferred_alloc() - create the LRC specific bits of a context |
* @ctx: LR context to create. |
* @ring: engine to be used with the context. |
* |
1820,10 → 2450,10 |
* |
* Return: non-zero on error. |
*/ |
int intel_lr_context_deferred_create(struct intel_context *ctx, |
|
int intel_lr_context_deferred_alloc(struct intel_context *ctx, |
struct intel_engine_cs *ring) |
{ |
const bool is_global_default_ctx = (ctx == ring->default_context); |
struct drm_device *dev = ring->dev; |
struct drm_i915_gem_object *ctx_obj; |
uint32_t context_size; |
1831,108 → 2461,96 |
int ret; |
|
WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
if (ctx->engine[ring->id].state) |
return 0; |
WARN_ON(ctx->engine[ring->id].state); |
|
context_size = round_up(get_lr_context_size(ring), 4096); |
|
ctx_obj = i915_gem_alloc_context_obj(dev, context_size); |
if (IS_ERR(ctx_obj)) { |
ret = PTR_ERR(ctx_obj); |
DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); |
return ret; |
/* One extra page as the sharing data between driver and GuC */ |
context_size += PAGE_SIZE * LRC_PPHWSP_PN; |
|
ctx_obj = i915_gem_alloc_object(dev, context_size); |
if (!ctx_obj) { |
DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
return -ENOMEM; |
} |
|
if (is_global_default_ctx) { |
ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); |
if (ret) { |
DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", |
ret); |
drm_gem_object_unreference(&ctx_obj->base); |
return ret; |
ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE); |
if (IS_ERR(ringbuf)) { |
ret = PTR_ERR(ringbuf); |
goto error_deref_obj; |
} |
} |
|
ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
if (!ringbuf) { |
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", |
ring->name); |
ret = -ENOMEM; |
goto error_unpin_ctx; |
ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); |
if (ret) { |
DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); |
goto error_ringbuf; |
} |
|
ringbuf->ring = ring; |
ringbuf->FIXME_lrc_ctx = ctx; |
ctx->engine[ring->id].ringbuf = ringbuf; |
ctx->engine[ring->id].state = ctx_obj; |
|
ringbuf->size = 32 * PAGE_SIZE; |
ringbuf->effective_size = ringbuf->size; |
ringbuf->head = 0; |
ringbuf->tail = 0; |
ringbuf->space = ringbuf->size; |
ringbuf->last_retired_head = -1; |
if (ctx != ring->default_context && ring->init_context) { |
struct drm_i915_gem_request *req; |
|
if (ringbuf->obj == NULL) { |
ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
ret = i915_gem_request_alloc(ring, |
ctx, &req); |
if (ret) { |
DRM_DEBUG_DRIVER( |
"Failed to allocate ringbuffer obj %s: %d\n", |
ring->name, ret); |
goto error_free_rbuf; |
DRM_ERROR("ring create req: %d\n", |
ret); |
goto error_ringbuf; |
} |
|
if (is_global_default_ctx) { |
ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
ret = ring->init_context(req); |
if (ret) { |
DRM_ERROR( |
"Failed to pin and map ringbuffer %s: %d\n", |
ring->name, ret); |
goto error_destroy_rbuf; |
DRM_ERROR("ring init context: %d\n", |
ret); |
i915_gem_request_cancel(req); |
goto error_ringbuf; |
} |
i915_add_request_no_flush(req); |
} |
return 0; |
|
error_ringbuf: |
intel_ringbuffer_free(ringbuf); |
error_deref_obj: |
drm_gem_object_unreference(&ctx_obj->base); |
ctx->engine[ring->id].ringbuf = NULL; |
ctx->engine[ring->id].state = NULL; |
return ret; |
} |
|
ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); |
if (ret) { |
DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); |
goto error; |
} |
void intel_lr_context_reset(struct drm_device *dev, |
struct intel_context *ctx) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_engine_cs *ring; |
int i; |
|
ctx->engine[ring->id].ringbuf = ringbuf; |
ctx->engine[ring->id].state = ctx_obj; |
for_each_ring(ring, dev_priv, i) { |
struct drm_i915_gem_object *ctx_obj = |
ctx->engine[ring->id].state; |
struct intel_ringbuffer *ringbuf = |
ctx->engine[ring->id].ringbuf; |
uint32_t *reg_state; |
struct page *page; |
|
if (ctx == ring->default_context) |
lrc_setup_hardware_status_page(ring, ctx_obj); |
if (!ctx_obj) |
continue; |
|
if (ring->id == RCS && !ctx->rcs_initialized) { |
if (ring->init_context) { |
ret = ring->init_context(ring, ctx); |
if (ret) |
DRM_ERROR("ring init context: %d\n", ret); |
if (i915_gem_object_get_pages(ctx_obj)) { |
WARN(1, "Failed get_pages for context obj\n"); |
continue; |
} |
page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
reg_state = kmap_atomic(page); |
|
ret = intel_lr_context_render_state_init(ring, ctx); |
if (ret) { |
DRM_ERROR("Init render state failed: %d\n", ret); |
ctx->engine[ring->id].ringbuf = NULL; |
ctx->engine[ring->id].state = NULL; |
goto error; |
} |
ctx->rcs_initialized = true; |
} |
reg_state[CTX_RING_HEAD+1] = 0; |
reg_state[CTX_RING_TAIL+1] = 0; |
|
return 0; |
kunmap_atomic(reg_state); |
|
error: |
if (is_global_default_ctx) |
intel_unpin_ringbuffer_obj(ringbuf); |
error_destroy_rbuf: |
intel_destroy_ringbuffer_obj(ringbuf); |
error_free_rbuf: |
kfree(ringbuf); |
error_unpin_ctx: |
if (is_global_default_ctx) |
i915_gem_object_ggtt_unpin(ctx_obj); |
drm_gem_object_unreference(&ctx_obj->base); |
return ret; |
ringbuf->head = 0; |
ringbuf->tail = 0; |
} |
} |