31,7 → 31,6 |
struct intel_dsi_device { |
unsigned int panel_id; |
const char *name; |
int type; |
const struct intel_dsi_dev_ops *dev_ops; |
void *dev_priv; |
}; |
85,6 → 84,9 |
/* virtual channel */ |
int channel; |
|
/* Video mode or command mode */ |
u16 operation_mode; |
|
/* number of DSI lanes */ |
unsigned int lane_count; |
|
95,8 → 97,10 |
u32 video_mode_format; |
|
/* eot for MIPI_EOT_DISABLE register */ |
u32 eot_disable; |
u8 eotp_pkt; |
u8 clock_stop; |
|
u8 escape_clk_div; |
u32 port_bits; |
u32 bw_timer; |
u32 dphy_reg; |
110,6 → 114,15 |
u16 hs_to_lp_count; |
u16 clk_lp_to_hs_count; |
u16 clk_hs_to_lp_count; |
|
u16 init_count; |
|
/* all delays in ms */ |
u16 backlight_off_delay; |
u16 backlight_on_delay; |
u16 panel_on_delay; |
u16 panel_off_delay; |
u16 panel_pwr_cycle_delay; |
}; |
|
static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) |
119,5 → 132,8 |
|
extern void vlv_enable_dsi_pll(struct intel_encoder *encoder); |
extern void vlv_disable_dsi_pll(struct intel_encoder *encoder); |
extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); |
|
extern struct intel_dsi_dev_ops vbt_generic_dsi_display_ops; |
|
#endif /* _INTEL_DSI_H */ |