26,6 → 26,7 |
#define __INTEL_DRV_H__ |
|
#include <linux/i2c.h> |
#include <linux/hdmi.h> |
#include <drm/i915_drm.h> |
#include "i915_drv.h" |
#include <drm/drm_crtc.h> |
64,29 → 65,11 |
ret__; \ |
}) |
|
#define wait_for_atomic_us(COND, US) ({ \ |
unsigned long timeout__ = GetTimerTicks() + usecs_to_jiffies(US); \ |
int ret__ = 0; \ |
while (!(COND)) { \ |
if (time_after(GetTimerTicks(), timeout__)) { \ |
ret__ = -ETIMEDOUT; \ |
break; \ |
} \ |
cpu_relax(); \ |
} \ |
ret__; \ |
}) |
|
#define wait_for(COND, MS) _wait_for(COND, MS, 1) |
#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
#define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
DIV_ROUND_UP((US), 1000), 0) |
|
#define MSLEEP(x) do { \ |
if (in_dbg_master()) \ |
mdelay(x); \ |
else \ |
msleep(x); \ |
} while(0) |
|
#define KHz(x) (1000*x) |
#define MHz(x) KHz(1000*x) |
|
143,7 → 126,6 |
struct intel_crtc *new_crtc; |
|
int type; |
bool needs_tv_clock; |
/* |
* Intel hw has only one MUX where encoders could be clone, hence a |
* simple flag is enough to compute the possible_clones mask. |
163,6 → 145,12 |
* the encoder is active. If the encoder is enabled it also set the pipe |
* it is connected to in the pipe parameter. */ |
bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
/* Reconstructs the equivalent mode flags for the current hardware |
* state. This must be called _after_ display->get_pipe_config has |
* pre-filled the pipe config. Note that intel_encoder->base.crtc must |
* be set correctly before calling this function. */ |
void (*get_config)(struct intel_encoder *, |
struct intel_crtc_config *pipe_config); |
int crtc_mask; |
enum hpd_pin hpd_pin; |
}; |
200,13 → 188,32 |
u8 polled; |
}; |
|
typedef struct dpll { |
/* given values */ |
int n; |
int m1, m2; |
int p1, p2; |
/* derived values */ |
int dot; |
int vco; |
int m; |
int p; |
} intel_clock_t; |
|
struct intel_crtc_config { |
/** |
* quirks - bitfield with hw state readout quirks |
* |
* For various reasons the hw state readout code might not be able to |
* completely faithfully read out the current state. These cases are |
* tracked with quirk flags so that fastboot and state checker can act |
* accordingly. |
*/ |
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
unsigned long quirks; |
|
struct drm_display_mode requested_mode; |
struct drm_display_mode adjusted_mode; |
/* This flag must be set by the encoder's compute_config callback if it |
* changes the crtc timings in the mode to prevent the crtc fixup from |
* overwriting them. Currently only lvds needs that. */ |
bool timings_set; |
/* Whether to set up the PCH/FDI. Note that we never allow sharing |
* between pch encoders and cpu encoders. */ |
bool has_pch_encoder; |
224,29 → 231,68 |
/* DP has a bunch of special case unfortunately, so mark the pipe |
* accordingly. */ |
bool has_dp_encoder; |
|
/* |
* Enable dithering, used when the selected pipe bpp doesn't match the |
* plane bpp. |
*/ |
bool dither; |
|
/* Controls for the clock computation, to override various stages. */ |
bool clock_set; |
|
/* SDVO TV has a bunch of special case. To make multifunction encoders |
* work correctly, we need to track this at runtime.*/ |
bool sdvo_tv_clock; |
|
/* |
* crtc bandwidth limit, don't increase pipe bpp or clock if not really |
* required. This is set in the 2nd loop of calling encoder's |
* ->compute_config if the first pick doesn't work out. |
*/ |
bool bw_constrained; |
|
/* Settings for the intel dpll used on pretty much everything but |
* haswell. */ |
struct dpll { |
unsigned n; |
unsigned m1, m2; |
unsigned p1, p2; |
} dpll; |
struct dpll dpll; |
|
/* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
enum intel_dpll_id shared_dpll; |
|
/* Actual register state of the dpll, for shared dpll cross-checking. */ |
struct intel_dpll_hw_state dpll_hw_state; |
|
int pipe_bpp; |
struct intel_link_m_n dp_m_n; |
/** |
* This is currently used by DP and HDMI encoders since those can have a |
* target pixel clock != the port link clock (which is currently stored |
* in adjusted_mode->clock). |
|
/* |
* Frequence the dpll for the port should run at. Differs from the |
* adjusted dotclock e.g. for DP or 12bpc hdmi mode. |
*/ |
int pixel_target_clock; |
int port_clock; |
|
/* Used by SDVO (and if we ever fix it, HDMI). */ |
unsigned pixel_multiplier; |
|
/* Panel fitter controls for gen2-gen4 + VLV */ |
struct { |
u32 control; |
u32 pgm_ratios; |
u32 lvds_border_bits; |
} gmch_pfit; |
|
/* Panel fitter placement and size for Ironlake+ */ |
struct { |
u32 pos; |
u32 size; |
bool enabled; |
} pch_pfit; |
|
/* FDI configuration, only valid if has_pch_encoder is set. */ |
int fdi_lanes; |
struct intel_link_m_n fdi_m_n; |
|
bool ips_enabled; |
}; |
|
struct intel_crtc { |
265,7 → 311,6 |
bool lowfreq_avail; |
struct intel_overlay *overlay; |
struct intel_unpin_work *unpin_work; |
int fdi_lanes; |
|
atomic_t unpin_work_count; |
|
282,14 → 327,23 |
|
struct intel_crtc_config config; |
|
/* We can share PLLs across outputs if the timings match */ |
struct intel_pch_pll *pch_pll; |
uint32_t ddi_pll_sel; |
|
/* reset counter value when the last flip was submitted */ |
unsigned int reset_counter; |
|
/* Access to these should be protected by dev_priv->irq_lock. */ |
bool cpu_fifo_underrun_disabled; |
bool pch_fifo_underrun_disabled; |
}; |
|
struct intel_plane_wm_parameters { |
uint32_t horiz_pixels; |
uint8_t bytes_per_pixel; |
bool enabled; |
bool scaled; |
}; |
|
struct intel_plane { |
struct drm_plane base; |
int plane; |
302,7 → 356,16 |
unsigned int crtc_w, crtc_h; |
uint32_t src_x, src_y; |
uint32_t src_w, src_h; |
|
/* Since we need to change the watermarks before/after |
* enabling/disabling the planes, we need to store the parameters here |
* as the other pieces of the struct may not reflect the values we want |
* for the watermark calculations. Currently only Haswell uses this. |
*/ |
struct intel_plane_wm_parameters wm; |
|
void (*update_plane)(struct drm_plane *plane, |
struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_i915_gem_object *obj, |
int crtc_x, int crtc_y, |
309,7 → 372,8 |
unsigned int crtc_w, unsigned int crtc_h, |
uint32_t x, uint32_t y, |
uint32_t src_w, uint32_t src_h); |
void (*disable_plane)(struct drm_plane *plane); |
void (*disable_plane)(struct drm_plane *plane, |
struct drm_crtc *crtc); |
int (*update_colorkey)(struct drm_plane *plane, |
struct drm_intel_sprite_colorkey *key); |
void (*get_colorkey)(struct drm_plane *plane, |
341,66 → 405,6 |
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
#define to_intel_plane(x) container_of(x, struct intel_plane, base) |
|
#define DIP_HEADER_SIZE 5 |
|
#define DIP_TYPE_AVI 0x82 |
#define DIP_VERSION_AVI 0x2 |
#define DIP_LEN_AVI 13 |
#define DIP_AVI_PR_1 0 |
#define DIP_AVI_PR_2 1 |
#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2) |
#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2) |
#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2) |
|
#define DIP_TYPE_SPD 0x83 |
#define DIP_VERSION_SPD 0x1 |
#define DIP_LEN_SPD 25 |
#define DIP_SPD_UNKNOWN 0 |
#define DIP_SPD_DSTB 0x1 |
#define DIP_SPD_DVDP 0x2 |
#define DIP_SPD_DVHS 0x3 |
#define DIP_SPD_HDDVR 0x4 |
#define DIP_SPD_DVC 0x5 |
#define DIP_SPD_DSC 0x6 |
#define DIP_SPD_VCD 0x7 |
#define DIP_SPD_GAME 0x8 |
#define DIP_SPD_PC 0x9 |
#define DIP_SPD_BD 0xa |
#define DIP_SPD_SCD 0xb |
|
struct dip_infoframe { |
uint8_t type; /* HB0 */ |
uint8_t ver; /* HB1 */ |
uint8_t len; /* HB2 - body len, not including checksum */ |
uint8_t ecc; /* Header ECC */ |
uint8_t checksum; /* PB0 */ |
union { |
struct { |
/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ |
uint8_t Y_A_B_S; |
/* PB2 - C 7:6, M 5:4, R 3:0 */ |
uint8_t C_M_R; |
/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ |
uint8_t ITC_EC_Q_SC; |
/* PB4 - VIC 6:0 */ |
uint8_t VIC; |
/* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
uint8_t YQ_CN_PR; |
/* PB6 to PB13 */ |
uint16_t top_bar_end; |
uint16_t bottom_bar_start; |
uint16_t left_bar_end; |
uint16_t right_bar_start; |
} __attribute__ ((packed)) avi; |
struct { |
uint8_t vn[8]; |
uint8_t pd[16]; |
uint8_t sdi; |
} __attribute__ ((packed)) spd; |
uint8_t payload[27]; |
} __attribute__ ((packed)) body; |
} __attribute__((packed)); |
|
struct intel_hdmi { |
u32 hdmi_reg; |
int ddc_bus; |
411,7 → 415,8 |
enum hdmi_force_audio force_audio; |
bool rgb_quant_range_selectable; |
void (*write_infoframe)(struct drm_encoder *encoder, |
struct dip_infoframe *frame); |
enum hdmi_infoframe_type type, |
const uint8_t *frame, ssize_t len); |
void (*set_infoframes)(struct drm_encoder *encoder, |
struct drm_display_mode *adjusted_mode); |
}; |
431,10 → 436,10 |
uint8_t link_bw; |
uint8_t lane_count; |
uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
struct i2c_adapter adapter; |
struct i2c_algo_dp_aux_data algo; |
bool is_pch_edp; |
uint8_t train_set[4]; |
int panel_power_up_delay; |
int panel_power_down_delay; |
443,6 → 448,7 |
int backlight_off_delay; |
struct delayed_work panel_vdd_work; |
bool want_panel_vdd; |
bool psr_setup_done; |
struct intel_connector *attached_connector; |
}; |
|
449,11 → 455,24 |
struct intel_digital_port { |
struct intel_encoder base; |
enum port port; |
u32 port_reversal; |
u32 saved_port_bits; |
struct intel_dp dp; |
struct intel_hdmi hdmi; |
}; |
|
static inline int |
vlv_dport_to_channel(struct intel_digital_port *dport) |
{ |
switch (dport->port) { |
case PORT_B: |
return 0; |
case PORT_C: |
return 1; |
default: |
BUG(); |
} |
} |
|
static inline struct drm_crtc * |
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
{ |
481,13 → 500,6 |
bool enable_stall_check; |
}; |
|
struct intel_fbc_work { |
struct delayed_work work; |
struct drm_crtc *crtc; |
struct drm_framebuffer *fb; |
int interval; |
}; |
|
int intel_pch_rawclk(struct drm_device *dev); |
|
int intel_connector_update_modes(struct drm_connector *connector, |
497,6 → 509,7 |
extern void intel_attach_force_audio_property(struct drm_connector *connector); |
extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
|
extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
extern void intel_crt_init(struct drm_device *dev); |
extern void intel_hdmi_init(struct drm_device *dev, |
int hdmi_reg, enum port port); |
505,19 → 518,19 |
extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
struct intel_crtc_config *pipe_config); |
extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
bool is_sdvob); |
extern void intel_dvo_init(struct drm_device *dev); |
extern void intel_tv_init(struct drm_device *dev); |
extern void intel_mark_busy(struct drm_device *dev); |
extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); |
extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
struct intel_ring_buffer *ring); |
extern void intel_mark_idle(struct drm_device *dev); |
extern bool intel_lvds_init(struct drm_device *dev); |
extern void intel_lvds_init(struct drm_device *dev); |
extern bool intel_is_dual_link_lvds(struct drm_device *dev); |
extern void intel_dp_init(struct drm_device *dev, int output_reg, |
enum port port); |
extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
struct intel_connector *intel_connector); |
extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
535,7 → 548,6 |
extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
enum plane plane); |
545,14 → 557,16 |
struct drm_display_mode *fixed_mode); |
extern void intel_panel_fini(struct intel_panel *panel); |
|
extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
struct drm_display_mode *adjusted_mode); |
extern void intel_pch_panel_fitting(struct drm_device *dev, |
int fitting_mode, |
const struct drm_display_mode *mode, |
struct drm_display_mode *adjusted_mode); |
extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); |
extern void intel_pch_panel_fitting(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config, |
int fitting_mode); |
extern void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config, |
int fitting_mode); |
extern void intel_panel_set_backlight(struct drm_device *dev, |
u32 level, u32 max); |
extern int intel_panel_setup_backlight(struct drm_connector *connector); |
extern void intel_panel_enable_backlight(struct drm_device *dev, |
enum pipe pipe); |
568,19 → 582,15 |
bool mode_changed; |
}; |
|
extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
int x, int y, struct drm_framebuffer *old_fb); |
extern void intel_modeset_disable(struct drm_device *dev); |
extern void intel_crtc_restore_mode(struct drm_crtc *crtc); |
extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
extern void intel_encoder_destroy(struct drm_encoder *encoder); |
extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); |
extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); |
extern void intel_connector_dpms(struct drm_connector *, int mode); |
extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
extern void intel_modeset_check_state(struct drm_device *dev); |
extern void intel_plane_restore(struct drm_plane *plane); |
extern void intel_plane_disable(struct drm_plane *plane); |
|
|
static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
588,13 → 598,6 |
return to_intel_connector(connector)->encoder; |
} |
|
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
{ |
struct intel_digital_port *intel_dig_port = |
container_of(encoder, struct intel_digital_port, base.base); |
return &intel_dig_port->dp; |
} |
|
static inline struct intel_digital_port * |
enc_to_dig_port(struct drm_encoder *encoder) |
{ |
601,6 → 604,11 |
return container_of(encoder, struct intel_digital_port, base.base); |
} |
|
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
{ |
return &enc_to_dig_port(encoder)->dp; |
} |
|
static inline struct intel_digital_port * |
dp_to_dig_port(struct intel_dp *intel_dp) |
{ |
630,6 → 638,7 |
extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); |
|
struct intel_load_detect_pipe { |
struct drm_framebuffer *release_fb; |
642,12 → 651,10 |
extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
struct intel_load_detect_pipe *old); |
|
extern void intelfb_restore(void); |
extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
u16 blue, int regno); |
extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
u16 *blue, int regno); |
extern void intel_enable_clock_gating(struct drm_device *dev); |
|
extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
struct drm_i915_gem_object *obj, |
658,6 → 665,7 |
struct intel_framebuffer *ifb, |
struct drm_mode_fb_cmd2 *mode_cmd, |
struct drm_i915_gem_object *obj); |
extern void intel_framebuffer_fini(struct intel_framebuffer *fb); |
extern int intel_fbdev_init(struct drm_device *dev); |
extern void intel_fbdev_initial_config(struct drm_device *dev); |
extern void intel_fbdev_fini(struct drm_device *dev); |
677,6 → 685,22 |
extern void intel_fb_output_poll_changed(struct drm_device *dev); |
extern void intel_fb_restore_mode(struct drm_device *dev); |
|
struct intel_shared_dpll * |
intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
|
void assert_shared_dpll(struct drm_i915_private *dev_priv, |
struct intel_shared_dpll *pll, |
bool state); |
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
void assert_pll(struct drm_i915_private *dev_priv, |
enum pipe pipe, bool state); |
#define assert_pll_enabled(d, p) assert_pll(d, p, true) |
#define assert_pll_disabled(d, p) assert_pll(d, p, false) |
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
enum pipe pipe, bool state); |
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
bool state); |
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
683,13 → 707,9 |
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
|
extern void intel_init_clock_gating(struct drm_device *dev); |
extern void intel_suspend_hw(struct drm_device *dev); |
extern void intel_write_eld(struct drm_encoder *encoder, |
struct drm_display_mode *mode); |
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
struct intel_link_m_n *m_n); |
extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
struct intel_link_m_n *m_n); |
extern void intel_prepare_ddi(struct drm_device *dev); |
extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
extern void intel_ddi_init(struct drm_device *dev, enum port port); |
696,11 → 716,10 |
|
/* For use by IVB LP watermark workaround in intel_sprite.c */ |
extern void intel_update_watermarks(struct drm_device *dev); |
extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
uint32_t sprite_width, |
int pixel_size); |
extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
struct drm_display_mode *mode); |
extern void intel_update_sprite_watermarks(struct drm_plane *plane, |
struct drm_crtc *crtc, |
uint32_t sprite_width, int pixel_size, |
bool enabled, bool scaled); |
|
extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
unsigned int tiling_mode, |
712,25 → 731,27 |
extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
struct drm_file *file_priv); |
|
extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
|
/* Power-related functions, located in intel_pm.c */ |
extern void intel_init_pm(struct drm_device *dev); |
/* FBC */ |
extern bool intel_fbc_enabled(struct drm_device *dev); |
extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); |
extern void intel_update_fbc(struct drm_device *dev); |
/* IPS */ |
extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
extern void intel_gpu_ips_teardown(void); |
|
extern bool intel_using_power_well(struct drm_device *dev); |
/* Power well */ |
extern int i915_init_power_well(struct drm_device *dev); |
extern void i915_remove_power_well(struct drm_device *dev); |
|
extern bool intel_display_power_enabled(struct drm_device *dev, |
enum intel_display_power_domain domain); |
extern void intel_init_power_well(struct drm_device *dev); |
extern void intel_set_power_well(struct drm_device *dev, bool enable); |
extern void intel_enable_gt_powersave(struct drm_device *dev); |
extern void intel_disable_gt_powersave(struct drm_device *dev); |
extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
extern void ironlake_teardown_rc6(struct drm_device *dev); |
void gen6_update_ring_freq(struct drm_device *dev); |
|
extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
enum pipe *pipe); |
742,7 → 763,7 |
extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); |
extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc); |
extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
751,5 → 772,31 |
extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
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extern void intel_display_handle_reset(struct drm_device *dev); |
extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
enum pipe pipe, |
bool enable); |
extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
enum transcoder pch_transcoder, |
bool enable); |
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extern void intel_edp_psr_enable(struct intel_dp *intel_dp); |
extern void intel_edp_psr_disable(struct intel_dp *intel_dp); |
extern void intel_edp_psr_update(struct drm_device *dev); |
extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
bool switch_to_fclk, bool allow_power_down); |
extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv); |
extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, |
uint32_t mask); |
extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv, |
uint32_t mask); |
extern void hsw_enable_pc8_work(struct work_struct *__work); |
extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv); |
extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv); |
extern void hsw_pc8_disable_interrupts(struct drm_device *dev); |
extern void hsw_pc8_restore_interrupts(struct drm_device *dev); |
extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); |
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#endif /* __INTEL_DRV_H__ */ |