| 35,13 → 35,23 |
|---|
| |
| #define KBUILD_MODNAME "i915.dll" |
| |
| |
| #define cpu_relax() asm volatile("rep; nop") |
| |
| /** |
| * _wait_for - magic (register) wait macro |
| * |
| * Does the right thing for modeset paths when run under kdgb or similar atomic |
| * contexts. Note that it's important that we check the condition again after |
| * having timed out, since the timeout could be due to preemption or similar and |
| * we've never had a chance to check the condition before the timeout. |
| */ |
| #define _wait_for(COND, MS, W) ({ \ |
| unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS); \ |
| int ret__ = 0; \ |
| while (!(COND)) { \ |
| if (time_after(GetTimerTicks(), timeout__)) { \ |
| if (!(COND)) \ |
| ret__ = -ETIMEDOUT; \ |
| break; \ |
| } \ |
| 112,34 → 122,6 |
|---|
| #define INTEL_DVO_CHIP_TMDS 2 |
| #define INTEL_DVO_CHIP_TVOUT 4 |
| |
| /* drm_display_mode->private_flags */ |
| #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) |
| #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) |
| #define INTEL_MODE_DP_FORCE_6BPC (0x10) |
| /* This flag must be set by the encoder's mode_fixup if it changes the crtc |
| * timings in the mode to prevent the crtc fixup from overwriting them. |
| * Currently only lvds needs that. */ |
| #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) |
| /* |
| * Set when limited 16-235 (as opposed to full 0-255) RGB color range is |
| * to be used. |
| */ |
| #define INTEL_MODE_LIMITED_COLOR_RANGE (0x40) |
| |
| static inline void |
| intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, |
| int multiplier) |
| { |
| mode->clock *= multiplier; |
| mode->private_flags |= multiplier; |
| } |
| |
| static inline int |
| intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) |
| { |
| return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; |
| } |
| |
| struct intel_framebuffer { |
| struct drm_framebuffer base; |
| struct drm_i915_gem_object *obj; |
| 169,9 → 151,12 |
|---|
| bool cloneable; |
| bool connectors_active; |
| void (*hot_plug)(struct intel_encoder *); |
| bool (*compute_config)(struct intel_encoder *, |
| struct intel_crtc_config *); |
| void (*pre_pll_enable)(struct intel_encoder *); |
| void (*pre_enable)(struct intel_encoder *); |
| void (*enable)(struct intel_encoder *); |
| void (*mode_set)(struct intel_encoder *intel_encoder); |
| void (*disable)(struct intel_encoder *); |
| void (*post_disable)(struct intel_encoder *); |
| /* Read out the current hw state of this connector, returning true if |
| 179,6 → 164,7 |
|---|
| * it is connected to in the pipe parameter. */ |
| bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
| int crtc_mask; |
| enum hpd_pin hpd_pin; |
| }; |
| |
| struct intel_panel { |
| 208,13 → 194,65 |
|---|
| |
| /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
| struct edid *edid; |
| |
| /* since POLL and HPD connectors may use the same HPD line keep the native |
| state of connector->polled in case hotplug storm detection changes it */ |
| u8 polled; |
| }; |
| |
| struct intel_crtc_config { |
| struct drm_display_mode requested_mode; |
| struct drm_display_mode adjusted_mode; |
| /* This flag must be set by the encoder's compute_config callback if it |
| * changes the crtc timings in the mode to prevent the crtc fixup from |
| * overwriting them. Currently only lvds needs that. */ |
| bool timings_set; |
| /* Whether to set up the PCH/FDI. Note that we never allow sharing |
| * between pch encoders and cpu encoders. */ |
| bool has_pch_encoder; |
| |
| /* CPU Transcoder for the pipe. Currently this can only differ from the |
| * pipe on Haswell (where we have a special eDP transcoder). */ |
| enum transcoder cpu_transcoder; |
| |
| /* |
| * Use reduced/limited/broadcast rbg range, compressing from the full |
| * range fed into the crtcs. |
| */ |
| bool limited_color_range; |
| |
| /* DP has a bunch of special case unfortunately, so mark the pipe |
| * accordingly. */ |
| bool has_dp_encoder; |
| bool dither; |
| |
| /* Controls for the clock computation, to override various stages. */ |
| bool clock_set; |
| |
| /* Settings for the intel dpll used on pretty much everything but |
| * haswell. */ |
| struct dpll { |
| unsigned n; |
| unsigned m1, m2; |
| unsigned p1, p2; |
| } dpll; |
| |
| int pipe_bpp; |
| struct intel_link_m_n dp_m_n; |
| /** |
| * This is currently used by DP and HDMI encoders since those can have a |
| * target pixel clock != the port link clock (which is currently stored |
| * in adjusted_mode->clock). |
| */ |
| int pixel_target_clock; |
| /* Used by SDVO (and if we ever fix it, HDMI). */ |
| unsigned pixel_multiplier; |
| }; |
| |
| struct intel_crtc { |
| struct drm_crtc base; |
| enum pipe pipe; |
| enum plane plane; |
| enum transcoder cpu_transcoder; |
| u8 lut_r[256], lut_g[256], lut_b[256]; |
| /* |
| * Whether the crtc and the connected output pipeline is active. Implies |
| 241,8 → 279,9 |
|---|
| int16_t cursor_x, cursor_y; |
| int16_t cursor_width, cursor_height; |
| bool cursor_visible; |
| unsigned int bpp; |
| |
| struct intel_crtc_config config; |
| |
| /* We can share PLLs across outputs if the timings match */ |
| struct intel_pch_pll *pch_pll; |
| uint32_t ddi_pll_sel; |
| 253,11 → 292,16 |
|---|
| |
| struct intel_plane { |
| struct drm_plane base; |
| int plane; |
| enum pipe pipe; |
| struct drm_i915_gem_object *obj; |
| bool can_scale; |
| int max_downscale; |
| u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
| int crtc_x, crtc_y; |
| unsigned int crtc_w, crtc_h; |
| uint32_t src_x, src_y; |
| uint32_t src_w, src_h; |
| void (*update_plane)(struct drm_plane *plane, |
| struct drm_framebuffer *fb, |
| struct drm_i915_gem_object *obj, |
| 358,7 → 402,7 |
|---|
| } __attribute__((packed)); |
| |
| struct intel_hdmi { |
| u32 sdvox_reg; |
| u32 hdmi_reg; |
| int ddc_bus; |
| uint32_t color_range; |
| bool color_range_auto; |
| 377,6 → 421,7 |
|---|
| |
| struct intel_dp { |
| uint32_t output_reg; |
| uint32_t aux_ch_ctl_reg; |
| uint32_t DP; |
| uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
| bool has_audio; |
| 454,13 → 499,12 |
|---|
| |
| extern void intel_crt_init(struct drm_device *dev); |
| extern void intel_hdmi_init(struct drm_device *dev, |
| int sdvox_reg, enum port port); |
| int hdmi_reg, enum port port); |
| extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| struct intel_connector *intel_connector); |
| extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
| const struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode); |
| extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
| struct intel_crtc_config *pipe_config); |
| extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
| extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
| bool is_sdvob); |
| 475,18 → 519,15 |
|---|
| enum port port); |
| extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| struct intel_connector *intel_connector); |
| void |
| intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode); |
| extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
| extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
| extern void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
| extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| extern void intel_dp_check_link_status(struct intel_dp *intel_dp); |
| extern bool intel_dp_mode_fixup(struct drm_encoder *encoder, |
| const struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode); |
| extern bool intel_dp_compute_config(struct intel_encoder *encoder, |
| struct intel_crtc_config *pipe_config); |
| extern bool intel_dpd_is_edp(struct drm_device *dev); |
| extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
| extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
| 494,11 → 535,8 |
|---|
| extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
| extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
| extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
| extern void intel_edp_link_config(struct intel_encoder *, int *, int *); |
| extern int intel_edp_target_clock(struct intel_encoder *, |
| struct drm_display_mode *mode); |
| extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
| extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); |
| extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
| extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
| enum plane plane); |
| |
| 542,6 → 580,7 |
|---|
| extern void intel_connector_dpms(struct drm_connector *, int mode); |
| extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
| extern void intel_modeset_check_state(struct drm_device *dev); |
| extern void intel_plane_restore(struct drm_plane *plane); |
| |
| |
| static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
| 647,6 → 686,10 |
|---|
| extern void intel_write_eld(struct drm_encoder *encoder, |
| struct drm_display_mode *mode); |
| extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
| extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
| struct intel_link_m_n *m_n); |
| extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
| struct intel_link_m_n *m_n); |
| extern void intel_prepare_ddi(struct drm_device *dev); |
| extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
| extern void intel_ddi_init(struct drm_device *dev, enum port port); |
| 681,6 → 724,7 |
|---|
| extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| extern void intel_gpu_ips_teardown(void); |
| |
| extern bool intel_using_power_well(struct drm_device *dev); |
| extern void intel_init_power_well(struct drm_device *dev); |
| extern void intel_set_power_well(struct drm_device *dev, bool enable); |
| extern void intel_enable_gt_powersave(struct drm_device *dev); |
| 692,7 → 736,7 |
|---|
| enum pipe *pipe); |
| extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
| extern void intel_ddi_pll_init(struct drm_device *dev); |
| extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); |
| extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
| extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| enum transcoder cpu_transcoder); |
| extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| 706,4 → 750,6 |
|---|
| intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
| |
| extern void intel_display_handle_reset(struct drm_device *dev); |
| |
| #endif /* __INTEL_DRV_H__ */ |