| 24,7 → 24,7 |
|---|
| * Eric Anholt <eric@anholt.net> |
| */ |
| |
| //#include <linux/dmi.h> |
| #include <linux/dmi.h> |
| #include <linux/module.h> |
| //#include <linux/input.h> |
| #include <linux/i2c.h> |
| 2244,6 → 2244,15 |
|---|
| if (need_vtd_wa(dev) && alignment < 256 * 1024) |
| alignment = 256 * 1024; |
| |
| /* |
| * Global gtt pte registers are special registers which actually forward |
| * writes to a chunk of system memory. Which means that there is no risk |
| * that the register values disappear as soon as we call |
| * intel_runtime_pm_put(), so it is correct to wrap only the |
| * pin/unpin/fence and not more. |
| */ |
| intel_runtime_pm_get(dev_priv); |
| |
| dev_priv->mm.interruptible = false; |
| ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
| if (ret) |
| 2261,6 → 2270,7 |
|---|
| i915_gem_object_pin_fence(obj); |
| |
| dev_priv->mm.interruptible = true; |
| intel_runtime_pm_put(dev_priv); |
| return 0; |
| |
| err_unpin: |
| 2267,6 → 2277,7 |
|---|
| i915_gem_object_unpin_from_display_plane(obj); |
| err_interruptible: |
| dev_priv->mm.interruptible = true; |
| intel_runtime_pm_put(dev_priv); |
| return ret; |
| } |
| |
| 4184,10 → 4195,6 |
|---|
| intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
| |
| intel_disable_pipe(dev_priv, pipe); |
| |
| if (intel_crtc->config.dp_encoder_is_mst) |
| intel_ddi_set_vc_payload_alloc(crtc, false); |
| |
| ironlake_pfit_disable(intel_crtc); |
| |
| for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4252,6 → 4259,9 |
|---|
| intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
| intel_disable_pipe(dev_priv, pipe); |
| |
| if (intel_crtc->config.dp_encoder_is_mst) |
| intel_ddi_set_vc_payload_alloc(crtc, false); |
| |
| intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
| |
| ironlake_pfit_disable(intel_crtc); |
| 8238,6 → 8248,15 |
|---|
| goto fail_locked; |
| } |
| |
| /* |
| * Global gtt pte registers are special registers which actually |
| * forward writes to a chunk of system memory. Which means that |
| * there is no risk that the register values disappear as soon |
| * as we call intel_runtime_pm_put(), so it is correct to wrap |
| * only the pin/unpin/fence and not more. |
| */ |
| intel_runtime_pm_get(dev_priv); |
| |
| /* Note that the w/a also requires 2 PTE of padding following |
| * the bo. We currently fill all unused PTE with the shadow |
| * page and so we should always have valid PTE following the |
| 8250,6 → 8269,7 |
|---|
| ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
| if (ret) { |
| DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
| intel_runtime_pm_put(dev_priv); |
| goto fail_locked; |
| } |
| |
| 8256,10 → 8276,13 |
|---|
| ret = i915_gem_object_put_fence(obj); |
| if (ret) { |
| DRM_DEBUG_KMS("failed to release fence for cursor"); |
| intel_runtime_pm_put(dev_priv); |
| goto fail_unpin; |
| } |
| |
| addr = i915_gem_obj_ggtt_offset(obj); |
| |
| intel_runtime_pm_put(dev_priv); |
| } else { |
| int align = IS_I830(dev) ? 16 * 1024 : 256; |
| // ret = i915_gem_object_attach_phys(obj, align); |
| 12186,6 → 12209,9 |
|---|
| /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
| { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
| |
| /* Acer C720 Chromebook (Core i3 4005U) */ |
| { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, |
| |
| /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
| { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
| |
| 12208,7 → 12234,11 |
|---|
| q->subsystem_device == PCI_ANY_ID)) |
| q->hook(dev); |
| } |
| for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
| if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
| intel_dmi_quirks[i].hook(dev); |
| } |
| } |
| |
| /* Disable the VGA plane that we never use */ |
| static void i915_disable_vga(struct drm_device *dev) |