133,12 → 133,12 |
{ 0x00002016, 0x000000A0, 0x0 }, |
{ 0x00005012, 0x0000009B, 0x0 }, |
{ 0x00007011, 0x00000088, 0x0 }, |
{ 0x00009010, 0x000000C7, 0x0 }, |
{ 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
{ 0x00002016, 0x0000009B, 0x0 }, |
{ 0x00005012, 0x00000088, 0x0 }, |
{ 0x00007011, 0x000000C7, 0x0 }, |
{ 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
{ 0x00002016, 0x000000DF, 0x0 }, |
{ 0x00005012, 0x000000C7, 0x0 }, |
{ 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
}; |
|
/* Skylake U */ |
146,12 → 146,12 |
{ 0x0000201B, 0x000000A2, 0x0 }, |
{ 0x00005012, 0x00000088, 0x0 }, |
{ 0x00007011, 0x00000087, 0x0 }, |
{ 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */ |
{ 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
{ 0x0000201B, 0x0000009D, 0x0 }, |
{ 0x00005012, 0x000000C7, 0x0 }, |
{ 0x00007011, 0x000000C7, 0x0 }, |
{ 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
{ 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
{ 0x00002016, 0x00000088, 0x0 }, |
{ 0x00005012, 0x000000C7, 0x0 }, |
{ 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ |
}; |
|
/* Skylake Y */ |
159,12 → 159,12 |
{ 0x00000018, 0x000000A2, 0x0 }, |
{ 0x00005012, 0x00000088, 0x0 }, |
{ 0x00007011, 0x00000087, 0x0 }, |
{ 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */ |
{ 0x80009010, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
{ 0x00000018, 0x0000009D, 0x0 }, |
{ 0x00005012, 0x000000C7, 0x0 }, |
{ 0x00007011, 0x000000C7, 0x0 }, |
{ 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
{ 0x80007011, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
{ 0x00000018, 0x00000088, 0x0 }, |
{ 0x00005012, 0x000000C7, 0x0 }, |
{ 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ |
}; |
|
/* |
345,7 → 345,7 |
static bool |
intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) |
{ |
return intel_dig_port->hdmi.hdmi_reg; |
return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg); |
} |
|
static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, |
353,10 → 353,10 |
{ |
const struct ddi_buf_trans *ddi_translations; |
|
if (IS_SKL_ULX(dev)) { |
if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
ddi_translations = skl_y_ddi_translations_dp; |
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
} else if (IS_SKL_ULT(dev)) { |
} else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { |
ddi_translations = skl_u_ddi_translations_dp; |
*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
} else { |
373,7 → 373,7 |
struct drm_i915_private *dev_priv = dev->dev_private; |
const struct ddi_buf_trans *ddi_translations; |
|
if (IS_SKL_ULX(dev)) { |
if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
if (dev_priv->edp_low_vswing) { |
ddi_translations = skl_y_ddi_translations_edp; |
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
381,7 → 381,7 |
ddi_translations = skl_y_ddi_translations_dp; |
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
} |
} else if (IS_SKL_ULT(dev)) { |
} else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { |
if (dev_priv->edp_low_vswing) { |
ddi_translations = skl_u_ddi_translations_edp; |
*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
408,7 → 408,7 |
{ |
const struct ddi_buf_trans *ddi_translations; |
|
if (IS_SKL_ULX(dev)) { |
if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { |
ddi_translations = skl_y_ddi_translations_hdmi; |
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
} else { |
448,7 → 448,7 |
bxt_ddi_vswing_sequence(dev, hdmi_level, port, |
INTEL_OUTPUT_HDMI); |
return; |
} else if (IS_SKYLAKE(dev)) { |
} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
ddi_translations_fdi = NULL; |
ddi_translations_dp = |
skl_get_buf_trans_dp(dev, &n_dp_entries); |
584,7 → 584,7 |
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
enum port port) |
{ |
uint32_t reg = DDI_BUF_CTL(port); |
i915_reg_t reg = DDI_BUF_CTL(port); |
int i; |
|
for (i = 0; i < 16; i++) { |
683,15 → 683,16 |
temp = I915_READ(DP_TP_STATUS(PORT_E)); |
if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { |
DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
break; |
} |
|
/* Enable normal pixel sending for FDI */ |
I915_WRITE(DP_TP_CTL(PORT_E), |
DP_TP_CTL_FDI_AUTOTRAIN | |
DP_TP_CTL_LINK_TRAIN_NORMAL | |
DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
DP_TP_CTL_ENABLE); |
|
return; |
/* |
* Leave things enabled even if we failed to train FDI. |
* Results in less fireworks from the state checker. |
*/ |
if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { |
DRM_ERROR("FDI link training failed!\n"); |
break; |
} |
|
temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
720,7 → 721,12 |
POSTING_READ(FDI_RX_MISC(PIPE_A)); |
} |
|
DRM_ERROR("FDI link training failed!\n"); |
/* Enable normal pixel sending for FDI */ |
I915_WRITE(DP_TP_CTL(PORT_E), |
DP_TP_CTL_FDI_AUTOTRAIN | |
DP_TP_CTL_LINK_TRAIN_NORMAL | |
DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
DP_TP_CTL_ENABLE); |
} |
|
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
939,7 → 945,8 |
/* Otherwise a < c && b >= d, do nothing */ |
} |
|
static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg) |
static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
i915_reg_t reg) |
{ |
int refclk = LC_FREQ; |
int n, p, r; |
975,7 → 982,7 |
static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
uint32_t dpll) |
{ |
uint32_t cfgcr1_reg, cfgcr2_reg; |
i915_reg_t cfgcr1_reg, cfgcr2_reg; |
uint32_t cfgcr1_val, cfgcr2_val; |
uint32_t p0, p1, p2, dco_freq; |
|
1120,10 → 1127,10 |
link_clock = 270000; |
break; |
case PORT_CLK_SEL_WRPLL1: |
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); |
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
break; |
case PORT_CLK_SEL_WRPLL2: |
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); |
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
break; |
case PORT_CLK_SEL_SPLL: |
pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; |
1192,7 → 1199,7 |
|
if (INTEL_INFO(dev)->gen <= 8) |
hsw_ddi_clock_get(encoder, pipe_config); |
else if (IS_SKYLAKE(dev)) |
else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
skl_ddi_clock_get(encoder, pipe_config); |
else if (IS_BROXTON(dev)) |
bxt_ddi_clock_get(encoder, pipe_config); |
1789,7 → 1796,7 |
struct intel_encoder *intel_encoder = |
intel_ddi_get_crtc_new_encoder(crtc_state); |
|
if (IS_SKYLAKE(dev)) |
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
return skl_ddi_pll_select(intel_crtc, crtc_state, |
intel_encoder); |
else if (IS_BROXTON(dev)) |
1951,7 → 1958,7 |
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
enum transcoder cpu_transcoder) |
{ |
uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
uint32_t val = I915_READ(reg); |
|
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
1970,13 → 1977,16 |
enum transcoder cpu_transcoder; |
enum intel_display_power_domain power_domain; |
uint32_t tmp; |
bool ret; |
|
power_domain = intel_display_port_power_domain(intel_encoder); |
if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
return false; |
|
if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
return false; |
if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { |
ret = false; |
goto out; |
} |
|
if (port == PORT_A) |
cpu_transcoder = TRANSCODER_EDP; |
1988,23 → 1998,33 |
switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { |
case TRANS_DDI_MODE_SELECT_HDMI: |
case TRANS_DDI_MODE_SELECT_DVI: |
return (type == DRM_MODE_CONNECTOR_HDMIA); |
ret = type == DRM_MODE_CONNECTOR_HDMIA; |
break; |
|
case TRANS_DDI_MODE_SELECT_DP_SST: |
if (type == DRM_MODE_CONNECTOR_eDP) |
return true; |
return (type == DRM_MODE_CONNECTOR_DisplayPort); |
ret = type == DRM_MODE_CONNECTOR_eDP || |
type == DRM_MODE_CONNECTOR_DisplayPort; |
break; |
|
case TRANS_DDI_MODE_SELECT_DP_MST: |
/* if the transcoder is in MST state then |
* connector isn't connected */ |
return false; |
ret = false; |
break; |
|
case TRANS_DDI_MODE_SELECT_FDI: |
return (type == DRM_MODE_CONNECTOR_VGA); |
ret = type == DRM_MODE_CONNECTOR_VGA; |
break; |
|
default: |
return false; |
ret = false; |
break; |
} |
|
out: |
intel_display_power_put(dev_priv, power_domain); |
|
return ret; |
} |
|
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
2016,15 → 2036,18 |
enum intel_display_power_domain power_domain; |
u32 tmp; |
int i; |
bool ret; |
|
power_domain = intel_display_port_power_domain(encoder); |
if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
return false; |
|
ret = false; |
|
tmp = I915_READ(DDI_BUF_CTL(port)); |
|
if (!(tmp & DDI_BUF_CTL_ENABLE)) |
return false; |
goto out; |
|
if (port == PORT_A) { |
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
2042,25 → 2065,32 |
break; |
} |
|
return true; |
} else { |
ret = true; |
|
goto out; |
} |
|
for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); |
|
if ((tmp & TRANS_DDI_PORT_MASK) |
== TRANS_DDI_SELECT_PORT(port)) { |
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) |
return false; |
if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { |
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == |
TRANS_DDI_MODE_SELECT_DP_MST) |
goto out; |
|
*pipe = i; |
return true; |
ret = true; |
|
goto out; |
} |
} |
} |
|
DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
|
return false; |
out: |
intel_display_power_put(dev_priv, power_domain); |
|
return ret; |
} |
|
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
2106,7 → 2136,7 |
iboost = dp_iboost; |
} else { |
ddi_translations = skl_get_buf_trans_dp(dev, &n_entries); |
iboost = ddi_translations[port].i_boost; |
iboost = ddi_translations[level].i_boost; |
} |
} else if (type == INTEL_OUTPUT_EDP) { |
if (dp_iboost) { |
2113,7 → 2143,7 |
iboost = dp_iboost; |
} else { |
ddi_translations = skl_get_buf_trans_edp(dev, &n_entries); |
iboost = ddi_translations[port].i_boost; |
iboost = ddi_translations[level].i_boost; |
} |
} else if (type == INTEL_OUTPUT_HDMI) { |
if (hdmi_iboost) { |
2120,7 → 2150,7 |
iboost = hdmi_iboost; |
} else { |
ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries); |
iboost = ddi_translations[port].i_boost; |
iboost = ddi_translations[level].i_boost; |
} |
} else { |
return; |
2272,7 → 2302,7 |
|
level = translate_signal_level(signal_levels); |
|
if (IS_SKYLAKE(dev)) |
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
skl_ddi_set_iboost(dev, level, port, encoder->type); |
else if (IS_BROXTON(dev)) |
bxt_ddi_vswing_sequence(dev, level, port, encoder->type); |
2280,23 → 2310,14 |
return DDI_BUF_TRANS_SELECT(level); |
} |
|
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
void intel_ddi_clk_select(struct intel_encoder *encoder, |
const struct intel_crtc_state *pipe_config) |
{ |
struct drm_encoder *encoder = &intel_encoder->base; |
struct drm_device *dev = encoder->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
enum port port = intel_ddi_get_encoder_port(intel_encoder); |
int type = intel_encoder->type; |
int hdmi_level; |
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
enum port port = intel_ddi_get_encoder_port(encoder); |
|
if (type == INTEL_OUTPUT_EDP) { |
struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
intel_edp_panel_on(intel_dp); |
} |
|
if (IS_SKYLAKE(dev)) { |
uint32_t dpll = crtc->config->ddi_pll_sel; |
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
uint32_t dpll = pipe_config->ddi_pll_sel; |
uint32_t val; |
|
/* |
2303,7 → 2324,7 |
* DPLL0 is used for eDP and is the only "private" DPLL (as |
* opposed to shared) on SKL |
*/ |
if (type == INTEL_OUTPUT_EDP) { |
if (encoder->type == INTEL_OUTPUT_EDP) { |
WARN_ON(dpll != SKL_DPLL0); |
|
val = I915_READ(DPLL_CTRL1); |
2311,7 → 2332,7 |
val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | |
DPLL_CTRL1_SSC(dpll) | |
DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); |
val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6); |
|
I915_WRITE(DPLL_CTRL1, val); |
POSTING_READ(DPLL_CTRL1); |
2327,11 → 2348,29 |
|
I915_WRITE(DPLL_CTRL2, val); |
|
} else if (INTEL_INFO(dev)->gen < 9) { |
WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); |
I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); |
} else if (INTEL_INFO(dev_priv)->gen < 9) { |
WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE); |
I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel); |
} |
} |
|
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
{ |
struct drm_encoder *encoder = &intel_encoder->base; |
struct drm_device *dev = encoder->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
enum port port = intel_ddi_get_encoder_port(intel_encoder); |
int type = intel_encoder->type; |
int hdmi_level; |
|
if (type == INTEL_OUTPUT_EDP) { |
struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
intel_edp_panel_on(intel_dp); |
} |
|
intel_ddi_clk_select(intel_encoder, crtc->config); |
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
|
2390,7 → 2429,7 |
intel_edp_panel_off(intel_dp); |
} |
|
if (IS_SKYLAKE(dev)) |
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
DPLL_CTRL2_DDI_CLK_OFF(port))); |
else if (INTEL_INFO(dev)->gen < 9) |
2500,12 → 2539,14 |
{ |
uint32_t val; |
|
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
return false; |
|
val = I915_READ(WRPLL_CTL(pll->id)); |
hw_state->wrpll = val; |
|
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
|
return val & WRPLL_PLL_ENABLE; |
} |
|
2515,12 → 2556,14 |
{ |
uint32_t val; |
|
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
return false; |
|
val = I915_READ(SPLL_CTL); |
hw_state->spll = val; |
|
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
|
return val & SPLL_PLL_ENABLE; |
} |
|
2562,7 → 2605,7 |
}; |
|
struct skl_dpll_regs { |
u32 ctl, cfgcr1, cfgcr2; |
i915_reg_t ctl, cfgcr1, cfgcr2; |
}; |
|
/* this array is indexed by the *shared* pll id */ |
2575,13 → 2618,13 |
}, |
{ |
/* DPLL 2 */ |
.ctl = WRPLL_CTL1, |
.ctl = WRPLL_CTL(0), |
.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), |
.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), |
}, |
{ |
/* DPLL 3 */ |
.ctl = WRPLL_CTL2, |
.ctl = WRPLL_CTL(1), |
.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), |
.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), |
}, |
2637,16 → 2680,19 |
uint32_t val; |
unsigned int dpll; |
const struct skl_dpll_regs *regs = skl_dpll_regs; |
bool ret; |
|
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
return false; |
|
ret = false; |
|
/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
dpll = pll->id + 1; |
|
val = I915_READ(regs[pll->id].ctl); |
if (!(val & LCPLL_PLL_ENABLE)) |
return false; |
goto out; |
|
val = I915_READ(DPLL_CTRL1); |
hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; |
2656,8 → 2702,12 |
hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); |
hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); |
} |
ret = true; |
|
return true; |
out: |
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
|
return ret; |
} |
|
static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) |
2924,13 → 2974,16 |
{ |
enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
uint32_t val; |
bool ret; |
|
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
return false; |
|
ret = false; |
|
val = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
if (!(val & PORT_PLL_ENABLE)) |
return false; |
goto out; |
|
hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); |
hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; |
2977,7 → 3030,12 |
I915_READ(BXT_PORT_PCS_DW12_LN23(port))); |
hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; |
|
return true; |
ret = true; |
|
out: |
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
|
return ret; |
} |
|
static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) |
3001,7 → 3059,7 |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t val = I915_READ(LCPLL_CTL); |
|
if (IS_SKYLAKE(dev)) |
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
skl_shared_dplls_init(dev_priv); |
else if (IS_BROXTON(dev)) |
bxt_shared_dplls_init(dev_priv); |
3008,15 → 3066,15 |
else |
hsw_shared_dplls_init(dev_priv); |
|
if (IS_SKYLAKE(dev)) { |
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
int cdclk_freq; |
|
cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
dev_priv->skl_boot_cdclk = cdclk_freq; |
if (skl_sanitize_cdclk(dev_priv)) |
DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); |
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) |
DRM_ERROR("LCPLL1 is disabled\n"); |
else |
intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
} else if (IS_BROXTON(dev)) { |
broxton_init_cdclk(dev); |
broxton_ddi_phy_init(dev); |
3035,11 → 3093,11 |
} |
} |
|
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) |
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
{ |
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
struct intel_dp *intel_dp = &intel_dig_port->dp; |
struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
struct drm_i915_private *dev_priv = |
to_i915(intel_dig_port->base.base.dev); |
enum port port = intel_dig_port->port; |
uint32_t val; |
bool wait = false; |
3150,7 → 3208,7 |
pipe_config->has_hdmi_sink = true; |
intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
|
if (intel_hdmi->infoframe_enabled(&encoder->base)) |
if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
pipe_config->has_infoframe = true; |
break; |
case TRANS_DDI_MODE_SELECT_DVI: |
3278,7 → 3336,7 |
encoder = &intel_encoder->base; |
|
drm_encoder_init(dev, encoder, &intel_ddi_funcs, |
DRM_MODE_ENCODER_TMDS); |
DRM_MODE_ENCODER_TMDS, NULL); |
|
intel_encoder->compute_config = intel_ddi_compute_config; |
intel_encoder->enable = intel_enable_ddi; |
3294,6 → 3352,20 |
(DDI_BUF_PORT_REVERSAL | |
DDI_A_4_LANES); |
|
/* |
* Bspec says that DDI_A_4_LANES is the only supported configuration |
* for Broxton. Yet some BIOS fail to set this bit on port A if eDP |
* wasn't lit up at boot. Force this bit on in our internal |
* configuration so that we use the proper lane count for our |
* calculations. |
*/ |
if (IS_BROXTON(dev) && port == PORT_A) { |
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); |
intel_dig_port->saved_port_bits |= DDI_A_4_LANES; |
} |
} |
|
intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
intel_encoder->cloneable = 0; |
3307,8 → 3379,7 |
* On BXT A0/A1, sw needs to activate DDIA HPD logic and |
* interrupts to check the external panel connection. |
*/ |
if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) |
&& port == PORT_B) |
if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) |
dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; |
else |
dev_priv->hotplug.irq_port[port] = intel_dig_port; |