| 610,16 → 610,17 |
|---|
| #define IOSF_BYTE_ENABLES_SHIFT 4 |
| #define IOSF_BAR_SHIFT 1 |
| #define IOSF_SB_BUSY (1<<0) |
| #define IOSF_PORT_BUNIT 0x3 |
| #define IOSF_PORT_PUNIT 0x4 |
| #define IOSF_PORT_BUNIT 0x03 |
| #define IOSF_PORT_PUNIT 0x04 |
| #define IOSF_PORT_NC 0x11 |
| #define IOSF_PORT_DPIO 0x12 |
| #define IOSF_PORT_DPIO_2 0x1a |
| #define IOSF_PORT_GPIO_NC 0x13 |
| #define IOSF_PORT_CCK 0x14 |
| #define IOSF_PORT_CCU 0xA9 |
| #define IOSF_PORT_GPS_CORE 0x48 |
| #define IOSF_PORT_FLISDSI 0x1B |
| #define IOSF_PORT_DPIO_2 0x1a |
| #define IOSF_PORT_FLISDSI 0x1b |
| #define IOSF_PORT_GPIO_SC 0x48 |
| #define IOSF_PORT_GPIO_SUS 0xa8 |
| #define IOSF_PORT_CCU 0xa9 |
| #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) |
| #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) |
| |
| 1635,6 → 1636,9 |
|---|
| #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ |
| #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
| |
| #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4) |
| #define RING_MAX_NONPRIV_SLOTS 12 |
| |
| #define GEN7_TLB_RD_ADDR _MMIO(0x4700) |
| |
| #if 0 |
| 1711,6 → 1715,11 |
|---|
| #define FPGA_DBG _MMIO(0x42300) |
| #define FPGA_DBG_RM_NOCLAIM (1<<31) |
| |
| #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) |
| #define CLAIM_ER_CLR (1 << 31) |
| #define CLAIM_ER_OVERFLOW (1 << 16) |
| #define CLAIM_ER_CTR_MASK 0xffff |
| |
| #define DERRMR _MMIO(0x44050) |
| /* Note that HBLANK events are reserved on bdw+ */ |
| #define DERRMR_PIPEA_SCANLINE (1<<0) |
| 5948,6 → 5957,7 |
|---|
| #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) |
| #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) |
| #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) |
| #define IVB_PIPE_C_DISABLE (1 << 28) |
| #define ILK_HDCP_DISABLE (1 << 25) |
| #define ILK_eDP_A_DISABLE (1 << 24) |
| #define HSW_CDCLK_LIMIT (1 << 24) |
| 5994,10 → 6004,19 |
|---|
| #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) |
| #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) |
| #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) |
| #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) |
| #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) |
| #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) |
| |
| #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) |
| #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14) |
| |
| #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) |
| #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) |
| |
| #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) |
| #define GEN8_CS_CHICKEN1 _MMIO(0x2580) |
| |
| /* GEN7 chicken */ |
| #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) |
| # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
| 6043,6 → 6062,8 |
|---|
| #define HDC_FORCE_NON_COHERENT (1<<4) |
| #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) |
| |
| #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) |
| |
| /* GEN9 chicken */ |
| #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) |
| #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) |
| 6773,6 → 6794,16 |
|---|
| |
| #define VLV_PMWGICZ _MMIO(0x1300a4) |
| |
| #define RC6_LOCATION _MMIO(0xD40) |
| #define RC6_CTX_IN_DRAM (1 << 0) |
| #define RC6_CTX_BASE _MMIO(0xD48) |
| #define RC6_CTX_BASE_MASK 0xFFFFFFF0 |
| #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) |
| #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) |
| #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) |
| #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) |
| #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) |
| #define IDLE_TIME_MASK 0xFFFFF |
| #define FORCEWAKE _MMIO(0xA18C) |
| #define FORCEWAKE_VLV _MMIO(0x1300b0) |
| #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) |
| 6911,6 → 6942,7 |
|---|
| #define GEN6_RPDEUC _MMIO(0xA084) |
| #define GEN6_RPDEUCSW _MMIO(0xA088) |
| #define GEN6_RC_STATE _MMIO(0xA094) |
| #define RC6_STATE (1 << 18) |
| #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) |
| #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) |
| #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) |
| 7545,6 → 7577,7 |
|---|
| #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 |
| |
| #define DC_STATE_DEBUG _MMIO(0x45520) |
| #define DC_STATE_DEBUG_MASK_CORES (1<<0) |
| #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) |
| |
| /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
| 8164,4 → 8197,11 |
|---|
| #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ |
| #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ |
| |
| /* gamt regs */ |
| #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) |
| #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ |
| #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ |
| #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ |
| #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ |
| |
| #endif /* _I915_REG_H_ */ |