| 26,15 → 26,26 |
|---|
| #define _I915_REG_H_ |
| |
| #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
| #define _PLANE(plane, a, b) _PIPE(plane, a, b) |
| #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
| |
| #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
| #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ |
| (pipe) == PIPE_B ? (b) : (c)) |
| |
| #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) |
| #define _MASKED_BIT_DISABLE(a) ((a) << 16) |
| #define _MASKED_FIELD(mask, value) ({ \ |
| if (__builtin_constant_p(mask)) \ |
| BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ |
| if (__builtin_constant_p(value)) \ |
| BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ |
| if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ |
| BUILD_BUG_ON_MSG((value) & ~(mask), \ |
| "Incorrect value for mask"); \ |
| (mask) << 16 | (value); }) |
| #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) |
| #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) |
| |
| |
| |
| /* PCI config space */ |
| |
| #define HPLLCC 0xc0 /* 855 only */ |
| 74,15 → 85,17 |
|---|
| #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
| #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
| #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) |
| #define GCDGMBUS 0xcc |
| #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ |
| |
| |
| /* Graphics reset regs */ |
| #define I965_GDRST 0xc0 /* PCI config register */ |
| #define I915_GDRST 0xc0 /* PCI config register */ |
| #define GRDOM_FULL (0<<2) |
| #define GRDOM_RENDER (1<<2) |
| #define GRDOM_MEDIA (3<<2) |
| #define GRDOM_MASK (3<<2) |
| #define GRDOM_RESET_STATUS (1<<1) |
| #define GRDOM_RESET_ENABLE (1<<0) |
| |
| #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
| 143,6 → 156,14 |
|---|
| #define GAB_CTL 0x24000 |
| #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
| |
| #define GEN7_BIOS_RESERVED 0x1082C0 |
| #define GEN7_BIOS_RESERVED_1M (0 << 5) |
| #define GEN7_BIOS_RESERVED_256K (1 << 5) |
| #define GEN8_BIOS_RESERVED_SHIFT 7 |
| #define GEN7_BIOS_RESERVED_MASK 0x1 |
| #define GEN8_BIOS_RESERVED_MASK 0x3 |
| |
| |
| /* VGA stuff */ |
| |
| #define VGA_ST01_MDA 0x3ba |
| 240,6 → 261,16 |
|---|
| #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
| #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
| #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
| /* SKL ones */ |
| #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) |
| #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) |
| #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) |
| #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) |
| #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) |
| #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) |
| #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) |
| #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) |
| #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) |
| #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ |
| #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
| #define MI_SEMAPHORE_UPDATE (1<<21) |
| 272,6 → 303,7 |
|---|
| #define MI_SEMAPHORE_POLL (1<<15) |
| #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) |
| #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
| #define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2) |
| #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
| #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
| #define MI_STORE_DWORD_INDEX_SHIFT 2 |
| 282,6 → 314,7 |
|---|
| * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
| */ |
| #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) |
| #define MI_LRI_FORCE_POSTED (1<<12) |
| #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) |
| #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) |
| #define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
| 304,6 → 337,8 |
|---|
| #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
| #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) |
| |
| #define MI_PREDICATE_SRC0 (0x2400) |
| #define MI_PREDICATE_SRC1 (0x2408) |
| |
| #define MI_PREDICATE_RESULT_2 (0x2214) |
| #define LOWER_SLICE_ENABLED (1<<0) |
| 360,6 → 395,7 |
|---|
| #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
| #define PIPE_CONTROL_CS_STALL (1<<20) |
| #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
| #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) |
| #define PIPE_CONTROL_QW_WRITE (1<<14) |
| #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) |
| #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
| 501,10 → 537,26 |
|---|
| #define BUNIT_REG_BISOC 0x11 |
| |
| #define PUNIT_REG_DSPFREQ 0x36 |
| #define DSPFREQSTAT_SHIFT_CHV 24 |
| #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) |
| #define DSPFREQGUAR_SHIFT_CHV 8 |
| #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) |
| #define DSPFREQSTAT_SHIFT 30 |
| #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) |
| #define DSPFREQGUAR_SHIFT 14 |
| #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) |
| #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) |
| #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) |
| #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) |
| #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) |
| #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) |
| #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) |
| #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) |
| #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) |
| #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) |
| #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) |
| #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) |
| #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) |
| |
| /* See the PUNIT HAS v0.8 for the below bits */ |
| enum punit_power_well { |
| 518,6 → 570,11 |
|---|
| PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, |
| PUNIT_POWER_WELL_DPIO_RX0 = 10, |
| PUNIT_POWER_WELL_DPIO_RX1 = 11, |
| PUNIT_POWER_WELL_DPIO_CMN_D = 12, |
| /* FIXME: guesswork below */ |
| PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, |
| PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, |
| PUNIT_POWER_WELL_DPIO_RX2 = 15, |
| |
| PUNIT_POWER_WELL_NUM, |
| }; |
| 533,6 → 590,7 |
|---|
| #define PUNIT_REG_GPU_LFM 0xd3 |
| #define PUNIT_REG_GPU_FREQ_REQ 0xd4 |
| #define PUNIT_REG_GPU_FREQ_STS 0xd8 |
| #define GPLLENABLE (1<<4) |
| #define GENFREQSTATUS (1<<0) |
| #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc |
| #define PUNIT_REG_CZ_TIMESTAMP 0xce |
| 641,7 → 699,7 |
|---|
| * need to be accessed during AUX communication, |
| * |
| * Generally the common lane corresponds to the pipe and |
| * the spline (PCS/TX) correponds to the port. |
| * the spline (PCS/TX) corresponds to the port. |
| * |
| * For dual channel PHY (VLV/CHV): |
| * |
| 765,6 → 823,8 |
|---|
| #define _VLV_PCS_DW0_CH1 0x8400 |
| #define DPIO_PCS_TX_LANE2_RESET (1<<16) |
| #define DPIO_PCS_TX_LANE1_RESET (1<<7) |
| #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) |
| #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) |
| #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
| |
| #define _VLV_PCS01_DW0_CH0 0x200 |
| 805,12 → 865,31 |
|---|
| |
| #define _VLV_PCS_DW9_CH0 0x8224 |
| #define _VLV_PCS_DW9_CH1 0x8424 |
| #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) |
| #define DPIO_PCS_TX2MARGIN_000 (0<<13) |
| #define DPIO_PCS_TX2MARGIN_101 (1<<13) |
| #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) |
| #define DPIO_PCS_TX1MARGIN_000 (0<<10) |
| #define DPIO_PCS_TX1MARGIN_101 (1<<10) |
| #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
| |
| #define _VLV_PCS01_DW9_CH0 0x224 |
| #define _VLV_PCS23_DW9_CH0 0x424 |
| #define _VLV_PCS01_DW9_CH1 0x2624 |
| #define _VLV_PCS23_DW9_CH1 0x2824 |
| #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) |
| #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) |
| |
| #define _CHV_PCS_DW10_CH0 0x8228 |
| #define _CHV_PCS_DW10_CH1 0x8428 |
| #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) |
| #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) |
| #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) |
| #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) |
| #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) |
| #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) |
| #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) |
| #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) |
| #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
| |
| #define _VLV_PCS01_DW10_CH0 0x0228 |
| 822,8 → 901,18 |
|---|
| |
| #define _VLV_PCS_DW11_CH0 0x822c |
| #define _VLV_PCS_DW11_CH1 0x842c |
| #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) |
| #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) |
| #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) |
| #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
| |
| #define _VLV_PCS01_DW11_CH0 0x022c |
| #define _VLV_PCS23_DW11_CH0 0x042c |
| #define _VLV_PCS01_DW11_CH1 0x262c |
| #define _VLV_PCS23_DW11_CH1 0x282c |
| #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
| #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) |
| |
| #define _VLV_PCS_DW12_CH0 0x8230 |
| #define _VLV_PCS_DW12_CH1 0x8430 |
| #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
| 838,8 → 927,8 |
|---|
| |
| #define _VLV_TX_DW2_CH0 0x8288 |
| #define _VLV_TX_DW2_CH1 0x8488 |
| #define DPIO_SWING_MARGIN_SHIFT 16 |
| #define DPIO_SWING_MARGIN_MASK (0xff << DPIO_SWING_MARGIN_SHIFT) |
| #define DPIO_SWING_MARGIN000_SHIFT 16 |
| #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) |
| #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
| #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
| |
| 847,6 → 936,8 |
|---|
| #define _VLV_TX_DW3_CH1 0x848c |
| /* The following bit for CHV phy */ |
| #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) |
| #define DPIO_SWING_MARGIN101_SHIFT 16 |
| #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) |
| #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
| |
| #define _VLV_TX_DW4_CH0 0x8290 |
| 853,6 → 944,8 |
|---|
| #define _VLV_TX_DW4_CH1 0x8490 |
| #define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
| #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) |
| #define DPIO_SWING_DEEMPH6P0_SHIFT 16 |
| #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) |
| #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
| |
| #define _VLV_TX3_DW4_CH0 0x690 |
| 1003,6 → 1096,13 |
|---|
| #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
| #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ |
| #define PGTBL_ER 0x02024 |
| #define PRB0_BASE (0x2030-0x30) |
| #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ |
| #define PRB2_BASE (0x2050-0x30) /* gen3 */ |
| #define SRB0_BASE (0x2100-0x30) /* gen2 */ |
| #define SRB1_BASE (0x2110-0x30) /* gen2 */ |
| #define SRB2_BASE (0x2120-0x30) /* 830 */ |
| #define SRB3_BASE (0x2130-0x30) /* 830 */ |
| #define RENDER_RING_BASE 0x02000 |
| #define BSD_RING_BASE 0x04000 |
| #define GEN6_BSD_RING_BASE 0x12000 |
| 1029,6 → 1129,7 |
|---|
| #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) |
| #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) |
| #define GEN6_NOSYNC 0 |
| #define RING_PSMI_CTL(base) ((base)+0x50) |
| #define RING_MAX_IDLE(base) ((base)+0x54) |
| #define RING_HWS_PGA(base) ((base)+0x80) |
| #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
| 1064,6 → 1165,7 |
|---|
| #define RING_ACTHD_UDW(base) ((base)+0x5c) |
| #define RING_NOPID(base) ((base)+0x94) |
| #define RING_IMR(base) ((base)+0xa8) |
| #define RING_HWSTAM(base) ((base)+0x98) |
| #define RING_TIMESTAMP(base) ((base)+0x358) |
| #define TAIL_ADDR 0x001FFFF8 |
| #define HEAD_WRAP_COUNT 0xFFE00000 |
| 1194,7 → 1296,7 |
|---|
| #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) |
| #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) |
| #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) |
| #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) |
| #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) |
| #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
| |
| #define GFX_MODE 0x02520 |
| 1248,6 → 1350,10 |
|---|
| #define INSTPM_TLB_INVALIDATE (1<<9) |
| #define INSTPM_SYNC_FLUSH (1<<5) |
| #define ACTHD 0x020c8 |
| #define MEM_MODE 0x020cc |
| #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ |
| #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ |
| #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ |
| #define FW_BLC 0x020d8 |
| #define FW_BLC2 0x020dc |
| #define FW_BLC_SELF 0x020e0 /* 915+ only */ |
| 1354,6 → 1460,7 |
|---|
| #define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
| |
| #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 |
| #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) |
| #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) |
| #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) |
| |
| 1380,6 → 1487,7 |
|---|
| #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) |
| #define GT_BSD_USER_INTERRUPT (1 << 12) |
| #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
| #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
| #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
| #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) |
| #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) |
| 1519,6 → 1627,7 |
|---|
| /* Framebuffer compression for Ironlake */ |
| #define ILK_DPFC_CB_BASE 0x43200 |
| #define ILK_DPFC_CONTROL 0x43208 |
| #define FBC_CTL_FALSE_COLOR (1<<10) |
| /* The bit 28-8 is reserved */ |
| #define DPFC_RESERVED (0x1FFFFF00) |
| #define ILK_DPFC_RECOMP_CTL 0x4320c |
| 1675,12 → 1784,9 |
|---|
| #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) |
| #define DPLL_PORTD_READY_MASK (0xf) |
| #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) |
| #define PHY_COM_LANE_RESET_DEASSERT(phy, val) \ |
| ((phy == DPIO_PHY0) ? (val | 1) : (val | 2)) |
| #define PHY_COM_LANE_RESET_ASSERT(phy, val) \ |
| ((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2)) |
| #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) |
| #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) |
| #define PHY_POWERGOOD(phy) ((phy == DPIO_PHY0) ? (1<<31) : (1<<30)) |
| #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) |
| |
| /* |
| * The i830 generation, in LVDS mode, defines P1 as the bit number set within |
| 1953,6 → 2059,8 |
|---|
| #define DCC_ADDRESSING_MODE_MASK (3 << 0) |
| #define DCC_CHANNEL_XOR_DISABLE (1 << 10) |
| #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
| #define DCC2 0x10204 |
| #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) |
| |
| /* Pineview MCH register contains DDR3 setting */ |
| #define CSHRDDR3CTL 0x101a8 |
| 2236,7 → 2344,6 |
|---|
| |
| #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
| #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
| #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) |
| |
| #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) |
| #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) |
| 2397,6 → 2504,7 |
|---|
| #define _PIPEASRC 0x6001c |
| #define _BCLRPAT_A 0x60020 |
| #define _VSYNCSHIFT_A 0x60028 |
| #define _PIPE_MULT_A 0x6002c |
| |
| /* Pipe B timing regs */ |
| #define _HTOTAL_B 0x61000 |
| 2408,6 → 2516,7 |
|---|
| #define _PIPEBSRC 0x6101c |
| #define _BCLRPAT_B 0x61020 |
| #define _VSYNCSHIFT_B 0x61028 |
| #define _PIPE_MULT_B 0x6102c |
| |
| #define TRANSCODER_A_OFFSET 0x60000 |
| #define TRANSCODER_B_OFFSET 0x61000 |
| 2428,6 → 2537,7 |
|---|
| #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) |
| #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) |
| #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) |
| #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) |
| |
| /* HSW+ eDP PSR registers */ |
| #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) |
| 2457,9 → 2567,7 |
|---|
| |
| #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) |
| #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) |
| #define EDP_PSR_DPCD_COMMAND 0x80060000 |
| #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) |
| #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24) |
| #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) |
| #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) |
| #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) |
| 3476,6 → 3584,8 |
|---|
| #define DP_LINK_TRAIN_OFF (3 << 28) |
| #define DP_LINK_TRAIN_MASK (3 << 28) |
| #define DP_LINK_TRAIN_SHIFT 28 |
| #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) |
| #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) |
| |
| /* CPT Link training mode */ |
| #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) |
| 3594,6 → 3704,7 |
|---|
| #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) |
| #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) |
| #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 |
| #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) |
| |
| /* |
| * Computing GMCH M and N values for the Display Port link |
| 3732,7 → 3843,6 |
|---|
| #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
| #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
| #define PIPE_DPST_EVENT_STATUS (1UL<<7) |
| #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
| #define PIPE_A_PSR_STATUS_VLV (1UL<<6) |
| #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
| #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
| 3842,6 → 3952,7 |
|---|
| #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
| #define DSPARB_AEND_SHIFT 0 |
| |
| /* pnv/gen4/g4x/vlv/chv */ |
| #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) |
| #define DSPFW_SR_SHIFT 23 |
| #define DSPFW_SR_MASK (0x1ff<<23) |
| 3849,67 → 3960,145 |
|---|
| #define DSPFW_CURSORB_MASK (0x3f<<16) |
| #define DSPFW_PLANEB_SHIFT 8 |
| #define DSPFW_PLANEB_MASK (0x7f<<8) |
| #define DSPFW_PLANEA_MASK (0x7f) |
| #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ |
| #define DSPFW_PLANEA_SHIFT 0 |
| #define DSPFW_PLANEA_MASK (0x7f<<0) |
| #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ |
| #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) |
| #define DSPFW_CURSORA_MASK 0x00003f00 |
| #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ |
| #define DSPFW_FBC_SR_SHIFT 28 |
| #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ |
| #define DSPFW_FBC_HPLL_SR_SHIFT 24 |
| #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ |
| #define DSPFW_SPRITEB_SHIFT (16) |
| #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ |
| #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ |
| #define DSPFW_CURSORA_SHIFT 8 |
| #define DSPFW_PLANEC_MASK (0x7f) |
| #define DSPFW_CURSORA_MASK (0x3f<<8) |
| #define DSPFW_PLANEC_SHIFT_OLD 0 |
| #define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */ |
| #define DSPFW_SPRITEA_SHIFT 0 |
| #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ |
| #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ |
| #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) |
| #define DSPFW_HPLL_SR_EN (1<<31) |
| #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
| #define DSPFW_CURSOR_SR_SHIFT 24 |
| #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
| #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
| #define DSPFW_HPLL_CURSOR_SHIFT 16 |
| #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
| #define DSPFW_HPLL_SR_MASK (0x1ff) |
| #define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070) |
| #define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c) |
| #define DSPFW_HPLL_SR_SHIFT 0 |
| #define DSPFW_HPLL_SR_MASK (0x1ff<<0) |
| |
| /* vlv/chv */ |
| #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070) |
| #define DSPFW_SPRITEB_WM1_SHIFT 16 |
| #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) |
| #define DSPFW_CURSORA_WM1_SHIFT 8 |
| #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) |
| #define DSPFW_SPRITEA_WM1_SHIFT 0 |
| #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) |
| #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074) |
| #define DSPFW_PLANEB_WM1_SHIFT 24 |
| #define DSPFW_PLANEB_WM1_MASK (0xff<<24) |
| #define DSPFW_PLANEA_WM1_SHIFT 16 |
| #define DSPFW_PLANEA_WM1_MASK (0xff<<16) |
| #define DSPFW_CURSORB_WM1_SHIFT 8 |
| #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) |
| #define DSPFW_CURSOR_SR_WM1_SHIFT 0 |
| #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) |
| #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078) |
| #define DSPFW_SR_WM1_SHIFT 0 |
| #define DSPFW_SR_WM1_MASK (0x1ff<<0) |
| #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) |
| #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ |
| #define DSPFW_SPRITED_WM1_SHIFT 24 |
| #define DSPFW_SPRITED_WM1_MASK (0xff<<24) |
| #define DSPFW_SPRITED_SHIFT 16 |
| #define DSPFW_SPRITED_MASK (0xff<<16) |
| #define DSPFW_SPRITEC_WM1_SHIFT 8 |
| #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) |
| #define DSPFW_SPRITEC_SHIFT 0 |
| #define DSPFW_SPRITEC_MASK (0xff<<0) |
| #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) |
| #define DSPFW_SPRITEF_WM1_SHIFT 24 |
| #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) |
| #define DSPFW_SPRITEF_SHIFT 16 |
| #define DSPFW_SPRITEF_MASK (0xff<<16) |
| #define DSPFW_SPRITEE_WM1_SHIFT 8 |
| #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) |
| #define DSPFW_SPRITEE_SHIFT 0 |
| #define DSPFW_SPRITEE_MASK (0xff<<0) |
| #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
| #define DSPFW_PLANEC_WM1_SHIFT 24 |
| #define DSPFW_PLANEC_WM1_MASK (0xff<<24) |
| #define DSPFW_PLANEC_SHIFT 16 |
| #define DSPFW_PLANEC_MASK (0xff<<16) |
| #define DSPFW_CURSORC_WM1_SHIFT 8 |
| #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) |
| #define DSPFW_CURSORC_SHIFT 0 |
| #define DSPFW_CURSORC_MASK (0x3f<<0) |
| |
| /* vlv/chv high order bits */ |
| #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) |
| #define DSPFW_SR_HI_SHIFT 24 |
| #define DSPFW_SR_HI_MASK (1<<24) |
| #define DSPFW_SPRITEF_HI_SHIFT 23 |
| #define DSPFW_SPRITEF_HI_MASK (1<<23) |
| #define DSPFW_SPRITEE_HI_SHIFT 22 |
| #define DSPFW_SPRITEE_HI_MASK (1<<22) |
| #define DSPFW_PLANEC_HI_SHIFT 21 |
| #define DSPFW_PLANEC_HI_MASK (1<<21) |
| #define DSPFW_SPRITED_HI_SHIFT 20 |
| #define DSPFW_SPRITED_HI_MASK (1<<20) |
| #define DSPFW_SPRITEC_HI_SHIFT 16 |
| #define DSPFW_SPRITEC_HI_MASK (1<<16) |
| #define DSPFW_PLANEB_HI_SHIFT 12 |
| #define DSPFW_PLANEB_HI_MASK (1<<12) |
| #define DSPFW_SPRITEB_HI_SHIFT 8 |
| #define DSPFW_SPRITEB_HI_MASK (1<<8) |
| #define DSPFW_SPRITEA_HI_SHIFT 4 |
| #define DSPFW_SPRITEA_HI_MASK (1<<4) |
| #define DSPFW_PLANEA_HI_SHIFT 0 |
| #define DSPFW_PLANEA_HI_MASK (1<<0) |
| #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) |
| #define DSPFW_SR_WM1_HI_SHIFT 24 |
| #define DSPFW_SR_WM1_HI_MASK (1<<24) |
| #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
| #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) |
| #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 |
| #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) |
| #define DSPFW_PLANEC_WM1_HI_SHIFT 21 |
| #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) |
| #define DSPFW_SPRITED_WM1_HI_SHIFT 20 |
| #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) |
| #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 |
| #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) |
| #define DSPFW_PLANEB_WM1_HI_SHIFT 12 |
| #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) |
| #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 |
| #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) |
| #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 |
| #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) |
| #define DSPFW_PLANEA_WM1_HI_SHIFT 0 |
| #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) |
| |
| /* drain latency register values*/ |
| #define DRAIN_LATENCY_PRECISION_16 16 |
| #define DRAIN_LATENCY_PRECISION_32 32 |
| #define DRAIN_LATENCY_PRECISION_64 64 |
| #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) |
| #define DDL_CURSORA_PRECISION_64 (1<<31) |
| #define DDL_CURSORA_PRECISION_32 (0<<31) |
| #define DDL_CURSORA_SHIFT 24 |
| #define DDL_SPRITEB_PRECISION_64 (1<<23) |
| #define DDL_SPRITEB_PRECISION_32 (0<<23) |
| #define DDL_SPRITEB_SHIFT 16 |
| #define DDL_SPRITEA_PRECISION_64 (1<<15) |
| #define DDL_SPRITEA_PRECISION_32 (0<<15) |
| #define DDL_SPRITEA_SHIFT 8 |
| #define DDL_PLANEA_PRECISION_64 (1<<7) |
| #define DDL_PLANEA_PRECISION_32 (0<<7) |
| #define DDL_PLANEA_SHIFT 0 |
| #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
| #define DDL_CURSOR_PRECISION_HIGH (1<<31) |
| #define DDL_CURSOR_PRECISION_LOW (0<<31) |
| #define DDL_CURSOR_SHIFT 24 |
| #define DDL_SPRITE_PRECISION_HIGH(sprite) (1<<(15+8*(sprite))) |
| #define DDL_SPRITE_PRECISION_LOW(sprite) (0<<(15+8*(sprite))) |
| #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) |
| #define DDL_PLANE_PRECISION_HIGH (1<<7) |
| #define DDL_PLANE_PRECISION_LOW (0<<7) |
| #define DDL_PLANE_SHIFT 0 |
| #define DRAIN_LATENCY_MASK 0x7f |
| |
| #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) |
| #define DDL_CURSORB_PRECISION_64 (1<<31) |
| #define DDL_CURSORB_PRECISION_32 (0<<31) |
| #define DDL_CURSORB_SHIFT 24 |
| #define DDL_SPRITED_PRECISION_64 (1<<23) |
| #define DDL_SPRITED_PRECISION_32 (0<<23) |
| #define DDL_SPRITED_SHIFT 16 |
| #define DDL_SPRITEC_PRECISION_64 (1<<15) |
| #define DDL_SPRITEC_PRECISION_32 (0<<15) |
| #define DDL_SPRITEC_SHIFT 8 |
| #define DDL_PLANEB_PRECISION_64 (1<<7) |
| #define DDL_PLANEB_PRECISION_32 (0<<7) |
| #define DDL_PLANEB_SHIFT 0 |
| |
| #define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058) |
| #define DDL_CURSORC_PRECISION_64 (1<<31) |
| #define DDL_CURSORC_PRECISION_32 (0<<31) |
| #define DDL_CURSORC_SHIFT 24 |
| #define DDL_SPRITEF_PRECISION_64 (1<<23) |
| #define DDL_SPRITEF_PRECISION_32 (0<<23) |
| #define DDL_SPRITEF_SHIFT 16 |
| #define DDL_SPRITEE_PRECISION_64 (1<<15) |
| #define DDL_SPRITEE_PRECISION_32 (0<<15) |
| #define DDL_SPRITEE_SHIFT 8 |
| #define DDL_PLANEC_PRECISION_64 (1<<7) |
| #define DDL_PLANEC_PRECISION_32 (0<<7) |
| #define DDL_PLANEC_SHIFT 0 |
| |
| /* FIFO watermark sizes etc */ |
| #define G4X_FIFO_LINE_SIZE 64 |
| #define I915_FIFO_LINE_SIZE 64 |
| 3943,6 → 4132,41 |
|---|
| #define I965_CURSOR_MAX_WM 32 |
| #define I965_CURSOR_DFT_WM 8 |
| |
| /* Watermark register definitions for SKL */ |
| #define CUR_WM_A_0 0x70140 |
| #define CUR_WM_B_0 0x71140 |
| #define PLANE_WM_1_A_0 0x70240 |
| #define PLANE_WM_1_B_0 0x71240 |
| #define PLANE_WM_2_A_0 0x70340 |
| #define PLANE_WM_2_B_0 0x71340 |
| #define PLANE_WM_TRANS_1_A_0 0x70268 |
| #define PLANE_WM_TRANS_1_B_0 0x71268 |
| #define PLANE_WM_TRANS_2_A_0 0x70368 |
| #define PLANE_WM_TRANS_2_B_0 0x71368 |
| #define CUR_WM_TRANS_A_0 0x70168 |
| #define CUR_WM_TRANS_B_0 0x71168 |
| #define PLANE_WM_EN (1 << 31) |
| #define PLANE_WM_LINES_SHIFT 14 |
| #define PLANE_WM_LINES_MASK 0x1f |
| #define PLANE_WM_BLOCKS_MASK 0x3ff |
| |
| #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0) |
| #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level))) |
| #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0) |
| |
| #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0) |
| #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0) |
| #define _PLANE_WM_BASE(pipe, plane) \ |
| _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) |
| #define PLANE_WM(pipe, plane, level) \ |
| (_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) |
| #define _PLANE_WM_TRANS_1(pipe) \ |
| _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0) |
| #define _PLANE_WM_TRANS_2(pipe) \ |
| _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0) |
| #define PLANE_WM_TRANS(pipe, plane) \ |
| _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)) |
| |
| /* define the Watermark register on Ironlake */ |
| #define WM0_PIPEA_ILK 0x45100 |
| #define WM0_PIPE_PLANE_MASK (0xffff<<16) |
| 4026,7 → 4250,8 |
|---|
| /* Old style CUR*CNTR flags (desktop 8xx) */ |
| #define CURSOR_ENABLE 0x80000000 |
| #define CURSOR_GAMMA_ENABLE 0x40000000 |
| #define CURSOR_STRIDE_MASK 0x30000000 |
| #define CURSOR_STRIDE_SHIFT 28 |
| #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ |
| #define CURSOR_PIPE_CSC_ENABLE (1<<24) |
| #define CURSOR_FORMAT_SHIFT 24 |
| #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) |
| 4048,6 → 4273,7 |
|---|
| #define MCURSOR_PIPE_A 0x00 |
| #define MCURSOR_PIPE_B (1 << 28) |
| #define MCURSOR_GAMMA_ENABLE (1 << 26) |
| #define CURSOR_ROTATE_180 (1<<15) |
| #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) |
| #define _CURABASE 0x70084 |
| #define _CURAPOS 0x70088 |
| 4111,8 → 4337,11 |
|---|
| #define DISPPLANE_NO_LINE_DOUBLE 0 |
| #define DISPPLANE_STEREO_POLARITY_FIRST 0 |
| #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
| #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ |
| #define DISPPLANE_ROTATE_180 (1<<15) |
| #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
| #define DISPPLANE_TILED (1<<10) |
| #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ |
| #define _DSPAADDR 0x70184 |
| #define _DSPASTRIDE 0x70188 |
| #define _DSPAPOS 0x7018C /* reserved */ |
| 4133,6 → 4362,24 |
|---|
| #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) |
| #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) |
| |
| /* CHV pipe B blender and primary plane */ |
| #define _CHV_BLEND_A 0x60a00 |
| #define CHV_BLEND_LEGACY (0<<30) |
| #define CHV_BLEND_ANDROID (1<<30) |
| #define CHV_BLEND_MPO (2<<30) |
| #define CHV_BLEND_MASK (3<<30) |
| #define _CHV_CANVAS_A 0x60a04 |
| #define _PRIMPOS_A 0x60a08 |
| #define _PRIMSIZE_A 0x60a0c |
| #define _PRIMCNSTALPHA_A 0x60a10 |
| #define PRIM_CONST_ALPHA_ENABLE (1<<31) |
| |
| #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A) |
| #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A) |
| #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A) |
| #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A) |
| #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A) |
| |
| /* Display/Sprite base address macros */ |
| #define DISP_BASEADDR_MASK (0xfffff000) |
| #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) |
| 4195,6 → 4442,7 |
|---|
| #define DVS_YUV_ORDER_UYVY (1<<16) |
| #define DVS_YUV_ORDER_YVYU (2<<16) |
| #define DVS_YUV_ORDER_VYUY (3<<16) |
| #define DVS_ROTATE_180 (1<<15) |
| #define DVS_DEST_KEY (1<<2) |
| #define DVS_TRICKLE_FEED_DISABLE (1<<14) |
| #define DVS_TILED (1<<10) |
| 4265,6 → 4513,7 |
|---|
| #define SPRITE_YUV_ORDER_UYVY (1<<16) |
| #define SPRITE_YUV_ORDER_YVYU (2<<16) |
| #define SPRITE_YUV_ORDER_VYUY (3<<16) |
| #define SPRITE_ROTATE_180 (1<<15) |
| #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) |
| #define SPRITE_INT_GAMMA_ENABLE (1<<13) |
| #define SPRITE_TILED (1<<10) |
| 4332,6 → 4581,7 |
|---|
| #define SP_FORMAT_RGBA1010102 (9<<26) |
| #define SP_FORMAT_RGBX8888 (0xe<<26) |
| #define SP_FORMAT_RGBA8888 (0xf<<26) |
| #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ |
| #define SP_SOURCE_KEY (1<<22) |
| #define SP_YUV_BYTE_ORDER_MASK (3<<16) |
| #define SP_YUV_ORDER_YUYV (0<<16) |
| 4338,7 → 4588,9 |
|---|
| #define SP_YUV_ORDER_UYVY (1<<16) |
| #define SP_YUV_ORDER_YVYU (2<<16) |
| #define SP_YUV_ORDER_VYUY (3<<16) |
| #define SP_ROTATE_180 (1<<15) |
| #define SP_TILED (1<<10) |
| #define SP_MIRROR (1<<8) /* CHV pipe B */ |
| #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) |
| #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) |
| #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) |
| 4349,6 → 4601,7 |
|---|
| #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) |
| #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) |
| #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) |
| #define SP_CONST_ALPHA_ENABLE (1<<31) |
| #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) |
| |
| #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) |
| 4377,6 → 4630,195 |
|---|
| #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) |
| #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) |
| |
| /* |
| * CHV pipe B sprite CSC |
| * |
| * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| |
| * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| |
| * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| |
| */ |
| #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) |
| #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) |
| #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) |
| #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ |
| #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ |
| |
| #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) |
| #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) |
| #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) |
| #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) |
| #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) |
| #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ |
| #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ |
| |
| #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) |
| #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) |
| #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) |
| #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ |
| #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ |
| |
| #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) |
| #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) |
| #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) |
| #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ |
| #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ |
| |
| /* Skylake plane registers */ |
| |
| #define _PLANE_CTL_1_A 0x70180 |
| #define _PLANE_CTL_2_A 0x70280 |
| #define _PLANE_CTL_3_A 0x70380 |
| #define PLANE_CTL_ENABLE (1 << 31) |
| #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) |
| #define PLANE_CTL_FORMAT_MASK (0xf << 24) |
| #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) |
| #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) |
| #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) |
| #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) |
| #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) |
| #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) |
| #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) |
| #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) |
| #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) |
| #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) |
| #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) |
| #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) |
| #define PLANE_CTL_ORDER_BGRX (0 << 20) |
| #define PLANE_CTL_ORDER_RGBX (1 << 20) |
| #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) |
| #define PLANE_CTL_YUV422_YUYV ( 0 << 16) |
| #define PLANE_CTL_YUV422_UYVY ( 1 << 16) |
| #define PLANE_CTL_YUV422_YVYU ( 2 << 16) |
| #define PLANE_CTL_YUV422_VYUY ( 3 << 16) |
| #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) |
| #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) |
| #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) |
| #define PLANE_CTL_TILED_MASK (0x7 << 10) |
| #define PLANE_CTL_TILED_LINEAR ( 0 << 10) |
| #define PLANE_CTL_TILED_X ( 1 << 10) |
| #define PLANE_CTL_TILED_Y ( 4 << 10) |
| #define PLANE_CTL_TILED_YF ( 5 << 10) |
| #define PLANE_CTL_ALPHA_MASK (0x3 << 4) |
| #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) |
| #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) |
| #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) |
| #define PLANE_CTL_ROTATE_MASK 0x3 |
| #define PLANE_CTL_ROTATE_0 0x0 |
| #define PLANE_CTL_ROTATE_180 0x2 |
| #define _PLANE_STRIDE_1_A 0x70188 |
| #define _PLANE_STRIDE_2_A 0x70288 |
| #define _PLANE_STRIDE_3_A 0x70388 |
| #define _PLANE_POS_1_A 0x7018c |
| #define _PLANE_POS_2_A 0x7028c |
| #define _PLANE_POS_3_A 0x7038c |
| #define _PLANE_SIZE_1_A 0x70190 |
| #define _PLANE_SIZE_2_A 0x70290 |
| #define _PLANE_SIZE_3_A 0x70390 |
| #define _PLANE_SURF_1_A 0x7019c |
| #define _PLANE_SURF_2_A 0x7029c |
| #define _PLANE_SURF_3_A 0x7039c |
| #define _PLANE_OFFSET_1_A 0x701a4 |
| #define _PLANE_OFFSET_2_A 0x702a4 |
| #define _PLANE_OFFSET_3_A 0x703a4 |
| #define _PLANE_KEYVAL_1_A 0x70194 |
| #define _PLANE_KEYVAL_2_A 0x70294 |
| #define _PLANE_KEYMSK_1_A 0x70198 |
| #define _PLANE_KEYMSK_2_A 0x70298 |
| #define _PLANE_KEYMAX_1_A 0x701a0 |
| #define _PLANE_KEYMAX_2_A 0x702a0 |
| #define _PLANE_BUF_CFG_1_A 0x7027c |
| #define _PLANE_BUF_CFG_2_A 0x7037c |
| |
| #define _PLANE_CTL_1_B 0x71180 |
| #define _PLANE_CTL_2_B 0x71280 |
| #define _PLANE_CTL_3_B 0x71380 |
| #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) |
| #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) |
| #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) |
| #define PLANE_CTL(pipe, plane) \ |
| _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) |
| |
| #define _PLANE_STRIDE_1_B 0x71188 |
| #define _PLANE_STRIDE_2_B 0x71288 |
| #define _PLANE_STRIDE_3_B 0x71388 |
| #define _PLANE_STRIDE_1(pipe) \ |
| _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) |
| #define _PLANE_STRIDE_2(pipe) \ |
| _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) |
| #define _PLANE_STRIDE_3(pipe) \ |
| _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) |
| #define PLANE_STRIDE(pipe, plane) \ |
| _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) |
| |
| #define _PLANE_POS_1_B 0x7118c |
| #define _PLANE_POS_2_B 0x7128c |
| #define _PLANE_POS_3_B 0x7138c |
| #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) |
| #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) |
| #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) |
| #define PLANE_POS(pipe, plane) \ |
| _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) |
| |
| #define _PLANE_SIZE_1_B 0x71190 |
| #define _PLANE_SIZE_2_B 0x71290 |
| #define _PLANE_SIZE_3_B 0x71390 |
| #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) |
| #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) |
| #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) |
| #define PLANE_SIZE(pipe, plane) \ |
| _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) |
| |
| #define _PLANE_SURF_1_B 0x7119c |
| #define _PLANE_SURF_2_B 0x7129c |
| #define _PLANE_SURF_3_B 0x7139c |
| #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) |
| #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) |
| #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) |
| #define PLANE_SURF(pipe, plane) \ |
| _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) |
| |
| #define _PLANE_OFFSET_1_B 0x711a4 |
| #define _PLANE_OFFSET_2_B 0x712a4 |
| #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) |
| #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) |
| #define PLANE_OFFSET(pipe, plane) \ |
| _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) |
| |
| #define _PLANE_KEYVAL_1_B 0x71194 |
| #define _PLANE_KEYVAL_2_B 0x71294 |
| #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) |
| #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) |
| #define PLANE_KEYVAL(pipe, plane) \ |
| _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) |
| |
| #define _PLANE_KEYMSK_1_B 0x71198 |
| #define _PLANE_KEYMSK_2_B 0x71298 |
| #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) |
| #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) |
| #define PLANE_KEYMSK(pipe, plane) \ |
| _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) |
| |
| #define _PLANE_KEYMAX_1_B 0x711a0 |
| #define _PLANE_KEYMAX_2_B 0x712a0 |
| #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) |
| #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) |
| #define PLANE_KEYMAX(pipe, plane) \ |
| _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) |
| |
| #define _PLANE_BUF_CFG_1_B 0x7127c |
| #define _PLANE_BUF_CFG_2_B 0x7137c |
| #define _PLANE_BUF_CFG_1(pipe) \ |
| _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) |
| #define _PLANE_BUF_CFG_2(pipe) \ |
| _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) |
| #define PLANE_BUF_CFG(pipe, plane) \ |
| _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) |
| |
| /* SKL new cursor registers */ |
| #define _CUR_BUF_CFG_A 0x7017c |
| #define _CUR_BUF_CFG_B 0x7117c |
| #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) |
| |
| /* VBIOS regs */ |
| #define VGACNTRL 0x71400 |
| # define VGA_DISP_DISABLE (1 << 31) |
| 4492,6 → 4934,18 |
|---|
| #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) |
| #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) |
| |
| #define _PSA_CTL 0x68180 |
| #define _PSB_CTL 0x68980 |
| #define PS_ENABLE (1<<31) |
| #define _PSA_WIN_SZ 0x68174 |
| #define _PSB_WIN_SZ 0x68974 |
| #define _PSA_WIN_POS 0x68170 |
| #define _PSB_WIN_POS 0x68970 |
| |
| #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL) |
| #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) |
| #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) |
| |
| /* legacy palette */ |
| #define _LGC_PALETTE_A 0x4a000 |
| #define _LGC_PALETTE_B 0x4a800 |
| 4613,10 → 5067,23 |
|---|
| #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
| #define GEN8_PIPE_VSYNC (1 << 1) |
| #define GEN8_PIPE_VBLANK (1 << 0) |
| #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
| #define GEN9_PIPE_PLANE3_FAULT (1 << 9) |
| #define GEN9_PIPE_PLANE2_FAULT (1 << 8) |
| #define GEN9_PIPE_PLANE1_FAULT (1 << 7) |
| #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) |
| #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) |
| #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) |
| #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p)) |
| #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
| (GEN8_PIPE_CURSOR_FAULT | \ |
| GEN8_PIPE_SPRITE_FAULT | \ |
| GEN8_PIPE_PRIMARY_FAULT) |
| #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
| (GEN9_PIPE_CURSOR_FAULT | \ |
| GEN9_PIPE_PLANE3_FAULT | \ |
| GEN9_PIPE_PLANE2_FAULT | \ |
| GEN9_PIPE_PLANE1_FAULT) |
| |
| #define GEN8_DE_PORT_ISR 0x44440 |
| #define GEN8_DE_PORT_IMR 0x44444 |
| 4623,6 → 5090,9 |
|---|
| #define GEN8_DE_PORT_IIR 0x44448 |
| #define GEN8_DE_PORT_IER 0x4444c |
| #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) |
| #define GEN9_AUX_CHANNEL_D (1 << 27) |
| #define GEN9_AUX_CHANNEL_C (1 << 26) |
| #define GEN9_AUX_CHANNEL_B (1 << 25) |
| #define GEN8_AUX_CHANNEL_A (1 << 0) |
| |
| #define GEN8_DE_MISC_ISR 0x44460 |
| 4706,6 → 5176,8 |
|---|
| /* GEN8 chicken */ |
| #define HDC_CHICKEN0 0x7300 |
| #define HDC_FORCE_NON_COHERENT (1<<4) |
| #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
| #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) |
| |
| /* WaCatErrorRejectionIssue */ |
| #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 |
| 5246,8 → 5718,7 |
|---|
| #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) |
| #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) |
| #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) |
| #define PANEL_PORT_SELECT_DPB_VLV (1 << 30) |
| #define PANEL_PORT_SELECT_DPC_VLV (2 << 30) |
| #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) |
| #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) |
| #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) |
| |
| 5407,8 → 5878,13 |
|---|
| #define VLV_GTLC_ALLOWWAKEERR (1 << 1) |
| #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) |
| #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) |
| #define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
| #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
| #define FORCEWAKE_MEDIA_GEN9 0xa270 |
| #define FORCEWAKE_RENDER_GEN9 0xa278 |
| #define FORCEWAKE_BLITTER_GEN9 0xa188 |
| #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88 |
| #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84 |
| #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044 |
| #define FORCEWAKE_KERNEL 0x1 |
| #define FORCEWAKE_USER 0x2 |
| #define FORCEWAKE_MT_ACK 0x130040 |
| 5545,12 → 6021,6 |
|---|
| GEN6_PM_RP_DOWN_THRESHOLD | \ |
| GEN6_PM_RP_DOWN_TIMEOUT) |
| |
| #define CHV_CZ_CLOCK_FREQ_MODE_200 200 |
| #define CHV_CZ_CLOCK_FREQ_MODE_267 267 |
| #define CHV_CZ_CLOCK_FREQ_MODE_320 320 |
| #define CHV_CZ_CLOCK_FREQ_MODE_333 333 |
| #define CHV_CZ_CLOCK_FREQ_MODE_400 400 |
| |
| #define GEN7_GT_SCRATCH_BASE 0x4F100 |
| #define GEN7_GT_SCRATCH_REG_NUM 8 |
| |
| 5586,10 → 6056,18 |
|---|
| #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
| #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
| #define DISPLAY_IPS_CONTROL 0x19 |
| #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
| #define GEN6_PCODE_DATA 0x138128 |
| #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
| #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
| #define GEN6_PCODE_DATA1 0x13812C |
| |
| #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
| #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF |
| #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 |
| #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 |
| #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 |
| |
| #define GEN6_GT_CORE_STATUS 0x138060 |
| #define GEN6_CORE_CPD_STATE_MASK (7<<4) |
| #define GEN6_RCn_MASK 7 |
| 5626,6 → 6104,9 |
|---|
| #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
| #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
| |
| #define GEN9_HALF_SLICE_CHICKEN5 0xe188 |
| #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) |
| |
| #define GEN8_ROW_CHICKEN 0xe4f0 |
| #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) |
| #define STALL_DOP_GATING_DISABLE (1<<5) |
| 5641,6 → 6122,7 |
|---|
| #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) |
| #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
| |
| /* Audio */ |
| #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) |
| #define INTEL_AUDIO_DEVCL 0x808629FB |
| #define INTEL_AUDIO_DEVBLC 0x80862801 |
| 5649,49 → 6131,49 |
|---|
| #define G4X_AUD_CNTL_ST 0x620B4 |
| #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) |
| #define G4X_ELDV_DEVCTG (1 << 14) |
| #define G4X_ELD_ADDR (0xf << 5) |
| #define G4X_ELD_ADDR_MASK (0xf << 5) |
| #define G4X_ELD_ACK (1 << 4) |
| #define G4X_HDMIW_HDMIEDID 0x6210C |
| |
| #define IBX_HDMIW_HDMIEDID_A 0xE2050 |
| #define IBX_HDMIW_HDMIEDID_B 0xE2150 |
| #define _IBX_HDMIW_HDMIEDID_A 0xE2050 |
| #define _IBX_HDMIW_HDMIEDID_B 0xE2150 |
| #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
| IBX_HDMIW_HDMIEDID_A, \ |
| IBX_HDMIW_HDMIEDID_B) |
| #define IBX_AUD_CNTL_ST_A 0xE20B4 |
| #define IBX_AUD_CNTL_ST_B 0xE21B4 |
| _IBX_HDMIW_HDMIEDID_A, \ |
| _IBX_HDMIW_HDMIEDID_B) |
| #define _IBX_AUD_CNTL_ST_A 0xE20B4 |
| #define _IBX_AUD_CNTL_ST_B 0xE21B4 |
| #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
| IBX_AUD_CNTL_ST_A, \ |
| IBX_AUD_CNTL_ST_B) |
| #define IBX_ELD_BUFFER_SIZE (0x1f << 10) |
| #define IBX_ELD_ADDRESS (0x1f << 5) |
| _IBX_AUD_CNTL_ST_A, \ |
| _IBX_AUD_CNTL_ST_B) |
| #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) |
| #define IBX_ELD_ADDRESS_MASK (0x1f << 5) |
| #define IBX_ELD_ACK (1 << 4) |
| #define IBX_AUD_CNTL_ST2 0xE20C0 |
| #define IBX_ELD_VALIDB (1 << 0) |
| #define IBX_CP_READYB (1 << 1) |
| #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) |
| #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) |
| |
| #define CPT_HDMIW_HDMIEDID_A 0xE5050 |
| #define CPT_HDMIW_HDMIEDID_B 0xE5150 |
| #define _CPT_HDMIW_HDMIEDID_A 0xE5050 |
| #define _CPT_HDMIW_HDMIEDID_B 0xE5150 |
| #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
| CPT_HDMIW_HDMIEDID_A, \ |
| CPT_HDMIW_HDMIEDID_B) |
| #define CPT_AUD_CNTL_ST_A 0xE50B4 |
| #define CPT_AUD_CNTL_ST_B 0xE51B4 |
| _CPT_HDMIW_HDMIEDID_A, \ |
| _CPT_HDMIW_HDMIEDID_B) |
| #define _CPT_AUD_CNTL_ST_A 0xE50B4 |
| #define _CPT_AUD_CNTL_ST_B 0xE51B4 |
| #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
| CPT_AUD_CNTL_ST_A, \ |
| CPT_AUD_CNTL_ST_B) |
| _CPT_AUD_CNTL_ST_A, \ |
| _CPT_AUD_CNTL_ST_B) |
| #define CPT_AUD_CNTRL_ST2 0xE50C0 |
| |
| #define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
| #define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) |
| #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
| #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) |
| #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
| VLV_HDMIW_HDMIEDID_A, \ |
| VLV_HDMIW_HDMIEDID_B) |
| #define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) |
| #define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) |
| _VLV_HDMIW_HDMIEDID_A, \ |
| _VLV_HDMIW_HDMIEDID_B) |
| #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) |
| #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) |
| #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
| VLV_AUD_CNTL_ST_A, \ |
| VLV_AUD_CNTL_ST_B) |
| _VLV_AUD_CNTL_ST_A, \ |
| _VLV_AUD_CNTL_ST_B) |
| #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) |
| |
| /* These are the 4 32-bit write offset registers for each stream |
| 5700,28 → 6182,28 |
|---|
| */ |
| #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) |
| |
| #define IBX_AUD_CONFIG_A 0xe2000 |
| #define IBX_AUD_CONFIG_B 0xe2100 |
| #define _IBX_AUD_CONFIG_A 0xe2000 |
| #define _IBX_AUD_CONFIG_B 0xe2100 |
| #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ |
| IBX_AUD_CONFIG_A, \ |
| IBX_AUD_CONFIG_B) |
| #define CPT_AUD_CONFIG_A 0xe5000 |
| #define CPT_AUD_CONFIG_B 0xe5100 |
| _IBX_AUD_CONFIG_A, \ |
| _IBX_AUD_CONFIG_B) |
| #define _CPT_AUD_CONFIG_A 0xe5000 |
| #define _CPT_AUD_CONFIG_B 0xe5100 |
| #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ |
| CPT_AUD_CONFIG_A, \ |
| CPT_AUD_CONFIG_B) |
| #define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) |
| #define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) |
| _CPT_AUD_CONFIG_A, \ |
| _CPT_AUD_CONFIG_B) |
| #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) |
| #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) |
| #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ |
| VLV_AUD_CONFIG_A, \ |
| VLV_AUD_CONFIG_B) |
| _VLV_AUD_CONFIG_A, \ |
| _VLV_AUD_CONFIG_B) |
| |
| #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
| #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) |
| #define AUD_CONFIG_UPPER_N_SHIFT 20 |
| #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) |
| #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) |
| #define AUD_CONFIG_LOWER_N_SHIFT 4 |
| #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) |
| #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) |
| #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
| #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) |
| #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) |
| 5737,52 → 6219,44 |
|---|
| #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
| |
| /* HSW Audio */ |
| #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ |
| #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ |
| #define _HSW_AUD_CONFIG_A 0x65000 |
| #define _HSW_AUD_CONFIG_B 0x65100 |
| #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ |
| HSW_AUD_CONFIG_A, \ |
| HSW_AUD_CONFIG_B) |
| _HSW_AUD_CONFIG_A, \ |
| _HSW_AUD_CONFIG_B) |
| |
| #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ |
| #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ |
| #define _HSW_AUD_MISC_CTRL_A 0x65010 |
| #define _HSW_AUD_MISC_CTRL_B 0x65110 |
| #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ |
| HSW_AUD_MISC_CTRL_A, \ |
| HSW_AUD_MISC_CTRL_B) |
| _HSW_AUD_MISC_CTRL_A, \ |
| _HSW_AUD_MISC_CTRL_B) |
| |
| #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ |
| #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ |
| #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 |
| #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 |
| #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ |
| HSW_AUD_DIP_ELD_CTRL_ST_A, \ |
| HSW_AUD_DIP_ELD_CTRL_ST_B) |
| _HSW_AUD_DIP_ELD_CTRL_ST_A, \ |
| _HSW_AUD_DIP_ELD_CTRL_ST_B) |
| |
| /* Audio Digital Converter */ |
| #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ |
| #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ |
| #define _HSW_AUD_DIG_CNVT_1 0x65080 |
| #define _HSW_AUD_DIG_CNVT_2 0x65180 |
| #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ |
| HSW_AUD_DIG_CNVT_1, \ |
| HSW_AUD_DIG_CNVT_2) |
| _HSW_AUD_DIG_CNVT_1, \ |
| _HSW_AUD_DIG_CNVT_2) |
| #define DIP_PORT_SEL_MASK 0x3 |
| |
| #define HSW_AUD_EDID_DATA_A 0x65050 |
| #define HSW_AUD_EDID_DATA_B 0x65150 |
| #define _HSW_AUD_EDID_DATA_A 0x65050 |
| #define _HSW_AUD_EDID_DATA_B 0x65150 |
| #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ |
| HSW_AUD_EDID_DATA_A, \ |
| HSW_AUD_EDID_DATA_B) |
| _HSW_AUD_EDID_DATA_A, \ |
| _HSW_AUD_EDID_DATA_B) |
| |
| #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ |
| #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ |
| #define AUDIO_INACTIVE_C (1<<11) |
| #define AUDIO_INACTIVE_B (1<<7) |
| #define AUDIO_INACTIVE_A (1<<3) |
| #define AUDIO_OUTPUT_ENABLE_A (1<<2) |
| #define AUDIO_OUTPUT_ENABLE_B (1<<6) |
| #define AUDIO_OUTPUT_ENABLE_C (1<<10) |
| #define AUDIO_ELD_VALID_A (1<<0) |
| #define AUDIO_ELD_VALID_B (1<<4) |
| #define AUDIO_ELD_VALID_C (1<<8) |
| #define AUDIO_CP_READY_A (1<<1) |
| #define AUDIO_CP_READY_B (1<<5) |
| #define AUDIO_CP_READY_C (1<<9) |
| #define HSW_AUD_PIPE_CONV_CFG 0x6507c |
| #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 |
| #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) |
| #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) |
| #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) |
| #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) |
| |
| /* HSW Power Wells */ |
| #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ |
| 5866,15 → 6340,7 |
|---|
| #define DDI_BUF_CTL_B 0x64100 |
| #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
| #define DDI_BUF_CTL_ENABLE (1<<31) |
| #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
| #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
| #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
| #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ |
| #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ |
| #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ |
| #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
| #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
| #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
| #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) |
| #define DDI_BUF_EMP_MASK (0xf<<24) |
| #define DDI_BUF_PORT_REVERSAL (1<<16) |
| #define DDI_BUF_IS_IDLE (1<<7) |
| 6008,6 → 6474,83 |
|---|
| #define LCPLL_CD_SOURCE_FCLK (1<<21) |
| #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
| |
| /* |
| * SKL Clocks |
| */ |
| |
| /* CDCLK_CTL */ |
| #define CDCLK_CTL 0x46000 |
| #define CDCLK_FREQ_SEL_MASK (3<<26) |
| #define CDCLK_FREQ_450_432 (0<<26) |
| #define CDCLK_FREQ_540 (1<<26) |
| #define CDCLK_FREQ_337_308 (2<<26) |
| #define CDCLK_FREQ_675_617 (3<<26) |
| #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) |
| |
| /* LCPLL_CTL */ |
| #define LCPLL1_CTL 0x46010 |
| #define LCPLL2_CTL 0x46014 |
| #define LCPLL_PLL_ENABLE (1<<31) |
| |
| /* DPLL control1 */ |
| #define DPLL_CTRL1 0x6C058 |
| #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) |
| #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) |
| #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) |
| #define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1) |
| #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) |
| #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) |
| #define DPLL_CRTL1_LINK_RATE_2700 0 |
| #define DPLL_CRTL1_LINK_RATE_1350 1 |
| #define DPLL_CRTL1_LINK_RATE_810 2 |
| #define DPLL_CRTL1_LINK_RATE_1620 3 |
| #define DPLL_CRTL1_LINK_RATE_1080 4 |
| #define DPLL_CRTL1_LINK_RATE_2160 5 |
| |
| /* DPLL control2 */ |
| #define DPLL_CTRL2 0x6C05C |
| #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15)) |
| #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) |
| #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) |
| #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1)) |
| #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) |
| |
| /* DPLL Status */ |
| #define DPLL_STATUS 0x6C060 |
| #define DPLL_LOCK(id) (1<<((id)*8)) |
| |
| /* DPLL cfg */ |
| #define DPLL1_CFGCR1 0x6C040 |
| #define DPLL2_CFGCR1 0x6C048 |
| #define DPLL3_CFGCR1 0x6C050 |
| #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) |
| #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) |
| #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9) |
| #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) |
| |
| #define DPLL1_CFGCR2 0x6C044 |
| #define DPLL2_CFGCR2 0x6C04C |
| #define DPLL3_CFGCR2 0x6C054 |
| #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) |
| #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8) |
| #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7) |
| #define DPLL_CFGCR2_KDIV_MASK (3<<5) |
| #define DPLL_CFGCR2_KDIV(x) (x<<5) |
| #define DPLL_CFGCR2_KDIV_5 (0<<5) |
| #define DPLL_CFGCR2_KDIV_2 (1<<5) |
| #define DPLL_CFGCR2_KDIV_3 (2<<5) |
| #define DPLL_CFGCR2_KDIV_1 (3<<5) |
| #define DPLL_CFGCR2_PDIV_MASK (7<<2) |
| #define DPLL_CFGCR2_PDIV(x) (x<<2) |
| #define DPLL_CFGCR2_PDIV_1 (0<<2) |
| #define DPLL_CFGCR2_PDIV_2 (1<<2) |
| #define DPLL_CFGCR2_PDIV_3 (2<<2) |
| #define DPLL_CFGCR2_PDIV_7 (4<<2) |
| #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) |
| |
| #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) |
| #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) |
| |
| /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
| * since on HSW we can't write to it using I915_WRITE. */ |
| #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |