26,10 → 26,11 |
#define _I915_REG_H_ |
|
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
#define _PIPE_INC(pipe, base, inc) ((base) + (pipe)*(inc)) |
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
|
#define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ |
(pipe) == PIPE_B ? (b) : (c)) |
|
#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) |
#define _MASKED_BIT_DISABLE(a) ((a) << 16) |
73,11 → 74,11 |
#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) |
#define LBB 0xf4 |
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ |
|
|
/* Graphics reset regs */ |
#define I965_GDRST 0xc0 /* PCI config register */ |
#define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
#define GRDOM_FULL (0<<2) |
#define GRDOM_RENDER (1<<2) |
#define GRDOM_MEDIA (3<<2) |
84,6 → 85,13 |
#define GRDOM_MASK (3<<2) |
#define GRDOM_RESET_ENABLE (1<<0) |
|
#define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
#define ILK_GRDOM_FULL (0<<1) |
#define ILK_GRDOM_RENDER (1<<1) |
#define ILK_GRDOM_MEDIA (3<<1) |
#define ILK_GRDOM_MASK (3<<1) |
#define ILK_GRDOM_RESET_ENABLE (1<<0) |
|
#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
#define GEN6_MBC_SNPCR_SHIFT 21 |
#define GEN6_MBC_SNPCR_MASK (3<<21) |
92,6 → 100,9 |
#define GEN6_MBC_SNPCR_LOW (2<<21) |
#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ |
|
#define VLV_G3DCTL 0x9024 |
#define VLV_GSCKGCTL 0x9028 |
|
#define GEN6_MBCTL 0x0907c |
#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) |
175,9 → 186,23 |
#define VGA_CR_DATA_CGA 0x3d5 |
|
/* |
* Instruction field definitions used by the command parser |
*/ |
#define INSTR_CLIENT_SHIFT 29 |
#define INSTR_CLIENT_MASK 0xE0000000 |
#define INSTR_MI_CLIENT 0x0 |
#define INSTR_BC_CLIENT 0x2 |
#define INSTR_RC_CLIENT 0x3 |
#define INSTR_SUBCLIENT_SHIFT 27 |
#define INSTR_SUBCLIENT_MASK 0x18000000 |
#define INSTR_MEDIA_SUBCLIENT 0x2 |
|
/* |
* Memory interface instructions used by the kernel |
*/ |
#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) |
/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ |
#define MI_GLOBAL_GTT (1<<22) |
|
#define MI_NOOP MI_INSTR(0, 0) |
#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) |
215,7 → 240,7 |
#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) |
#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) |
#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) |
#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ |
#define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
#define MI_SEMAPHORE_UPDATE (1<<21) |
#define MI_SEMAPHORE_COMPARE (1<<20) |
233,6 → 258,7 |
#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ |
#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ |
#define MI_SEMAPHORE_SYNC_INVALID (3<<16) |
#define MI_SEMAPHORE_SYNC_MASK (3<<16) |
#define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
#define MI_MM_SPACE_GTT (1<<8) |
#define MI_MM_SPACE_PHYSICAL (0<<8) |
240,6 → 266,11 |
#define MI_RESTORE_EXT_STATE_EN (1<<2) |
#define MI_FORCE_RESTORE (1<<1) |
#define MI_RESTORE_INHIBIT (1<<0) |
#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ |
#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) |
#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ |
#define MI_SEMAPHORE_POLL (1<<15) |
#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) |
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
250,13 → 281,16 |
* - One can actually load arbitrary many arbitrary registers: Simply issue x |
* address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
*/ |
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) |
#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1) |
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) |
#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) |
#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) |
#define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
#define MI_FLUSH_DW_STORE_INDEX (1<<21) |
#define MI_INVALIDATE_TLB (1<<18) |
#define MI_FLUSH_DW_OP_STOREDW (1<<14) |
#define MI_FLUSH_DW_OP_MASK (3<<14) |
#define MI_FLUSH_DW_NOTIFY (1<<8) |
#define MI_INVALIDATE_BSD (1<<7) |
#define MI_FLUSH_DW_USE_GTT (1<<2) |
#define MI_FLUSH_DW_USE_PPGTT (0<<2) |
318,9 → 352,12 |
#define DISPLAY_PLANE_B (1<<20) |
#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ |
#define PIPE_CONTROL_MMIO_WRITE (1<<23) |
#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
#define PIPE_CONTROL_CS_STALL (1<<20) |
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
#define PIPE_CONTROL_QW_WRITE (1<<14) |
#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) |
#define PIPE_CONTROL_DEPTH_STALL (1<<13) |
#define PIPE_CONTROL_WRITE_FLUSH (1<<12) |
#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
328,6 → 365,7 |
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ |
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) |
#define PIPE_CONTROL_NOTIFY (1<<8) |
#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ |
#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) |
#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) |
335,8 → 373,96 |
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ |
|
/* |
* Commands used only by the command parser |
*/ |
#define MI_SET_PREDICATE MI_INSTR(0x01, 0) |
#define MI_ARB_CHECK MI_INSTR(0x05, 0) |
#define MI_RS_CONTROL MI_INSTR(0x06, 0) |
#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) |
#define MI_PREDICATE MI_INSTR(0x0C, 0) |
#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) |
#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) |
#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) |
#define MI_URB_CLEAR MI_INSTR(0x19, 0) |
#define MI_UPDATE_GTT MI_INSTR(0x23, 0) |
#define MI_CLFLUSH MI_INSTR(0x27, 0) |
#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) |
#define MI_REPORT_PERF_COUNT_GGTT (1<<0) |
#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) |
#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) |
#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) |
#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) |
#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) |
#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) |
|
#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) |
#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) |
#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) |
#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) |
#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ |
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) |
#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ |
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) |
#define GFX_OP_3DSTATE_SO_DECL_LIST \ |
((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) |
|
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ |
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) |
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ |
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) |
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ |
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) |
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ |
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) |
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ |
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) |
|
#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) |
|
#define COLOR_BLT ((0x2<<29)|(0x40<<22)) |
#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) |
|
/* |
* Registers used only by the command parser |
*/ |
#define BCS_SWCTRL 0x22200 |
|
#define HS_INVOCATION_COUNT 0x2300 |
#define DS_INVOCATION_COUNT 0x2308 |
#define IA_VERTICES_COUNT 0x2310 |
#define IA_PRIMITIVES_COUNT 0x2318 |
#define VS_INVOCATION_COUNT 0x2320 |
#define GS_INVOCATION_COUNT 0x2328 |
#define GS_PRIMITIVES_COUNT 0x2330 |
#define CL_INVOCATION_COUNT 0x2338 |
#define CL_PRIMITIVES_COUNT 0x2340 |
#define PS_INVOCATION_COUNT 0x2348 |
#define PS_DEPTH_COUNT 0x2350 |
|
/* There are the 4 64-bit counter registers, one for each stream output */ |
#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) |
|
#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) |
|
#define GEN7_3DPRIM_END_OFFSET 0x2420 |
#define GEN7_3DPRIM_START_VERTEX 0x2430 |
#define GEN7_3DPRIM_VERTEX_COUNT 0x2434 |
#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 |
#define GEN7_3DPRIM_START_INSTANCE 0x243C |
#define GEN7_3DPRIM_BASE_VERTEX 0x2440 |
|
#define OACONTROL 0x2360 |
|
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068 |
#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ |
_GEN7_PIPEA_DE_LOAD_SL, \ |
_GEN7_PIPEB_DE_LOAD_SL) |
|
/* |
* Reset registers |
*/ |
#define DEBUG_RESET_I830 0x6070 |
358,6 → 484,7 |
#define IOSF_PORT_PUNIT 0x4 |
#define IOSF_PORT_NC 0x11 |
#define IOSF_PORT_DPIO 0x12 |
#define IOSF_PORT_DPIO_2 0x1a |
#define IOSF_PORT_GPIO_NC 0x13 |
#define IOSF_PORT_CCK 0x14 |
#define IOSF_PORT_CCU 0xA9 |
369,22 → 496,35 |
/* See configdb bunit SB addr map */ |
#define BUNIT_REG_BISOC 0x11 |
|
#define PUNIT_OPCODE_REG_READ 6 |
#define PUNIT_OPCODE_REG_WRITE 7 |
|
#define PUNIT_REG_DSPFREQ 0x36 |
#define DSPFREQSTAT_SHIFT 30 |
#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) |
#define DSPFREQGUAR_SHIFT 14 |
#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) |
|
/* See the PUNIT HAS v0.8 for the below bits */ |
enum punit_power_well { |
PUNIT_POWER_WELL_RENDER = 0, |
PUNIT_POWER_WELL_MEDIA = 1, |
PUNIT_POWER_WELL_DISP2D = 3, |
PUNIT_POWER_WELL_DPIO_CMN_BC = 5, |
PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, |
PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, |
PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, |
PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, |
PUNIT_POWER_WELL_DPIO_RX0 = 10, |
PUNIT_POWER_WELL_DPIO_RX1 = 11, |
|
PUNIT_POWER_WELL_NUM, |
}; |
|
#define PUNIT_REG_PWRGT_CTRL 0x60 |
#define PUNIT_REG_PWRGT_STATUS 0x61 |
#define PUNIT_CLK_GATE 1 |
#define PUNIT_PWR_RESET 2 |
#define PUNIT_PWR_GATE 3 |
#define RENDER_PWRGT (PUNIT_PWR_GATE << 0) |
#define MEDIA_PWRGT (PUNIT_PWR_GATE << 2) |
#define DISP2D_PWRGT (PUNIT_PWR_GATE << 6) |
#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) |
#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) |
#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) |
#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) |
#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) |
|
#define PUNIT_REG_GPU_LFM 0xd3 |
#define PUNIT_REG_GPU_FREQ_REQ 0xd4 |
391,10 → 531,21 |
#define PUNIT_REG_GPU_FREQ_STS 0xd8 |
#define GENFREQSTATUS (1<<0) |
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc |
#define PUNIT_REG_CZ_TIMESTAMP 0xce |
|
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ |
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ |
|
#define PUNIT_GPU_STATUS_REG 0xdb |
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 |
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff |
#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 |
#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff |
|
#define PUNIT_GPU_DUTYCYCLE_REG 0xdf |
#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 |
#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff |
|
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c |
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 |
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 |
406,6 → 557,11 |
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 |
#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 |
|
#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 |
#define VLV_RP_UP_EI_THRESHOLD 90 |
#define VLV_RP_DOWN_EI_THRESHOLD 70 |
#define VLV_INT_COUNT_FOR_DOWN_EI 5 |
|
/* vlv2 north clock has */ |
#define CCK_FUSE_REG 0x8 |
#define CCK_FUSE_HPLL_FREQ_MASK 0x3 |
440,17 → 596,97 |
#define DSI_PLL_M1_DIV_SHIFT 0 |
#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) |
#define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
#define DISPLAY_TRUNK_FORCE_ON (1 << 17) |
#define DISPLAY_TRUNK_FORCE_OFF (1 << 16) |
#define DISPLAY_FREQUENCY_STATUS (0x1f << 8) |
#define DISPLAY_FREQUENCY_STATUS_SHIFT 8 |
#define DISPLAY_FREQUENCY_VALUES (0x1f << 0) |
|
/* |
* DPIO - a special bus for various display related registers to hide behind |
/** |
* DOC: DPIO |
* |
* DPIO is VLV only. |
* VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI |
* ports. DPIO is the name given to such a display PHY. These PHYs |
* don't follow the standard programming model using direct MMIO |
* registers, and instead their registers must be accessed trough IOSF |
* sideband. VLV has one such PHY for driving ports B and C, and CHV |
* adds another PHY for driving port D. Each PHY responds to specific |
* IOSF-SB port. |
* |
* Note: digital port B is DDI0, digital pot C is DDI1 |
* Each display PHY is made up of one or two channels. Each channel |
* houses a common lane part which contains the PLL and other common |
* logic. CH0 common lane also contains the IOSF-SB logic for the |
* Common Register Interface (CRI) ie. the DPIO registers. CRI clock |
* must be running when any DPIO registers are accessed. |
* |
* In addition to having their own registers, the PHYs are also |
* controlled through some dedicated signals from the display |
* controller. These include PLL reference clock enable, PLL enable, |
* and CRI clock selection, for example. |
* |
* Eeach channel also has two splines (also called data lanes), and |
* each spline is made up of one Physical Access Coding Sub-Layer |
* (PCS) block and two TX lanes. So each channel has two PCS blocks |
* and four TX lanes. The TX lanes are used as DP lanes or TMDS |
* data/clock pairs depending on the output type. |
* |
* Additionally the PHY also contains an AUX lane with AUX blocks |
* for each channel. This is used for DP AUX communication, but |
* this fact isn't really relevant for the driver since AUX is |
* controlled from the display controller side. No DPIO registers |
* need to be accessed during AUX communication, |
* |
* Generally the common lane corresponds to the pipe and |
* the spline (PCS/TX) correponds to the port. |
* |
* For dual channel PHY (VLV/CHV): |
* |
* pipe A == CMN/PLL/REF CH0 |
* |
* pipe B == CMN/PLL/REF CH1 |
* |
* port B == PCS/TX CH0 |
* |
* port C == PCS/TX CH1 |
* |
* This is especially important when we cross the streams |
* ie. drive port B with pipe B, or port C with pipe A. |
* |
* For single channel PHY (CHV): |
* |
* pipe C == CMN/PLL/REF CH0 |
* |
* port D == PCS/TX CH0 |
* |
* Note: digital port B is DDI0, digital port C is DDI1, |
* digital port D is DDI2 |
*/ |
/* |
* Dual channel PHY (VLV/CHV) |
* --------------------------------- |
* | CH0 | CH1 | |
* | CMN/PLL/REF | CMN/PLL/REF | |
* |---------------|---------------| Display PHY |
* | PCS01 | PCS23 | PCS01 | PCS23 | |
* |-------|-------|-------|-------| |
* |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| |
* --------------------------------- |
* | DDI0 | DDI1 | DP/HDMI ports |
* --------------------------------- |
* |
* Single channel PHY (CHV) |
* ----------------- |
* | CH0 | |
* | CMN/PLL/REF | |
* |---------------| Display PHY |
* | PCS01 | PCS23 | |
* |-------|-------| |
* |TX0|TX1|TX2|TX3| |
* ----------------- |
* | DDI2 | DP/HDMI port |
* ----------------- |
*/ |
#define DPIO_DEVFN 0 |
#define DPIO_OPCODE_REG_WRITE 1 |
#define DPIO_OPCODE_REG_READ 0 |
|
#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) |
#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
527,8 → 763,16 |
#define DPIO_PCS_TX_LANE1_RESET (1<<7) |
#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
|
#define _VLV_PCS01_DW0_CH0 0x200 |
#define _VLV_PCS23_DW0_CH0 0x400 |
#define _VLV_PCS01_DW0_CH1 0x2600 |
#define _VLV_PCS23_DW0_CH1 0x2800 |
#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) |
#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) |
|
#define _VLV_PCS_DW1_CH0 0x8204 |
#define _VLV_PCS_DW1_CH1 0x8404 |
#define CHV_PCS_REQ_SOFTRESET_EN (1<<23) |
#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) |
#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) |
#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
535,8 → 779,17 |
#define DPIO_PCS_CLK_SOFT_RESET (1<<5) |
#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
|
#define _VLV_PCS01_DW1_CH0 0x204 |
#define _VLV_PCS23_DW1_CH0 0x404 |
#define _VLV_PCS01_DW1_CH1 0x2604 |
#define _VLV_PCS23_DW1_CH1 0x2804 |
#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) |
#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) |
|
#define _VLV_PCS_DW8_CH0 0x8220 |
#define _VLV_PCS_DW8_CH1 0x8420 |
#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) |
#define CHV_PCS_USEDCLKCHANNEL (1 << 21) |
#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
|
#define _VLV_PCS01_DW8_CH0 0x0220 |
550,6 → 803,19 |
#define _VLV_PCS_DW9_CH1 0x8424 |
#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
|
#define _CHV_PCS_DW10_CH0 0x8228 |
#define _CHV_PCS_DW10_CH1 0x8428 |
#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) |
#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) |
#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
|
#define _VLV_PCS01_DW10_CH0 0x0228 |
#define _VLV_PCS23_DW10_CH0 0x0428 |
#define _VLV_PCS01_DW10_CH1 0x2628 |
#define _VLV_PCS23_DW10_CH1 0x2828 |
#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) |
#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) |
|
#define _VLV_PCS_DW11_CH0 0x822c |
#define _VLV_PCS_DW11_CH1 0x842c |
#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
568,14 → 834,21 |
|
#define _VLV_TX_DW2_CH0 0x8288 |
#define _VLV_TX_DW2_CH1 0x8488 |
#define DPIO_SWING_MARGIN_SHIFT 16 |
#define DPIO_SWING_MARGIN_MASK (0xff << DPIO_SWING_MARGIN_SHIFT) |
#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
|
#define _VLV_TX_DW3_CH0 0x828c |
#define _VLV_TX_DW3_CH1 0x848c |
/* The following bit for CHV phy */ |
#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) |
#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
|
#define _VLV_TX_DW4_CH0 0x8290 |
#define _VLV_TX_DW4_CH1 0x8490 |
#define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) |
#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
|
#define _VLV_TX3_DW4_CH0 0x690 |
595,6 → 868,96 |
#define _VLV_TX_DW14_CH1 0x84b8 |
#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) |
|
/* CHV dpPhy registers */ |
#define _CHV_PLL_DW0_CH0 0x8000 |
#define _CHV_PLL_DW0_CH1 0x8180 |
#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) |
|
#define _CHV_PLL_DW1_CH0 0x8004 |
#define _CHV_PLL_DW1_CH1 0x8184 |
#define DPIO_CHV_N_DIV_SHIFT 8 |
#define DPIO_CHV_M1_DIV_BY_2 (0 << 0) |
#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) |
|
#define _CHV_PLL_DW2_CH0 0x8008 |
#define _CHV_PLL_DW2_CH1 0x8188 |
#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) |
|
#define _CHV_PLL_DW3_CH0 0x800c |
#define _CHV_PLL_DW3_CH1 0x818c |
#define DPIO_CHV_FRAC_DIV_EN (1 << 16) |
#define DPIO_CHV_FIRST_MOD (0 << 8) |
#define DPIO_CHV_SECOND_MOD (1 << 8) |
#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 |
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
|
#define _CHV_PLL_DW6_CH0 0x8018 |
#define _CHV_PLL_DW6_CH1 0x8198 |
#define DPIO_CHV_GAIN_CTRL_SHIFT 16 |
#define DPIO_CHV_INT_COEFF_SHIFT 8 |
#define DPIO_CHV_PROP_COEFF_SHIFT 0 |
#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) |
|
#define _CHV_CMN_DW5_CH0 0x8114 |
#define CHV_BUFRIGHTENA1_DISABLE (0 << 20) |
#define CHV_BUFRIGHTENA1_NORMAL (1 << 20) |
#define CHV_BUFRIGHTENA1_FORCE (3 << 20) |
#define CHV_BUFRIGHTENA1_MASK (3 << 20) |
#define CHV_BUFLEFTENA1_DISABLE (0 << 22) |
#define CHV_BUFLEFTENA1_NORMAL (1 << 22) |
#define CHV_BUFLEFTENA1_FORCE (3 << 22) |
#define CHV_BUFLEFTENA1_MASK (3 << 22) |
|
#define _CHV_CMN_DW13_CH0 0x8134 |
#define _CHV_CMN_DW0_CH1 0x8080 |
#define DPIO_CHV_S1_DIV_SHIFT 21 |
#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ |
#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ |
#define DPIO_CHV_K_DIV_SHIFT 4 |
#define DPIO_PLL_FREQLOCK (1 << 1) |
#define DPIO_PLL_LOCK (1 << 0) |
#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) |
|
#define _CHV_CMN_DW14_CH0 0x8138 |
#define _CHV_CMN_DW1_CH1 0x8084 |
#define DPIO_AFC_RECAL (1 << 14) |
#define DPIO_DCLKP_EN (1 << 13) |
#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ |
#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ |
#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ |
#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ |
#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ |
#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ |
#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ |
#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ |
#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
|
#define _CHV_CMN_DW19_CH0 0x814c |
#define _CHV_CMN_DW6_CH1 0x8098 |
#define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
|
#define CHV_CMN_DW30 0x8178 |
#define DPIO_LRC_BYPASS (1 << 3) |
|
#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ |
(lane) * 0x200 + (offset)) |
|
#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) |
#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) |
#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) |
#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) |
#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) |
#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) |
#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) |
#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) |
#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) |
#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) |
#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) |
#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
#define DPIO_FRC_LATENCY_SHFIT 8 |
#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) |
#define DPIO_UPAR_SHIFT 30 |
/* |
* Fence registers |
*/ |
622,6 → 985,7 |
#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
|
|
/* control register for cpu gtt access */ |
#define TILECTL 0x101000 |
#define TILECTL_SWZCTL (1 << 0) |
631,10 → 995,14 |
/* |
* Instruction and interrupt control regs |
*/ |
#define PGTBL_CTL 0x02020 |
#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ |
#define PGTBL_ER 0x02024 |
#define RENDER_RING_BASE 0x02000 |
#define BSD_RING_BASE 0x04000 |
#define GEN6_BSD_RING_BASE 0x12000 |
#define GEN8_BSD2_RING_BASE 0x1c000 |
#define VEBOX_RING_BASE 0x1a000 |
#define BLT_RING_BASE 0x22000 |
#define RING_TAIL(base) ((base)+0x30) |
660,9 → 1028,20 |
#define RING_MAX_IDLE(base) ((base)+0x54) |
#define RING_HWS_PGA(base) ((base)+0x80) |
#define RING_HWS_PGA_GEN6(base) ((base)+0x2080) |
#define ARB_MODE 0x04030 |
|
#define GEN7_WR_WATERMARK 0x4028 |
#define GEN7_GFX_PRIO_CTRL 0x402C |
#define ARB_MODE 0x4030 |
#define ARB_MODE_SWIZZLE_SNB (1<<4) |
#define ARB_MODE_SWIZZLE_IVB (1<<5) |
#define GEN7_GFX_PEND_TLB0 0x4034 |
#define GEN7_GFX_PEND_TLB1 0x4038 |
/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
#define GEN7_LRA_LIMITS_BASE 0x403C |
#define GEN7_LRA_LIMITS_REG_NUM 13 |
#define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 |
#define GEN7_GFX_MAX_REQ_COUNT 0x4074 |
|
#define GAMTARBMODE 0x04a08 |
#define ARB_MODE_BWGTLB_DISABLE (1<<9) |
#define ARB_MODE_SWIZZLE_BDW (1<<1) |
678,6 → 1057,7 |
#define BLT_HWS_PGA_GEN7 (0x04280) |
#define VEBOX_HWS_PGA_GEN7 (0x04380) |
#define RING_ACTHD(base) ((base)+0x74) |
#define RING_ACTHD_UDW(base) ((base)+0x5c) |
#define RING_NOPID(base) ((base)+0x94) |
#define RING_IMR(base) ((base)+0xa8) |
#define RING_TIMESTAMP(base) ((base)+0x358) |
696,6 → 1076,9 |
#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ |
#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
|
#define GEN7_TLB_RD_ADDR 0x4700 |
|
#if 0 |
#define PRB0_TAIL 0x02030 |
#define PRB0_HEAD 0x02034 |
719,7 → 1102,9 |
#define RING_INSTDONE(base) ((base)+0x6c) |
#define RING_INSTPS(base) ((base)+0x70) |
#define RING_DMA_FADD(base) ((base)+0x78) |
#define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ |
#define RING_INSTPM(base) ((base)+0xc0) |
#define RING_MI_MODE(base) ((base)+0x9c) |
#define INSTPS 0x02070 /* 965+ only */ |
#define INSTDONE1 0x0207c /* 965+ only */ |
#define ACTHD_I965 0x02074 |
789,15 → 1174,23 |
#define _3D_CHICKEN3 0x02090 |
#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) |
#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ |
#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ |
|
#define MI_MODE 0x0209c |
# define VS_TIMER_DISPATCH (1 << 6) |
# define MI_FLUSH_ENABLE (1 << 12) |
# define ASYNC_FLIP_PERF_DISABLE (1 << 14) |
# define MODE_IDLE (1 << 9) |
# define STOP_RING (1 << 8) |
|
#define GEN6_GT_MODE 0x20d0 |
#define GEN6_GT_MODE_HI (1 << 9) |
#define GEN7_GT_MODE 0x7008 |
#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) |
#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) |
#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) |
#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) |
#define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) |
#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
|
#define GFX_MODE 0x02520 |
804,7 → 1197,7 |
#define GFX_MODE_GEN7 0x0229c |
#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
#define GFX_RUN_LIST_ENABLE (1<<15) |
#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) |
#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) |
#define GFX_SURFACE_FAULT_ENABLE (1<<12) |
#define GFX_REPLAY_MODE (1<<11) |
#define GFX_PSMI_GRANULARITY (1<<10) |
811,7 → 1204,10 |
#define GFX_PPGTT_ENABLE (1<<9) |
|
#define VLV_DISPLAY_BASE 0x180000 |
#define VLV_MIPI_BASE VLV_DISPLAY_BASE |
|
#define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) |
#define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) |
#define SCPD0 0x0209c /* 915+ only */ |
#define IER 0x020a0 |
#define IIR 0x020a4 |
818,7 → 1214,9 |
#define IMR 0x020a8 |
#define ISR 0x020ac |
#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) |
#define GINT_DIS (1<<22) |
#define GCFG_DIS (1<<8) |
#define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) |
#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) |
#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) |
#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) |
825,6 → 1223,8 |
#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) |
#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) |
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) |
#define VLV_PCBR_ADDR_SHIFT 12 |
|
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ |
#define EIR 0x020b0 |
#define EMR 0x020b4 |
837,7 → 1237,7 |
#define I915_ERROR_INSTRUCTION (1<<0) |
#define INSTPM 0x020c0 |
#define INSTPM_SELF_EN (1<<12) /* 915GM only */ |
#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts |
#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts |
will not assert AGPBUSY# and will only |
be delivered when out of C3. */ |
#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
918,6 → 1318,10 |
#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ |
#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
|
#define MI_STATE 0x020e4 /* gen2 only */ |
#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ |
#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ |
|
#define CACHE_MODE_0 0x02120 /* 915+ only */ |
#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) |
#define CM0_IZ_OPT_DISABLE (1<<6) |
934,13 → 1338,21 |
#define ECO_GATING_CX_ONLY (1<<3) |
#define ECO_FLIP_DONE (1<<0) |
|
#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ |
#define RC_OP_FLUSH_ENABLE (1<<0) |
#define HIZ_RAW_STALL_OPT_DISABLE (1<<2) |
#define CACHE_MODE_1 0x7004 /* IVB+ */ |
#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) |
|
#define GEN6_BLITTER_ECOSKPD 0x221d0 |
#define GEN6_BLITTER_LOCK_SHIFT 16 |
#define GEN6_BLITTER_FBC_NOTIFY (1<<3) |
|
#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 |
#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) |
#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) |
|
#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) |
980,21 → 1392,40 |
|
/* These are all the "old" interrupts */ |
#define ILK_BSD_USER_INTERRUPT (1<<5) |
|
#define I915_PM_INTERRUPT (1<<31) |
#define I915_ISP_INTERRUPT (1<<22) |
#define I915_LPE_PIPE_B_INTERRUPT (1<<21) |
#define I915_LPE_PIPE_A_INTERRUPT (1<<20) |
#define I915_MIPIB_INTERRUPT (1<<19) |
#define I915_MIPIA_INTERRUPT (1<<18) |
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
#define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) |
#define I915_MASTER_ERROR_INTERRUPT (1<<15) |
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) |
#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) |
#define I915_HWB_OOM_INTERRUPT (1<<13) |
#define I915_LPE_PIPE_C_INTERRUPT (1<<12) |
#define I915_SYNC_STATUS_INTERRUPT (1<<12) |
#define I915_MISC_INTERRUPT (1<<11) |
#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) |
#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) |
#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) |
#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) |
#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) |
#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) |
#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) |
#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) |
#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) |
#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) |
#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) |
#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) |
#define I915_DEBUG_INTERRUPT (1<<2) |
#define I915_WINVALID_INTERRUPT (1<<1) |
#define I915_USER_INTERRUPT (1<<1) |
#define I915_ASLE_INTERRUPT (1<<0) |
#define I915_BSD_USER_INTERRUPT (1 << 25) |
1046,9 → 1477,8 |
#define FBC_CTL_IDLE_LINE (2<<2) |
#define FBC_CTL_IDLE_DEBUG (3<<2) |
#define FBC_CTL_CPU_FENCE (1<<1) |
#define FBC_CTL_PLANEA (0<<0) |
#define FBC_CTL_PLANEB (1<<0) |
#define FBC_FENCE_OFF 0x0321b |
#define FBC_CTL_PLANE(plane) ((plane)<<0) |
#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ |
#define FBC_TAG 0x03300 |
|
#define FBC_LL_SIZE (1536) |
1057,9 → 1487,8 |
#define DPFC_CB_BASE 0x3200 |
#define DPFC_CONTROL 0x3208 |
#define DPFC_CTL_EN (1<<31) |
#define DPFC_CTL_PLANEA (0<<30) |
#define DPFC_CTL_PLANEB (1<<30) |
#define IVB_DPFC_CTL_PLANE_SHIFT (29) |
#define DPFC_CTL_PLANE(plane) ((plane)<<30) |
#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) |
#define DPFC_CTL_FENCE_EN (1<<29) |
#define IVB_DPFC_CTL_FENCE_EN (1<<28) |
#define DPFC_CTL_PERSISTENT_MODE (1<<25) |
1120,13 → 1549,6 |
#define FBC_REND_NUKE (1<<2) |
#define FBC_REND_CACHE_CLEAN (1<<1) |
|
#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 |
#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 |
#define HSW_BYPASS_FBC_QUEUE (1<<22) |
#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ |
_HSW_PIPE_SLICE_CHICKEN_1_A, + \ |
_HSW_PIPE_SLICE_CHICKEN_1_B) |
|
/* |
* GPIO regs |
*/ |
1163,6 → 1585,7 |
#define GMBUS_PORT_SSC 1 |
#define GMBUS_PORT_VGADDC 2 |
#define GMBUS_PORT_PANEL 3 |
#define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ |
#define GMBUS_PORT_DPC 4 /* HDMIC */ |
#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
#define GMBUS_PORT_DPD 6 /* HDMID */ |
1202,6 → 1625,10 |
/* |
* Clock control & power management |
*/ |
#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) |
#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) |
#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) |
#define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) |
|
#define VGA0 0x6000 |
#define VGA1 0x6004 |
1214,9 → 1641,6 |
#define VGA1_PD_P1_DIV_2 (1 << 13) |
#define VGA1_PD_P1_SHIFT 8 |
#define VGA1_PD_P1_MASK (0x1f << 8) |
#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014) |
#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018) |
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) |
#define DPLL_VCO_ENABLE (1 << 31) |
#define DPLL_SDVO_HIGH_SPEED (1 << 30) |
#define DPLL_DVO_2X_MODE (1 << 30) |
1237,10 → 1661,23 |
#define DPLL_LOCK_VLV (1<<15) |
#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
#define DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
#define DPLL_SSC_REF_CLOCK_CHV (1<<13) |
#define DPLL_PORTC_READY_MASK (0xf << 4) |
#define DPLL_PORTB_READY_MASK (0xf) |
|
#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
|
/* Additional CHV pll/phy registers */ |
#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) |
#define DPLL_PORTD_READY_MASK (0xf) |
#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) |
#define PHY_COM_LANE_RESET_DEASSERT(phy, val) \ |
((phy == DPIO_PHY0) ? (val | 1) : (val | 2)) |
#define PHY_COM_LANE_RESET_ASSERT(phy, val) \ |
((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2)) |
#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) |
#define PHY_POWERGOOD(phy) ((phy == DPIO_PHY0) ? (1<<31) : (1<<30)) |
|
/* |
* The i830 generation, in LVDS mode, defines P1 as the bit number set within |
* this field (only one bit may be set). |
1278,7 → 1715,12 |
#define SDVO_MULTIPLIER_MASK 0x000000ff |
#define SDVO_MULTIPLIER_SHIFT_HIRES 4 |
#define SDVO_MULTIPLIER_SHIFT_VGA 0 |
#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */ |
|
#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) |
#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) |
#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) |
#define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) |
|
/* |
* UDI pixel divider, controlling how many pixels are stuffed into a packet. |
* |
1315,8 → 1757,6 |
*/ |
#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */ |
#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) |
|
#define _FPA0 0x06040 |
#define _FPA1 0x06044 |
1348,7 → 1788,7 |
#define DSTATE_PLL_D3_OFF (1<<3) |
#define DSTATE_GFX_CLOCK_GATING (1<<1) |
#define DSTATE_DOT_CLOCK_GATING (1<<0) |
#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200) |
#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) |
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ |
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ |
1377,7 → 1817,7 |
# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ |
# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) |
# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) |
/** |
/* |
* This bit must be set on the 830 to prevent hangs when turning off the |
* overlay scaler. |
*/ |
1397,12 → 1837,12 |
# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) |
# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) |
# define MAG_CLOCK_GATE_DISABLE (1 << 5) |
/** This bit must be unset on 855,865 */ |
/* This bit must be unset on 855,865 */ |
# define MECI_CLOCK_GATE_DISABLE (1 << 4) |
# define DCMP_CLOCK_GATE_DISABLE (1 << 3) |
# define MEC_CLOCK_GATE_DISABLE (1 << 2) |
# define MECO_CLOCK_GATE_DISABLE (1 << 1) |
/** This bit must be set on 855,865. */ |
/* This bit must be set on 855,865. */ |
# define SV_CLOCK_GATE_DISABLE (1 << 0) |
# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) |
# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) |
1423,7 → 1863,7 |
# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) |
|
# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) |
/** This bit must always be set on 965G/965GM */ |
/* This bit must always be set on 965G/965GM */ |
# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) |
# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) |
1430,7 → 1870,7 |
# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) |
# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) |
# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) |
/** This bit must always be set on 965G */ |
/* This bit must always be set on 965G */ |
# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) |
# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) |
1455,6 → 1895,10 |
#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
|
#define VDECCLK_GATE_D 0x620C /* g4x only */ |
#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) |
|
#define RAMCLK_GATE_D 0x6210 /* CRL only */ |
#define DEUC 0x6214 /* CRL only */ |
|
1472,11 → 1916,12 |
/* |
* Palette regs |
*/ |
#define PALETTE_A_OFFSET 0xa000 |
#define PALETTE_B_OFFSET 0xa800 |
#define CHV_PALETTE_C_OFFSET 0xc000 |
#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ |
dev_priv->info.display_mmio_offset) |
|
#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) |
#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) |
#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) |
|
/* MCH MMIO space */ |
|
/* |
1496,7 → 1941,7 |
/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
|
/** 915-945 and GM965 MCH register controlling DRAM channel access */ |
/* 915-945 and GM965 MCH register controlling DRAM channel access */ |
#define DCC 0x10200 |
#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) |
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) |
1505,15 → 1950,15 |
#define DCC_CHANNEL_XOR_DISABLE (1 << 10) |
#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
|
/** Pineview MCH register contains DDR3 setting */ |
/* Pineview MCH register contains DDR3 setting */ |
#define CSHRDDR3CTL 0x101a8 |
#define CSHRDDR3CTL_DDR3 (1 << 2) |
|
/** 965 MCH register controlling DRAM channel configuration */ |
/* 965 MCH register controlling DRAM channel configuration */ |
#define C0DRB3 0x10206 |
#define C1DRB3 0x10606 |
|
/** snb MCH registers for reading the DRAM channel configuration */ |
/* snb MCH registers for reading the DRAM channel configuration */ |
#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) |
#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) |
#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) |
1535,7 → 1980,7 |
#define MAD_DIMM_A_SIZE_SHIFT 0 |
#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) |
|
/** snb MCH registers for priority tuning */ |
/* snb MCH registers for priority tuning */ |
#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) |
#define MCH_SSKPD_WM0_MASK 0x3f |
#define MCH_SSKPD_WM0_VAL 0xc |
1839,7 → 2284,7 |
/* Same as Haswell, but 72064 bytes now. */ |
#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) |
|
|
#define CHV_CLK_CTL1 0x101100 |
#define VLV_CLK_CTL2 0x101104 |
#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 |
|
1862,7 → 2307,7 |
*/ |
|
/* Pipe A CRC regs */ |
#define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050) |
#define _PIPE_CRC_CTL_A 0x60050 |
#define PIPE_CRC_ENABLE (1 << 31) |
/* ivb+ source selection */ |
#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) |
1902,11 → 2347,11 |
#define _PIPE_CRC_RES_4_A_IVB 0x60070 |
#define _PIPE_CRC_RES_5_A_IVB 0x60074 |
|
#define _PIPE_CRC_RES_RED_A (dev_priv->info->display_mmio_offset + 0x60060) |
#define _PIPE_CRC_RES_GREEN_A (dev_priv->info->display_mmio_offset + 0x60064) |
#define _PIPE_CRC_RES_BLUE_A (dev_priv->info->display_mmio_offset + 0x60068) |
#define _PIPE_CRC_RES_RES1_A_I915 (dev_priv->info->display_mmio_offset + 0x6006c) |
#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080) |
#define _PIPE_CRC_RES_RED_A 0x60060 |
#define _PIPE_CRC_RES_GREEN_A 0x60064 |
#define _PIPE_CRC_RES_BLUE_A 0x60068 |
#define _PIPE_CRC_RES_RES1_A_I915 0x6006c |
#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 |
|
/* Pipe B CRC regs */ |
#define _PIPE_CRC_RES_1_B_IVB 0x61064 |
1915,64 → 2360,76 |
#define _PIPE_CRC_RES_4_B_IVB 0x61070 |
#define _PIPE_CRC_RES_5_B_IVB 0x61074 |
|
#define PIPE_CRC_CTL(pipe) _PIPE_INC(pipe, _PIPE_CRC_CTL_A, 0x01000) |
#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) |
#define PIPE_CRC_RES_1_IVB(pipe) \ |
_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) |
#define PIPE_CRC_RES_2_IVB(pipe) \ |
_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) |
#define PIPE_CRC_RES_3_IVB(pipe) \ |
_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) |
#define PIPE_CRC_RES_4_IVB(pipe) \ |
_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) |
#define PIPE_CRC_RES_5_IVB(pipe) \ |
_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) |
|
#define PIPE_CRC_RES_RED(pipe) \ |
_PIPE_INC(pipe, _PIPE_CRC_RES_RED_A, 0x01000) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) |
#define PIPE_CRC_RES_GREEN(pipe) \ |
_PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A, 0x01000) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) |
#define PIPE_CRC_RES_BLUE(pipe) \ |
_PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A, 0x01000) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) |
#define PIPE_CRC_RES_RES1_I915(pipe) \ |
_PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_I915, 0x01000) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) |
#define PIPE_CRC_RES_RES2_G4X(pipe) \ |
_PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000) |
_TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) |
|
/* Pipe A timing regs */ |
#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000) |
#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004) |
#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008) |
#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c) |
#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010) |
#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014) |
#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c) |
#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020) |
#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028) |
#define _HTOTAL_A 0x60000 |
#define _HBLANK_A 0x60004 |
#define _HSYNC_A 0x60008 |
#define _VTOTAL_A 0x6000c |
#define _VBLANK_A 0x60010 |
#define _VSYNC_A 0x60014 |
#define _PIPEASRC 0x6001c |
#define _BCLRPAT_A 0x60020 |
#define _VSYNCSHIFT_A 0x60028 |
|
/* Pipe B timing regs */ |
#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000) |
#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004) |
#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008) |
#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c) |
#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010) |
#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014) |
#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c) |
#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020) |
#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028) |
#define _HTOTAL_B 0x61000 |
#define _HBLANK_B 0x61004 |
#define _HSYNC_B 0x61008 |
#define _VTOTAL_B 0x6100c |
#define _VBLANK_B 0x61010 |
#define _VSYNC_B 0x61014 |
#define _PIPEBSRC 0x6101c |
#define _BCLRPAT_B 0x61020 |
#define _VSYNCSHIFT_B 0x61028 |
|
#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) |
#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) |
#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) |
#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) |
#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) |
#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) |
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) |
#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) |
#define TRANSCODER_A_OFFSET 0x60000 |
#define TRANSCODER_B_OFFSET 0x61000 |
#define TRANSCODER_C_OFFSET 0x62000 |
#define CHV_TRANSCODER_C_OFFSET 0x63000 |
#define TRANSCODER_EDP_OFFSET 0x6f000 |
|
#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ |
dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ |
dev_priv->info.display_mmio_offset) |
|
#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) |
#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) |
#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) |
#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) |
#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) |
#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) |
#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) |
#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) |
#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) |
|
/* HSW+ eDP PSR registers */ |
#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) |
#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) |
#define EDP_PSR_ENABLE (1<<31) |
#define BDW_PSR_SINGLE_FRAME (1<<30) |
#define EDP_PSR_LINK_DISABLE (0<<27) |
#define EDP_PSR_LINK_STANDBY (1<<27) |
#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) |
2084,7 → 2541,7 |
|
|
/* Hotplug control (945+ only) */ |
#define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110) |
#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) |
#define PORTB_HOTPLUG_INT_EN (1 << 29) |
#define PORTC_HOTPLUG_INT_EN (1 << 28) |
#define PORTD_HOTPLUG_INT_EN (1 << 27) |
2114,7 → 2571,7 |
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
|
#define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114) |
#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) |
/* |
* HDMI/DP bits are gen4+ |
* |
2130,8 → 2587,14 |
#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) |
#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) |
#define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) |
#define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) |
#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) |
#define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) |
#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) |
/* CRT/TV common between gen3+ */ |
#define CRT_HOTPLUG_INT_STATUS (1 << 11) |
#define TV_HOTPLUG_INT_STATUS (1 << 10) |
2177,6 → 2640,7 |
#define GEN3_SDVOC 0x61160 |
#define GEN4_HDMIB GEN3_SDVOB |
#define GEN4_HDMIC GEN3_SDVOC |
#define CHV_HDMID 0x6116C |
#define PCH_SDVOB 0xe1140 |
#define PCH_HDMIB PCH_SDVOB |
#define PCH_HDMIC 0xe1150 |
2184,7 → 2648,7 |
|
#define PORT_DFT_I9XX 0x61150 |
#define DC_BALANCE_RESET (1 << 25) |
#define PORT_DFT2_G4X 0x61154 |
#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) |
#define DC_BALANCE_RESET_VLV (1 << 31) |
#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) |
#define PIPE_B_SCRAMBLE_RESET (1 << 1) |
2197,7 → 2661,7 |
#define SDVO_PIPE_B_SELECT (1 << 30) |
#define SDVO_STALL_SELECT (1 << 29) |
#define SDVO_INTERRUPT_ENABLE (1 << 26) |
/** |
/* |
* 915G/GM SDVO pixel multiplier. |
* Programmed value is multiplier - 1, up to 5x. |
* \sa DPLL_MD_UDI_MULTIPLIER_MASK |
2237,7 → 2701,11 |
#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
#define SDVO_PIPE_SEL_MASK_CPT (3 << 29) |
|
/* CHV SDVO/HDMI bits: */ |
#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) |
#define SDVO_PIPE_SEL_MASK_CHV (3 << 24) |
|
|
/* DVO port control */ |
#define DVOA 0x61120 |
#define DVOB 0x61140 |
2332,9 → 2800,7 |
#define VIDEO_DIP_CTL 0x61170 |
/* Pre HSW: */ |
#define VIDEO_DIP_ENABLE (1 << 31) |
#define VIDEO_DIP_PORT_B (1 << 29) |
#define VIDEO_DIP_PORT_C (2 << 29) |
#define VIDEO_DIP_PORT_D (3 << 29) |
#define VIDEO_DIP_PORT(port) ((port) << 29) |
#define VIDEO_DIP_PORT_MASK (3 << 29) |
#define VIDEO_DIP_ENABLE_GCP (1 << 25) |
#define VIDEO_DIP_ENABLE_AVI (1 << 21) |
2391,7 → 2857,7 |
#define PP_DIVISOR 0x61210 |
|
/* Panel fitting */ |
#define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230) |
#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) |
#define PFIT_ENABLE (1 << 31) |
#define PFIT_PIPE_MASK (3 << 29) |
#define PFIT_PIPE_SHIFT 29 |
2409,7 → 2875,7 |
#define PFIT_SCALING_PROGRAMMED (1 << 26) |
#define PFIT_SCALING_PILLAR (2 << 26) |
#define PFIT_SCALING_LETTER (3 << 26) |
#define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234) |
#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) |
/* Pre-965 */ |
#define PFIT_VERT_SCALE_SHIFT 20 |
#define PFIT_VERT_SCALE_MASK 0xfff00000 |
2421,25 → 2887,25 |
#define PFIT_HORIZ_SCALE_SHIFT_965 0 |
#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
|
#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238) |
#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) |
|
#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250) |
#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350) |
#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) |
#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) |
#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ |
_VLV_BLC_PWM_CTL2_B) |
|
#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254) |
#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354) |
#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) |
#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) |
#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ |
_VLV_BLC_PWM_CTL_B) |
|
#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260) |
#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360) |
#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) |
#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) |
#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ |
_VLV_BLC_HIST_CTL_B) |
|
/* Backlight control */ |
#define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */ |
#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ |
#define BLM_PWM_ENABLE (1 << 31) |
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ |
#define BLM_PIPE_SELECT (1 << 29) |
2462,7 → 2928,7 |
#define BLM_PHASE_IN_COUNT_MASK (0xff << 8) |
#define BLM_PHASE_IN_INCR_SHIFT (0) |
#define BLM_PHASE_IN_INCR_MASK (0xff << 0) |
#define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254) |
#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) |
/* |
* This is the most significant 15 bits of the number of backlight cycles in a |
* complete cycle of the modulated backlight control. |
2484,7 → 2950,7 |
#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
|
#define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260) |
#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) |
|
/* New registers for PCH-split platforms. Safe where new bits show up, the |
* register layout machtes with gen4 BLC_PWM_CTL[12]. */ |
2509,65 → 2975,65 |
|
/* TV port control */ |
#define TV_CTL 0x68000 |
/** Enables the TV encoder */ |
/* Enables the TV encoder */ |
# define TV_ENC_ENABLE (1 << 31) |
/** Sources the TV encoder input from pipe B instead of A. */ |
/* Sources the TV encoder input from pipe B instead of A. */ |
# define TV_ENC_PIPEB_SELECT (1 << 30) |
/** Outputs composite video (DAC A only) */ |
/* Outputs composite video (DAC A only) */ |
# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
/** Outputs SVideo video (DAC B/C) */ |
/* Outputs SVideo video (DAC B/C) */ |
# define TV_ENC_OUTPUT_SVIDEO (1 << 28) |
/** Outputs Component video (DAC A/B/C) */ |
/* Outputs Component video (DAC A/B/C) */ |
# define TV_ENC_OUTPUT_COMPONENT (2 << 28) |
/** Outputs Composite and SVideo (DAC A/B/C) */ |
/* Outputs Composite and SVideo (DAC A/B/C) */ |
# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
# define TV_TRILEVEL_SYNC (1 << 21) |
/** Enables slow sync generation (945GM only) */ |
/* Enables slow sync generation (945GM only) */ |
# define TV_SLOW_SYNC (1 << 20) |
/** Selects 4x oversampling for 480i and 576p */ |
/* Selects 4x oversampling for 480i and 576p */ |
# define TV_OVERSAMPLE_4X (0 << 18) |
/** Selects 2x oversampling for 720p and 1080i */ |
/* Selects 2x oversampling for 720p and 1080i */ |
# define TV_OVERSAMPLE_2X (1 << 18) |
/** Selects no oversampling for 1080p */ |
/* Selects no oversampling for 1080p */ |
# define TV_OVERSAMPLE_NONE (2 << 18) |
/** Selects 8x oversampling */ |
/* Selects 8x oversampling */ |
# define TV_OVERSAMPLE_8X (3 << 18) |
/** Selects progressive mode rather than interlaced */ |
/* Selects progressive mode rather than interlaced */ |
# define TV_PROGRESSIVE (1 << 17) |
/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ |
/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ |
# define TV_PAL_BURST (1 << 16) |
/** Field for setting delay of Y compared to C */ |
/* Field for setting delay of Y compared to C */ |
# define TV_YC_SKEW_MASK (7 << 12) |
/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ |
/* Enables a fix for 480p/576p standard definition modes on the 915GM only */ |
# define TV_ENC_SDP_FIX (1 << 11) |
/** |
/* |
* Enables a fix for the 915GM only. |
* |
* Not sure what it does. |
*/ |
# define TV_ENC_C0_FIX (1 << 10) |
/** Bits that must be preserved by software */ |
/* Bits that must be preserved by software */ |
# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
# define TV_FUSE_STATE_MASK (3 << 4) |
/** Read-only state that reports all features enabled */ |
/* Read-only state that reports all features enabled */ |
# define TV_FUSE_STATE_ENABLED (0 << 4) |
/** Read-only state that reports that Macrovision is disabled in hardware*/ |
/* Read-only state that reports that Macrovision is disabled in hardware*/ |
# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
/** Read-only state that reports that TV-out is disabled in hardware. */ |
/* Read-only state that reports that TV-out is disabled in hardware. */ |
# define TV_FUSE_STATE_DISABLED (2 << 4) |
/** Normal operation */ |
/* Normal operation */ |
# define TV_TEST_MODE_NORMAL (0 << 0) |
/** Encoder test pattern 1 - combo pattern */ |
/* Encoder test pattern 1 - combo pattern */ |
# define TV_TEST_MODE_PATTERN_1 (1 << 0) |
/** Encoder test pattern 2 - full screen vertical 75% color bars */ |
/* Encoder test pattern 2 - full screen vertical 75% color bars */ |
# define TV_TEST_MODE_PATTERN_2 (2 << 0) |
/** Encoder test pattern 3 - full screen horizontal 75% color bars */ |
/* Encoder test pattern 3 - full screen horizontal 75% color bars */ |
# define TV_TEST_MODE_PATTERN_3 (3 << 0) |
/** Encoder test pattern 4 - random noise */ |
/* Encoder test pattern 4 - random noise */ |
# define TV_TEST_MODE_PATTERN_4 (4 << 0) |
/** Encoder test pattern 5 - linear color ramps */ |
/* Encoder test pattern 5 - linear color ramps */ |
# define TV_TEST_MODE_PATTERN_5 (5 << 0) |
/** |
/* |
* This test mode forces the DACs to 50% of full output. |
* |
* This is used for load detection in combination with TVDAC_SENSE_MASK |
2577,7 → 3043,7 |
|
#define TV_DAC 0x68004 |
# define TV_DAC_SAVE 0x00ffff00 |
/** |
/* |
* Reports that DAC state change logic has reported change (RO). |
* |
* This gets cleared when TV_DAC_STATE_EN is cleared |
2584,13 → 3050,13 |
*/ |
# define TVDAC_STATE_CHG (1 << 31) |
# define TVDAC_SENSE_MASK (7 << 28) |
/** Reports that DAC A voltage is above the detect threshold */ |
/* Reports that DAC A voltage is above the detect threshold */ |
# define TVDAC_A_SENSE (1 << 30) |
/** Reports that DAC B voltage is above the detect threshold */ |
/* Reports that DAC B voltage is above the detect threshold */ |
# define TVDAC_B_SENSE (1 << 29) |
/** Reports that DAC C voltage is above the detect threshold */ |
/* Reports that DAC C voltage is above the detect threshold */ |
# define TVDAC_C_SENSE (1 << 28) |
/** |
/* |
* Enables DAC state detection logic, for load-based TV detection. |
* |
* The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set |
2597,15 → 3063,15 |
* to off, for load detection to work. |
*/ |
# define TVDAC_STATE_CHG_EN (1 << 27) |
/** Sets the DAC A sense value to high */ |
/* Sets the DAC A sense value to high */ |
# define TVDAC_A_SENSE_CTL (1 << 26) |
/** Sets the DAC B sense value to high */ |
/* Sets the DAC B sense value to high */ |
# define TVDAC_B_SENSE_CTL (1 << 25) |
/** Sets the DAC C sense value to high */ |
/* Sets the DAC C sense value to high */ |
# define TVDAC_C_SENSE_CTL (1 << 24) |
/** Overrides the ENC_ENABLE and DAC voltage levels */ |
/* Overrides the ENC_ENABLE and DAC voltage levels */ |
# define DAC_CTL_OVERRIDE (1 << 7) |
/** Sets the slew rate. Must be preserved in software */ |
/* Sets the slew rate. Must be preserved in software */ |
# define ENC_TVDAC_SLEW_FAST (1 << 6) |
# define DAC_A_1_3_V (0 << 4) |
# define DAC_A_1_1_V (1 << 4) |
2620,7 → 3086,7 |
# define DAC_C_0_7_V (2 << 0) |
# define DAC_C_MASK (3 << 0) |
|
/** |
/* |
* CSC coefficients are stored in a floating point format with 9 bits of |
* mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, |
* where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with |
2635,7 → 3101,7 |
#define TV_CSC_Y2 0x68014 |
# define TV_BY_MASK 0x07ff0000 |
# define TV_BY_SHIFT 16 |
/** |
/* |
* Y attenuation for component video. |
* |
* Stored in 1.9 fixed point. |
2652,7 → 3118,7 |
#define TV_CSC_U2 0x6801c |
# define TV_BU_MASK 0x07ff0000 |
# define TV_BU_SHIFT 16 |
/** |
/* |
* U attenuation for component video. |
* |
* Stored in 1.9 fixed point. |
2669,7 → 3135,7 |
#define TV_CSC_V2 0x68024 |
# define TV_BV_MASK 0x07ff0000 |
# define TV_BV_SHIFT 16 |
/** |
/* |
* V attenuation for component video. |
* |
* Stored in 1.9 fixed point. |
2678,74 → 3144,74 |
# define TV_AV_SHIFT 0 |
|
#define TV_CLR_KNOBS 0x68028 |
/** 2s-complement brightness adjustment */ |
/* 2s-complement brightness adjustment */ |
# define TV_BRIGHTNESS_MASK 0xff000000 |
# define TV_BRIGHTNESS_SHIFT 24 |
/** Contrast adjustment, as a 2.6 unsigned floating point number */ |
/* Contrast adjustment, as a 2.6 unsigned floating point number */ |
# define TV_CONTRAST_MASK 0x00ff0000 |
# define TV_CONTRAST_SHIFT 16 |
/** Saturation adjustment, as a 2.6 unsigned floating point number */ |
/* Saturation adjustment, as a 2.6 unsigned floating point number */ |
# define TV_SATURATION_MASK 0x0000ff00 |
# define TV_SATURATION_SHIFT 8 |
/** Hue adjustment, as an integer phase angle in degrees */ |
/* Hue adjustment, as an integer phase angle in degrees */ |
# define TV_HUE_MASK 0x000000ff |
# define TV_HUE_SHIFT 0 |
|
#define TV_CLR_LEVEL 0x6802c |
/** Controls the DAC level for black */ |
/* Controls the DAC level for black */ |
# define TV_BLACK_LEVEL_MASK 0x01ff0000 |
# define TV_BLACK_LEVEL_SHIFT 16 |
/** Controls the DAC level for blanking */ |
/* Controls the DAC level for blanking */ |
# define TV_BLANK_LEVEL_MASK 0x000001ff |
# define TV_BLANK_LEVEL_SHIFT 0 |
|
#define TV_H_CTL_1 0x68030 |
/** Number of pixels in the hsync. */ |
/* Number of pixels in the hsync. */ |
# define TV_HSYNC_END_MASK 0x1fff0000 |
# define TV_HSYNC_END_SHIFT 16 |
/** Total number of pixels minus one in the line (display and blanking). */ |
/* Total number of pixels minus one in the line (display and blanking). */ |
# define TV_HTOTAL_MASK 0x00001fff |
# define TV_HTOTAL_SHIFT 0 |
|
#define TV_H_CTL_2 0x68034 |
/** Enables the colorburst (needed for non-component color) */ |
/* Enables the colorburst (needed for non-component color) */ |
# define TV_BURST_ENA (1 << 31) |
/** Offset of the colorburst from the start of hsync, in pixels minus one. */ |
/* Offset of the colorburst from the start of hsync, in pixels minus one. */ |
# define TV_HBURST_START_SHIFT 16 |
# define TV_HBURST_START_MASK 0x1fff0000 |
/** Length of the colorburst */ |
/* Length of the colorburst */ |
# define TV_HBURST_LEN_SHIFT 0 |
# define TV_HBURST_LEN_MASK 0x0001fff |
|
#define TV_H_CTL_3 0x68038 |
/** End of hblank, measured in pixels minus one from start of hsync */ |
/* End of hblank, measured in pixels minus one from start of hsync */ |
# define TV_HBLANK_END_SHIFT 16 |
# define TV_HBLANK_END_MASK 0x1fff0000 |
/** Start of hblank, measured in pixels minus one from start of hsync */ |
/* Start of hblank, measured in pixels minus one from start of hsync */ |
# define TV_HBLANK_START_SHIFT 0 |
# define TV_HBLANK_START_MASK 0x0001fff |
|
#define TV_V_CTL_1 0x6803c |
/** XXX */ |
/* XXX */ |
# define TV_NBR_END_SHIFT 16 |
# define TV_NBR_END_MASK 0x07ff0000 |
/** XXX */ |
/* XXX */ |
# define TV_VI_END_F1_SHIFT 8 |
# define TV_VI_END_F1_MASK 0x00003f00 |
/** XXX */ |
/* XXX */ |
# define TV_VI_END_F2_SHIFT 0 |
# define TV_VI_END_F2_MASK 0x0000003f |
|
#define TV_V_CTL_2 0x68040 |
/** Length of vsync, in half lines */ |
/* Length of vsync, in half lines */ |
# define TV_VSYNC_LEN_MASK 0x07ff0000 |
# define TV_VSYNC_LEN_SHIFT 16 |
/** Offset of the start of vsync in field 1, measured in one less than the |
/* Offset of the start of vsync in field 1, measured in one less than the |
* number of half lines. |
*/ |
# define TV_VSYNC_START_F1_MASK 0x00007f00 |
# define TV_VSYNC_START_F1_SHIFT 8 |
/** |
/* |
* Offset of the start of vsync in field 2, measured in one less than the |
* number of half lines. |
*/ |
2753,17 → 3219,17 |
# define TV_VSYNC_START_F2_SHIFT 0 |
|
#define TV_V_CTL_3 0x68044 |
/** Enables generation of the equalization signal */ |
/* Enables generation of the equalization signal */ |
# define TV_EQUAL_ENA (1 << 31) |
/** Length of vsync, in half lines */ |
/* Length of vsync, in half lines */ |
# define TV_VEQ_LEN_MASK 0x007f0000 |
# define TV_VEQ_LEN_SHIFT 16 |
/** Offset of the start of equalization in field 1, measured in one less than |
/* Offset of the start of equalization in field 1, measured in one less than |
* the number of half lines. |
*/ |
# define TV_VEQ_START_F1_MASK 0x0007f00 |
# define TV_VEQ_START_F1_SHIFT 8 |
/** |
/* |
* Offset of the start of equalization in field 2, measured in one less than |
* the number of half lines. |
*/ |
2771,13 → 3237,13 |
# define TV_VEQ_START_F2_SHIFT 0 |
|
#define TV_V_CTL_4 0x68048 |
/** |
/* |
* Offset to start of vertical colorburst, measured in one less than the |
* number of lines from vertical start. |
*/ |
# define TV_VBURST_START_F1_MASK 0x003f0000 |
# define TV_VBURST_START_F1_SHIFT 16 |
/** |
/* |
* Offset to the end of vertical colorburst, measured in one less than the |
* number of lines from the start of NBR. |
*/ |
2785,13 → 3251,13 |
# define TV_VBURST_END_F1_SHIFT 0 |
|
#define TV_V_CTL_5 0x6804c |
/** |
/* |
* Offset to start of vertical colorburst, measured in one less than the |
* number of lines from vertical start. |
*/ |
# define TV_VBURST_START_F2_MASK 0x003f0000 |
# define TV_VBURST_START_F2_SHIFT 16 |
/** |
/* |
* Offset to the end of vertical colorburst, measured in one less than the |
* number of lines from the start of NBR. |
*/ |
2799,13 → 3265,13 |
# define TV_VBURST_END_F2_SHIFT 0 |
|
#define TV_V_CTL_6 0x68050 |
/** |
/* |
* Offset to start of vertical colorburst, measured in one less than the |
* number of lines from vertical start. |
*/ |
# define TV_VBURST_START_F3_MASK 0x003f0000 |
# define TV_VBURST_START_F3_SHIFT 16 |
/** |
/* |
* Offset to the end of vertical colorburst, measured in one less than the |
* number of lines from the start of NBR. |
*/ |
2813,13 → 3279,13 |
# define TV_VBURST_END_F3_SHIFT 0 |
|
#define TV_V_CTL_7 0x68054 |
/** |
/* |
* Offset to start of vertical colorburst, measured in one less than the |
* number of lines from vertical start. |
*/ |
# define TV_VBURST_START_F4_MASK 0x003f0000 |
# define TV_VBURST_START_F4_SHIFT 16 |
/** |
/* |
* Offset to the end of vertical colorburst, measured in one less than the |
* number of lines from the start of NBR. |
*/ |
2827,56 → 3293,56 |
# define TV_VBURST_END_F4_SHIFT 0 |
|
#define TV_SC_CTL_1 0x68060 |
/** Turns on the first subcarrier phase generation DDA */ |
/* Turns on the first subcarrier phase generation DDA */ |
# define TV_SC_DDA1_EN (1 << 31) |
/** Turns on the first subcarrier phase generation DDA */ |
/* Turns on the first subcarrier phase generation DDA */ |
# define TV_SC_DDA2_EN (1 << 30) |
/** Turns on the first subcarrier phase generation DDA */ |
/* Turns on the first subcarrier phase generation DDA */ |
# define TV_SC_DDA3_EN (1 << 29) |
/** Sets the subcarrier DDA to reset frequency every other field */ |
/* Sets the subcarrier DDA to reset frequency every other field */ |
# define TV_SC_RESET_EVERY_2 (0 << 24) |
/** Sets the subcarrier DDA to reset frequency every fourth field */ |
/* Sets the subcarrier DDA to reset frequency every fourth field */ |
# define TV_SC_RESET_EVERY_4 (1 << 24) |
/** Sets the subcarrier DDA to reset frequency every eighth field */ |
/* Sets the subcarrier DDA to reset frequency every eighth field */ |
# define TV_SC_RESET_EVERY_8 (2 << 24) |
/** Sets the subcarrier DDA to never reset the frequency */ |
/* Sets the subcarrier DDA to never reset the frequency */ |
# define TV_SC_RESET_NEVER (3 << 24) |
/** Sets the peak amplitude of the colorburst.*/ |
/* Sets the peak amplitude of the colorburst.*/ |
# define TV_BURST_LEVEL_MASK 0x00ff0000 |
# define TV_BURST_LEVEL_SHIFT 16 |
/** Sets the increment of the first subcarrier phase generation DDA */ |
/* Sets the increment of the first subcarrier phase generation DDA */ |
# define TV_SCDDA1_INC_MASK 0x00000fff |
# define TV_SCDDA1_INC_SHIFT 0 |
|
#define TV_SC_CTL_2 0x68064 |
/** Sets the rollover for the second subcarrier phase generation DDA */ |
/* Sets the rollover for the second subcarrier phase generation DDA */ |
# define TV_SCDDA2_SIZE_MASK 0x7fff0000 |
# define TV_SCDDA2_SIZE_SHIFT 16 |
/** Sets the increent of the second subcarrier phase generation DDA */ |
/* Sets the increent of the second subcarrier phase generation DDA */ |
# define TV_SCDDA2_INC_MASK 0x00007fff |
# define TV_SCDDA2_INC_SHIFT 0 |
|
#define TV_SC_CTL_3 0x68068 |
/** Sets the rollover for the third subcarrier phase generation DDA */ |
/* Sets the rollover for the third subcarrier phase generation DDA */ |
# define TV_SCDDA3_SIZE_MASK 0x7fff0000 |
# define TV_SCDDA3_SIZE_SHIFT 16 |
/** Sets the increent of the third subcarrier phase generation DDA */ |
/* Sets the increent of the third subcarrier phase generation DDA */ |
# define TV_SCDDA3_INC_MASK 0x00007fff |
# define TV_SCDDA3_INC_SHIFT 0 |
|
#define TV_WIN_POS 0x68070 |
/** X coordinate of the display from the start of horizontal active */ |
/* X coordinate of the display from the start of horizontal active */ |
# define TV_XPOS_MASK 0x1fff0000 |
# define TV_XPOS_SHIFT 16 |
/** Y coordinate of the display from the start of vertical active (NBR) */ |
/* Y coordinate of the display from the start of vertical active (NBR) */ |
# define TV_YPOS_MASK 0x00000fff |
# define TV_YPOS_SHIFT 0 |
|
#define TV_WIN_SIZE 0x68074 |
/** Horizontal size of the display window, measured in pixels*/ |
/* Horizontal size of the display window, measured in pixels*/ |
# define TV_XSIZE_MASK 0x1fff0000 |
# define TV_XSIZE_SHIFT 16 |
/** |
/* |
* Vertical size of the display window, measured in pixels. |
* |
* Must be even for interlaced modes. |
2885,7 → 3351,7 |
# define TV_YSIZE_SHIFT 0 |
|
#define TV_FILTER_CTL_1 0x68080 |
/** |
/* |
* Enables automatic scaling calculation. |
* |
* If set, the rest of the registers are ignored, and the calculated values can |
2892,21 → 3358,21 |
* be read back from the register. |
*/ |
# define TV_AUTO_SCALE (1 << 31) |
/** |
/* |
* Disables the vertical filter. |
* |
* This is required on modes more than 1024 pixels wide */ |
# define TV_V_FILTER_BYPASS (1 << 29) |
/** Enables adaptive vertical filtering */ |
/* Enables adaptive vertical filtering */ |
# define TV_VADAPT (1 << 28) |
# define TV_VADAPT_MODE_MASK (3 << 26) |
/** Selects the least adaptive vertical filtering mode */ |
/* Selects the least adaptive vertical filtering mode */ |
# define TV_VADAPT_MODE_LEAST (0 << 26) |
/** Selects the moderately adaptive vertical filtering mode */ |
/* Selects the moderately adaptive vertical filtering mode */ |
# define TV_VADAPT_MODE_MODERATE (1 << 26) |
/** Selects the most adaptive vertical filtering mode */ |
/* Selects the most adaptive vertical filtering mode */ |
# define TV_VADAPT_MODE_MOST (3 << 26) |
/** |
/* |
* Sets the horizontal scaling factor. |
* |
* This should be the fractional part of the horizontal scaling factor divided |
2918,7 → 3384,7 |
# define TV_HSCALE_FRAC_SHIFT 0 |
|
#define TV_FILTER_CTL_2 0x68084 |
/** |
/* |
* Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
* |
* TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) |
2925,7 → 3391,7 |
*/ |
# define TV_VSCALE_INT_MASK 0x00038000 |
# define TV_VSCALE_INT_SHIFT 15 |
/** |
/* |
* Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
* |
* \sa TV_VSCALE_INT_MASK |
2934,7 → 3400,7 |
# define TV_VSCALE_FRAC_SHIFT 0 |
|
#define TV_FILTER_CTL_3 0x68088 |
/** |
/* |
* Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
* |
* TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) |
2943,7 → 3409,7 |
*/ |
# define TV_VSCALE_IP_INT_MASK 0x00038000 |
# define TV_VSCALE_IP_INT_SHIFT 15 |
/** |
/* |
* Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
* |
* For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. |
2955,7 → 3421,7 |
|
#define TV_CC_CONTROL 0x68090 |
# define TV_CC_ENABLE (1 << 31) |
/** |
/* |
* Specifies which field to send the CC data in. |
* |
* CC data is usually sent in field 0. |
2962,19 → 3428,19 |
*/ |
# define TV_CC_FID_MASK (1 << 27) |
# define TV_CC_FID_SHIFT 27 |
/** Sets the horizontal position of the CC data. Usually 135. */ |
/* Sets the horizontal position of the CC data. Usually 135. */ |
# define TV_CC_HOFF_MASK 0x03ff0000 |
# define TV_CC_HOFF_SHIFT 16 |
/** Sets the vertical position of the CC data. Usually 21 */ |
/* Sets the vertical position of the CC data. Usually 21 */ |
# define TV_CC_LINE_MASK 0x0000003f |
# define TV_CC_LINE_SHIFT 0 |
|
#define TV_CC_DATA 0x68094 |
# define TV_CC_RDY (1 << 31) |
/** Second word of CC data to be transmitted. */ |
/* Second word of CC data to be transmitted. */ |
# define TV_CC_DATA_2_MASK 0x007f0000 |
# define TV_CC_DATA_2_SHIFT 16 |
/** First word of CC data to be transmitted. */ |
/* First word of CC data to be transmitted. */ |
# define TV_CC_DATA_1_MASK 0x0000007f |
# define TV_CC_DATA_1_SHIFT 0 |
|
2996,6 → 3462,8 |
#define DP_PORT_EN (1 << 31) |
#define DP_PIPEB_SELECT (1 << 30) |
#define DP_PIPE_MASK (1 << 30) |
#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) |
#define DP_PIPE_MASK_CHV (3 << 16) |
|
/* Link training mode - select a suitable mode for each stage */ |
#define DP_LINK_TRAIN_PAT_1 (0 << 28) |
3043,32 → 3511,32 |
#define DP_PLL_FREQ_160MHZ (1 << 16) |
#define DP_PLL_FREQ_MASK (3 << 16) |
|
/** locked once port is enabled */ |
/* locked once port is enabled */ |
#define DP_PORT_REVERSAL (1 << 15) |
|
/* eDP */ |
#define DP_PLL_ENABLE (1 << 14) |
|
/** sends the clock on lane 15 of the PEG for debug */ |
/* sends the clock on lane 15 of the PEG for debug */ |
#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
|
#define DP_SCRAMBLING_DISABLE (1 << 12) |
#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
|
/** limit RGB values to avoid confusing TVs */ |
/* limit RGB values to avoid confusing TVs */ |
#define DP_COLOR_RANGE_16_235 (1 << 8) |
|
/** Turn on the audio link */ |
/* Turn on the audio link */ |
#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
|
/** vs and hs sync polarity */ |
/* vs and hs sync polarity */ |
#define DP_SYNC_VS_HIGH (1 << 4) |
#define DP_SYNC_HS_HIGH (1 << 3) |
|
/** A fantasy */ |
/* A fantasy */ |
#define DP_DETECTED (1 << 2) |
|
/** The aux channel provides a way to talk to the |
/* The aux channel provides a way to talk to the |
* signal sink for DDC etc. Max packet size supported |
* is 20 bytes in each direction, hence the 5 fixed |
* data registers |
3178,10 → 3646,10 |
/* Display & cursor control */ |
|
/* Pipe A */ |
#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000) |
#define _PIPEADSL 0x70000 |
#define DSL_LINEMASK_GEN2 0x00000fff |
#define DSL_LINEMASK_GEN3 0x00001fff |
#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008) |
#define _PIPEACONF 0x70008 |
#define PIPECONF_ENABLE (1<<31) |
#define PIPECONF_DISABLE 0 |
#define PIPECONF_DOUBLE_WIDE (1<<30) |
3211,6 → 3679,7 |
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ |
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ |
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21) |
#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) |
#define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
#define PIPECONF_BPC_MASK (0x7 << 5) |
3224,11 → 3693,12 |
#define PIPECONF_DITHER_TYPE_ST1 (1<<2) |
#define PIPECONF_DITHER_TYPE_ST2 (2<<2) |
#define PIPECONF_DITHER_TYPE_TEMP (3<<2) |
#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024) |
#define _PIPEASTAT 0x70024 |
#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) |
#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) |
#define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
#define PIPE_CRC_DONE_ENABLE (1UL<<28) |
#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) |
#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
3239,36 → 3709,64 |
#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) |
#define PERF_COUNTER_INTERRUPT_EN (1UL<<19) |
#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) |
#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
#define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14) |
#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) |
#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) |
#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) |
#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
#define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) |
#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) |
#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
#define PIPE_DPST_EVENT_STATUS (1UL<<7) |
#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
#define PIPE_A_PSR_STATUS_VLV (1UL<<6) |
#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) |
#define PIPE_B_PSR_STATUS_VLV (1UL<<3) |
#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) |
#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ |
#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) |
#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
#define PIPE_HBLANK_INT_STATUS (1UL<<0) |
#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
|
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) |
#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) |
#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) |
#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) |
#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 |
#define PIPESTAT_INT_STATUS_MASK 0x0000ffff |
|
#define PIPE_A_OFFSET 0x70000 |
#define PIPE_B_OFFSET 0x71000 |
#define PIPE_C_OFFSET 0x72000 |
#define CHV_PIPE_C_OFFSET 0x74000 |
/* |
* There's actually no pipe EDP. Some pipe registers have |
* simply shifted from the pipe to the transcoder, while |
* keeping their original offset. Thus we need PIPE_EDP_OFFSET |
* to access such registers in transcoder EDP. |
*/ |
#define PIPE_EDP_OFFSET 0x7f000 |
|
#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ |
dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ |
dev_priv->info.display_mmio_offset) |
|
#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) |
#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) |
#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) |
#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) |
#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) |
|
#define _PIPE_MISC_A 0x70030 |
#define _PIPE_MISC_B 0x71030 |
#define PIPEMISC_DITHER_BPC_MASK (7<<5) |
3279,23 → 3777,34 |
#define PIPEMISC_DITHER_ENABLE (1<<4) |
#define PIPEMISC_DITHER_TYPE_MASK (3<<2) |
#define PIPEMISC_DITHER_TYPE_SP (0<<2) |
#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) |
#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) |
|
#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) |
#define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
#define PIPEB_HLINE_INT_EN (1<<28) |
#define PIPEB_VBLANK_INT_EN (1<<27) |
#define SPRITED_FLIPDONE_INT_EN (1<<26) |
#define SPRITEC_FLIPDONE_INT_EN (1<<25) |
#define PLANEB_FLIPDONE_INT_EN (1<<24) |
#define SPRITED_FLIP_DONE_INT_EN (1<<26) |
#define SPRITEC_FLIP_DONE_INT_EN (1<<25) |
#define PLANEB_FLIP_DONE_INT_EN (1<<24) |
#define PIPE_PSR_INT_EN (1<<22) |
#define PIPEA_LINE_COMPARE_INT_EN (1<<21) |
#define PIPEA_HLINE_INT_EN (1<<20) |
#define PIPEA_VBLANK_INT_EN (1<<19) |
#define SPRITEB_FLIPDONE_INT_EN (1<<18) |
#define SPRITEA_FLIPDONE_INT_EN (1<<17) |
#define SPRITEB_FLIP_DONE_INT_EN (1<<18) |
#define SPRITEA_FLIP_DONE_INT_EN (1<<17) |
#define PLANEA_FLIPDONE_INT_EN (1<<16) |
#define PIPEC_LINE_COMPARE_INT_EN (1<<13) |
#define PIPEC_HLINE_INT_EN (1<<12) |
#define PIPEC_VBLANK_INT_EN (1<<11) |
#define SPRITEF_FLIPDONE_INT_EN (1<<10) |
#define SPRITEE_FLIPDONE_INT_EN (1<<9) |
#define PLANEC_FLIPDONE_INT_EN (1<<8) |
|
#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */ |
#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ |
#define SPRITEF_INVALID_GTT_INT_EN (1<<27) |
#define SPRITEE_INVALID_GTT_INT_EN (1<<26) |
#define PLANEC_INVALID_GTT_INT_EN (1<<25) |
#define CURSORC_INVALID_GTT_INT_EN (1<<24) |
#define CURSORB_INVALID_GTT_INT_EN (1<<23) |
#define CURSORA_INVALID_GTT_INT_EN (1<<22) |
#define SPRITED_INVALID_GTT_INT_EN (1<<21) |
3305,6 → 3814,11 |
#define SPRITEA_INVALID_GTT_INT_EN (1<<17) |
#define PLANEA_INVALID_GTT_INT_EN (1<<16) |
#define DPINVGTT_EN_MASK 0xff0000 |
#define DPINVGTT_EN_MASK_CHV 0xfff0000 |
#define SPRITEF_INVALID_GTT_STATUS (1<<11) |
#define SPRITEE_INVALID_GTT_STATUS (1<<10) |
#define PLANEC_INVALID_GTT_STATUS (1<<9) |
#define CURSORC_INVALID_GTT_STATUS (1<<8) |
#define CURSORB_INVALID_GTT_STATUS (1<<7) |
#define CURSORA_INVALID_GTT_STATUS (1<<6) |
#define SPRITED_INVALID_GTT_STATUS (1<<5) |
3314,6 → 3828,7 |
#define SPRITEA_INVALID_GTT_STATUS (1<<1) |
#define PLANEA_INVALID_GTT_STATUS (1<<0) |
#define DPINVGTT_STATUS_MASK 0xff |
#define DPINVGTT_STATUS_MASK_CHV 0xfff |
|
#define DSPARB 0x70030 |
#define DSPARB_CSTART_MASK (0x7f << 7) |
3323,7 → 3838,7 |
#define DSPARB_BEND_SHIFT 9 /* on 855 */ |
#define DSPARB_AEND_SHIFT 0 |
|
#define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034) |
#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) |
#define DSPFW_SR_SHIFT 23 |
#define DSPFW_SR_MASK (0x1ff<<23) |
#define DSPFW_CURSORB_SHIFT 16 |
3331,11 → 3846,11 |
#define DSPFW_PLANEB_SHIFT 8 |
#define DSPFW_PLANEB_MASK (0x7f<<8) |
#define DSPFW_PLANEA_MASK (0x7f) |
#define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038) |
#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) |
#define DSPFW_CURSORA_MASK 0x00003f00 |
#define DSPFW_CURSORA_SHIFT 8 |
#define DSPFW_PLANEC_MASK (0x7f) |
#define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c) |
#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) |
#define DSPFW_HPLL_SR_EN (1<<31) |
#define DSPFW_CURSOR_SR_SHIFT 24 |
#define PINEVIEW_SELF_REFRESH_EN (1<<30) |
3343,25 → 3858,54 |
#define DSPFW_HPLL_CURSOR_SHIFT 16 |
#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
#define DSPFW_HPLL_SR_MASK (0x1ff) |
#define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070) |
#define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c) |
#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070) |
#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c) |
|
/* drain latency register values*/ |
#define DRAIN_LATENCY_PRECISION_32 32 |
#define DRAIN_LATENCY_PRECISION_16 16 |
#define DRAIN_LATENCY_PRECISION_64 64 |
#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) |
#define DDL_CURSORA_PRECISION_32 (1<<31) |
#define DDL_CURSORA_PRECISION_16 (0<<31) |
#define DDL_CURSORA_PRECISION_64 (1<<31) |
#define DDL_CURSORA_PRECISION_32 (0<<31) |
#define DDL_CURSORA_SHIFT 24 |
#define DDL_PLANEA_PRECISION_32 (1<<7) |
#define DDL_PLANEA_PRECISION_16 (0<<7) |
#define DDL_SPRITEB_PRECISION_64 (1<<23) |
#define DDL_SPRITEB_PRECISION_32 (0<<23) |
#define DDL_SPRITEB_SHIFT 16 |
#define DDL_SPRITEA_PRECISION_64 (1<<15) |
#define DDL_SPRITEA_PRECISION_32 (0<<15) |
#define DDL_SPRITEA_SHIFT 8 |
#define DDL_PLANEA_PRECISION_64 (1<<7) |
#define DDL_PLANEA_PRECISION_32 (0<<7) |
#define DDL_PLANEA_SHIFT 0 |
|
#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) |
#define DDL_CURSORB_PRECISION_32 (1<<31) |
#define DDL_CURSORB_PRECISION_16 (0<<31) |
#define DDL_CURSORB_PRECISION_64 (1<<31) |
#define DDL_CURSORB_PRECISION_32 (0<<31) |
#define DDL_CURSORB_SHIFT 24 |
#define DDL_PLANEB_PRECISION_32 (1<<7) |
#define DDL_PLANEB_PRECISION_16 (0<<7) |
#define DDL_SPRITED_PRECISION_64 (1<<23) |
#define DDL_SPRITED_PRECISION_32 (0<<23) |
#define DDL_SPRITED_SHIFT 16 |
#define DDL_SPRITEC_PRECISION_64 (1<<15) |
#define DDL_SPRITEC_PRECISION_32 (0<<15) |
#define DDL_SPRITEC_SHIFT 8 |
#define DDL_PLANEB_PRECISION_64 (1<<7) |
#define DDL_PLANEB_PRECISION_32 (0<<7) |
#define DDL_PLANEB_SHIFT 0 |
|
#define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058) |
#define DDL_CURSORC_PRECISION_64 (1<<31) |
#define DDL_CURSORC_PRECISION_32 (0<<31) |
#define DDL_CURSORC_SHIFT 24 |
#define DDL_SPRITEF_PRECISION_64 (1<<23) |
#define DDL_SPRITEF_PRECISION_32 (0<<23) |
#define DDL_SPRITEF_SHIFT 16 |
#define DDL_SPRITEE_PRECISION_64 (1<<15) |
#define DDL_SPRITEE_PRECISION_32 (0<<15) |
#define DDL_SPRITEE_SHIFT 8 |
#define DDL_PLANEC_PRECISION_64 (1<<7) |
#define DDL_PLANEC_PRECISION_32 (0<<7) |
#define DDL_PLANEC_SHIFT 0 |
|
/* FIFO watermark sizes etc */ |
#define G4X_FIFO_LINE_SIZE 64 |
#define I915_FIFO_LINE_SIZE 64 |
3468,12 → 4012,13 |
#define PIPE_PIXEL_MASK 0x00ffffff |
#define PIPE_PIXEL_SHIFT 0 |
/* GM45+ just has to be different */ |
#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70040) |
#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70044) |
#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) |
#define _PIPEA_FRMCOUNT_GM45 0x70040 |
#define _PIPEA_FLIPCOUNT_GM45 0x70044 |
#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) |
#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) |
|
/* Cursor A & B regs */ |
#define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080) |
#define _CURACNTR 0x70080 |
/* Old style CUR*CNTR flags (desktop 8xx) */ |
#define CURSOR_ENABLE 0x80000000 |
#define CURSOR_GAMMA_ENABLE 0x40000000 |
3489,7 → 4034,11 |
/* New style CUR*CNTR flags */ |
#define CURSOR_MODE 0x27 |
#define CURSOR_MODE_DISABLE 0x00 |
#define CURSOR_MODE_128_32B_AX 0x02 |
#define CURSOR_MODE_256_32B_AX 0x03 |
#define CURSOR_MODE_64_32B_AX 0x07 |
#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) |
#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) |
#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) |
#define MCURSOR_PIPE_SELECT (1 << 28) |
#define MCURSOR_PIPE_A 0x00 |
3496,31 → 4045,37 |
#define MCURSOR_PIPE_B (1 << 28) |
#define MCURSOR_GAMMA_ENABLE (1 << 26) |
#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) |
#define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084) |
#define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088) |
#define _CURABASE 0x70084 |
#define _CURAPOS 0x70088 |
#define CURSOR_POS_MASK 0x007FF |
#define CURSOR_POS_SIGN 0x8000 |
#define CURSOR_X_SHIFT 0 |
#define CURSOR_Y_SHIFT 16 |
#define CURSIZE 0x700a0 |
#define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0) |
#define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4) |
#define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8) |
#define _CURBCNTR 0x700c0 |
#define _CURBBASE 0x700c4 |
#define _CURBPOS 0x700c8 |
|
#define _CURBCNTR_IVB 0x71080 |
#define _CURBBASE_IVB 0x71084 |
#define _CURBPOS_IVB 0x71088 |
|
#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) |
#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) |
#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) |
#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ |
dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ |
dev_priv->info.display_mmio_offset) |
|
#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) |
#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) |
#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) |
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) |
#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) |
#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) |
|
#define CURSOR_A_OFFSET 0x70080 |
#define CURSOR_B_OFFSET 0x700c0 |
#define CHV_CURSOR_C_OFFSET 0x700e0 |
#define IVB_CURSOR_B_OFFSET 0x71080 |
#define IVB_CURSOR_C_OFFSET 0x72080 |
|
/* Display A control */ |
#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180) |
#define _DSPACNTR 0x70180 |
#define DISPLAY_PLANE_ENABLE (1<<31) |
#define DISPLAY_PLANE_DISABLE 0 |
#define DISPPLANE_GAMMA_ENABLE (1<<30) |
3554,25 → 4109,25 |
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
#define DISPPLANE_TILED (1<<10) |
#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) |
#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188) |
#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */ |
#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190) |
#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */ |
#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */ |
#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */ |
#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC) |
#define _DSPAADDR 0x70184 |
#define _DSPASTRIDE 0x70188 |
#define _DSPAPOS 0x7018C /* reserved */ |
#define _DSPASIZE 0x70190 |
#define _DSPASURF 0x7019C /* 965+ only */ |
#define _DSPATILEOFF 0x701A4 /* 965+ only */ |
#define _DSPAOFFSET 0x701A4 /* HSW */ |
#define _DSPASURFLIVE 0x701AC |
|
#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) |
#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) |
#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) |
#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) |
#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) |
#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) |
#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) |
#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) |
#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) |
#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) |
#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) |
#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) |
#define DSPSURF(plane) _PIPE2(plane, _DSPASURF) |
#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) |
#define DSPLINOFF(plane) DSPADDR(plane) |
#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) |
#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) |
#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) |
#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) |
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/* Display/Sprite base address macros */ |
#define DISP_BASEADDR_MASK (0xfffff000) |
3580,44 → 4135,44 |
#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) |
|
/* VBIOS flags */ |
#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410) |
#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414) |
#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418) |
#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c) |
#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420) |
#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424) |
#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428) |
#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410) |
#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414) |
#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420) |
#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414) |
#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418) |
#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c) |
#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) |
#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) |
#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) |
#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) |
#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) |
#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) |
#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) |
#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) |
#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) |
#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) |
#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) |
#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) |
#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) |
|
/* Pipe B */ |
#define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000) |
#define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008) |
#define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024) |
#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) |
#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) |
#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) |
#define _PIPEBFRAMEHIGH 0x71040 |
#define _PIPEBFRAMEPIXEL 0x71044 |
#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71040) |
#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71044) |
#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) |
#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) |
|
|
/* Display B control */ |
#define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180) |
#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) |
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
#define DISPPLANE_ALPHA_TRANS_DISABLE 0 |
#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 |
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) |
#define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184) |
#define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188) |
#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C) |
#define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190) |
#define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C) |
#define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4) |
#define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4) |
#define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC) |
#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) |
#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) |
#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) |
#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) |
#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) |
#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) |
#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) |
#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) |
|
/* Sprite A control */ |
#define _DVSACNTR 0x72180 |
3866,49 → 4421,46 |
#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff |
|
|
#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030) |
#define _PIPEA_DATA_M1 0x60030 |
#define PIPE_DATA_M1_OFFSET 0 |
#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034) |
#define _PIPEA_DATA_N1 0x60034 |
#define PIPE_DATA_N1_OFFSET 0 |
|
#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038) |
#define _PIPEA_DATA_M2 0x60038 |
#define PIPE_DATA_M2_OFFSET 0 |
#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c) |
#define _PIPEA_DATA_N2 0x6003c |
#define PIPE_DATA_N2_OFFSET 0 |
|
#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040) |
#define _PIPEA_LINK_M1 0x60040 |
#define PIPE_LINK_M1_OFFSET 0 |
#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044) |
#define _PIPEA_LINK_N1 0x60044 |
#define PIPE_LINK_N1_OFFSET 0 |
|
#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048) |
#define _PIPEA_LINK_M2 0x60048 |
#define PIPE_LINK_M2_OFFSET 0 |
#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c) |
#define _PIPEA_LINK_N2 0x6004c |
#define PIPE_LINK_N2_OFFSET 0 |
|
/* PIPEB timing regs are same start from 0x61000 */ |
|
#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030) |
#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034) |
#define _PIPEB_DATA_M1 0x61030 |
#define _PIPEB_DATA_N1 0x61034 |
#define _PIPEB_DATA_M2 0x61038 |
#define _PIPEB_DATA_N2 0x6103c |
#define _PIPEB_LINK_M1 0x61040 |
#define _PIPEB_LINK_N1 0x61044 |
#define _PIPEB_LINK_M2 0x61048 |
#define _PIPEB_LINK_N2 0x6104c |
|
#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038) |
#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c) |
#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) |
#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) |
#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) |
#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) |
#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) |
#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) |
#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) |
#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) |
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#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040) |
#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044) |
|
#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048) |
#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c) |
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#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) |
#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) |
#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) |
#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) |
#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) |
#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1) |
#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2) |
#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2) |
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/* CPU panel fitter */ |
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
#define _PFA_CTL_1 0x68080 |
4025,6 → 4577,7 |
#define GEN8_DE_PIPE_A_IRQ (1<<16) |
#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) |
#define GEN8_GT_VECS_IRQ (1<<6) |
#define GEN8_GT_PM_IRQ (1<<4) |
#define GEN8_GT_VCS2_IRQ (1<<3) |
#define GEN8_GT_VCS1_IRQ (1<<2) |
#define GEN8_GT_BCS_IRQ (1<<1) |
4052,7 → 4605,7 |
#define GEN8_PIPE_SPRITE_FAULT (1 << 9) |
#define GEN8_PIPE_PRIMARY_FAULT (1 << 8) |
#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) |
#define GEN8_PIPE_FLIP_DONE (1 << 4) |
#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
#define GEN8_PIPE_VSYNC (1 << 1) |
#define GEN8_PIPE_VBLANK (1 << 0) |
4084,12 → 4637,13 |
#define ILK_ELPIN_409_SELECT (1 << 25) |
#define ILK_DPARB_GATE (1<<22) |
#define ILK_VSDPFD_FULL (1<<21) |
#define ILK_DISPLAY_CHICKEN_FUSES 0x42014 |
#define FUSE_STRAP 0x42014 |
#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) |
#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) |
#define ILK_DISPLAY_DEBUG_DISABLE (1<<29) |
#define ILK_HDCP_DISABLE (1<<25) |
#define ILK_eDP_A_DISABLE (1<<24) |
#define HSW_CDCLK_LIMIT (1 << 24) |
#define ILK_DESKTOP (1<<23) |
|
#define ILK_DSPCLK_GATE_D 0x42020 |
4109,7 → 4663,8 |
|
#define _CHICKEN_PIPESL_1_A 0x420b0 |
#define _CHICKEN_PIPESL_1_B 0x420b4 |
#define DPRS_MASK_VBLANK_SRD (1 << 0) |
#define HSW_FBCQ_DIS (1 << 22) |
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) |
#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
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#define DISP_ARB_CTL 0x45000 |
4120,6 → 4675,8 |
#define GEN7_MSG_CTL 0x45010 |
#define WAIT_FOR_PCH_RESET_ACK (1<<1) |
#define WAIT_FOR_PCH_FLR_ACK (1<<0) |
#define HSW_NDE_RSTWRN_OPT 0x46408 |
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4) |
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/* GEN7 chicken */ |
#define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
4127,9 → 4684,14 |
#define COMMON_SLICE_CHICKEN2 0x7014 |
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) |
|
#define GEN7_L3SQCREG1 0xB010 |
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 |
|
#define GEN7_L3CNTLREG1 0xB01C |
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C |
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |
#define GEN7_L3AGDIS (1<<19) |
#define GEN7_L3CNTLREG2 0xB020 |
#define GEN7_L3CNTLREG3 0xB024 |
|
#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 |
#define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
4148,9 → 4710,6 |
#define HSW_SCRATCH1 0xb038 |
#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) |
|
#define HSW_FUSE_STRAP 0x42014 |
#define HSW_CDCLK_LIMIT (1 << 24) |
|
/* PCH */ |
|
/* south display engine interrupt: IBX */ |
4379,8 → 4938,7 |
#define _PCH_TRANSA_LINK_M2 0xe0048 |
#define _PCH_TRANSA_LINK_N2 0xe004c |
|
/* Per-transcoder DIP controls */ |
|
/* Per-transcoder DIP controls (PCH) */ |
#define _VIDEO_DIP_CTL_A 0xe0200 |
#define _VIDEO_DIP_DATA_A 0xe0208 |
#define _VIDEO_DIP_GCP_A 0xe0210 |
4393,6 → 4951,7 |
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
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/* Per-transcoder DIP controls (VLV) */ |
#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) |
#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) |
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) |
4401,12 → 4960,19 |
#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) |
#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) |
|
#define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) |
#define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) |
#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) |
|
#define VLV_TVIDEO_DIP_CTL(pipe) \ |
_PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) |
_PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \ |
VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C) |
#define VLV_TVIDEO_DIP_DATA(pipe) \ |
_PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) |
_PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \ |
VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C) |
#define VLV_TVIDEO_DIP_GCP(pipe) \ |
_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) |
_PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ |
VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C) |
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/* Haswell DIP controls */ |
#define HSW_VIDEO_DIP_CTL_A 0x60200 |
4436,17 → 5002,17 |
#define HSW_VIDEO_DIP_GCP_B 0x61210 |
|
#define HSW_TVIDEO_DIP_CTL(trans) \ |
_TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) |
_TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) |
#define HSW_TVIDEO_DIP_AVI_DATA(trans) \ |
_TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) |
_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) |
#define HSW_TVIDEO_DIP_VS_DATA(trans) \ |
_TRANSCODER(trans, HSW_VIDEO_DIP_VS_DATA_A, HSW_VIDEO_DIP_VS_DATA_B) |
_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) |
#define HSW_TVIDEO_DIP_SPD_DATA(trans) \ |
_TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) |
_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) |
#define HSW_TVIDEO_DIP_GCP(trans) \ |
_TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) |
_TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) |
#define HSW_TVIDEO_DIP_VSC_DATA(trans) \ |
_TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B) |
_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) |
|
#define HSW_STEREO_3D_CTL_A 0x70020 |
#define S3D_ENABLE (1<<31) |
4453,7 → 5019,7 |
#define HSW_STEREO_3D_CTL_B 0x71020 |
|
#define HSW_STEREO_3D_CTL(trans) \ |
_TRANSCODER(trans, HSW_STEREO_3D_CTL_A, HSW_STEREO_3D_CTL_A) |
_PIPE2(trans, HSW_STEREO_3D_CTL_A) |
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#define _PCH_TRANS_HTOTAL_B 0xe1000 |
#define _PCH_TRANS_HBLANK_B 0xe1004 |
4760,6 → 5326,8 |
#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) |
#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) |
#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) |
#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) |
|
#define TRANS_DP_CTL_A 0xe0300 |
#define TRANS_DP_CTL_B 0xe1300 |
4816,6 → 5384,8 |
|
#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
|
#define VLV_PMWGICZ 0x1300a4 |
|
#define FORCEWAKE 0xA18C |
#define FORCEWAKE_VLV 0x1300b0 |
#define FORCEWAKE_ACK_VLV 0x1300b4 |
4824,9 → 5394,16 |
#define FORCEWAKE_ACK_HSW 0x130044 |
#define FORCEWAKE_ACK 0x130090 |
#define VLV_GTLC_WAKE_CTRL 0x130090 |
#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) |
#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) |
#define VLV_GTLC_ALLOWWAKEREQ (1 << 0) |
|
#define VLV_GTLC_PW_STATUS 0x130094 |
#define VLV_GTLC_PW_RENDER_STATUS_MASK 0x80 |
#define VLV_GTLC_PW_MEDIA_STATUS_MASK 0x20 |
#define VLV_GTLC_ALLOWWAKEACK (1 << 0) |
#define VLV_GTLC_ALLOWWAKEERR (1 << 1) |
#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) |
#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) |
#define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
#define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
#define FORCEWAKE_KERNEL 0x1 |
#define FORCEWAKE_USER 0x2 |
4833,6 → 5410,7 |
#define FORCEWAKE_MT_ACK 0x130040 |
#define ECOBUS 0xa180 |
#define FORCEWAKE_MT_ENABLE (1<<5) |
#define VLV_SPAREG2H 0xA194 |
|
#define GTFIFODBG 0x120000 |
#define GT_FIFO_SBDROPERR (1<<6) |
4852,6 → 5430,7 |
#define HSW_EDRAM_PRESENT 0x120010 |
|
#define GEN6_UCGCTL1 0x9400 |
# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) |
# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
|
4862,9 → 5441,19 |
# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
|
#define GEN6_UCGCTL3 0x9408 |
|
#define GEN7_UCGCTL4 0x940c |
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) |
|
#define GEN6_RCGCTL1 0x9410 |
#define GEN6_RCGCTL2 0x9414 |
#define GEN6_RSTCTL 0x9420 |
|
#define GEN8_UCGCTL6 0x9430 |
#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) |
|
#define GEN6_GFXPAUSE 0xA000 |
#define GEN6_RPNSWREQ 0xA008 |
#define GEN6_TURBO_DISABLE (1<<31) |
#define GEN6_FREQUENCY(x) ((x)<<25) |
4917,6 → 5506,9 |
#define GEN6_RP_UP_EI 0xA068 |
#define GEN6_RP_DOWN_EI 0xA06C |
#define GEN6_RP_IDLE_HYSTERSIS 0xA070 |
#define GEN6_RPDEUHWTC 0xA080 |
#define GEN6_RPDEUC 0xA084 |
#define GEN6_RPDEUCSW 0xA088 |
#define GEN6_RC_STATE 0xA094 |
#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 |
#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C |
4924,11 → 5516,15 |
#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 |
#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC |
#define GEN6_RC_SLEEP 0xA0B0 |
#define GEN6_RCUBMABDTMR 0xA0B0 |
#define GEN6_RC1e_THRESHOLD 0xA0B4 |
#define GEN6_RC6_THRESHOLD 0xA0B8 |
#define GEN6_RC6p_THRESHOLD 0xA0BC |
#define VLV_RCEDATA 0xA0BC |
#define GEN6_RC6pp_THRESHOLD 0xA0C0 |
#define GEN6_PMINTRMSK 0xA168 |
#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) |
#define VLV_PWRDWNUPCTL 0xA294 |
|
#define GEN6_PMISR 0x44020 |
#define GEN6_PMIMR 0x44024 /* rps_lock */ |
4945,14 → 5541,34 |
GEN6_PM_RP_DOWN_THRESHOLD | \ |
GEN6_PM_RP_DOWN_TIMEOUT) |
|
#define CHV_CZ_CLOCK_FREQ_MODE_200 200 |
#define CHV_CZ_CLOCK_FREQ_MODE_267 267 |
#define CHV_CZ_CLOCK_FREQ_MODE_320 320 |
#define CHV_CZ_CLOCK_FREQ_MODE_333 333 |
#define CHV_CZ_CLOCK_FREQ_MODE_400 400 |
|
#define GEN7_GT_SCRATCH_BASE 0x4F100 |
#define GEN7_GT_SCRATCH_REG_NUM 8 |
|
#define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
#define VLV_GFX_CLK_STATUS_BIT (1<<3) |
#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) |
|
#define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
#define VLV_COUNTER_CONTROL 0x138104 |
#define VLV_COUNT_RANGE_HIGH (1<<15) |
#define VLV_MEDIA_RC0_COUNT_EN (1<<5) |
#define VLV_RENDER_RC0_COUNT_EN (1<<4) |
#define VLV_MEDIA_RC6_COUNT_EN (1<<1) |
#define VLV_RENDER_RC6_COUNT_EN (1<<0) |
#define GEN6_GT_GFX_RC6 0x138108 |
#define VLV_GT_RENDER_RC6 0x138108 |
#define VLV_GT_MEDIA_RC6 0x13810C |
|
#define GEN6_GT_GFX_RC6p 0x13810C |
#define GEN6_GT_GFX_RC6pp 0x138110 |
#define VLV_RENDER_C0_COUNT_REG 0x138118 |
#define VLV_MEDIA_C0_COUNT_REG 0x13811C |
|
#define GEN6_PCODE_MAILBOX 0x138124 |
#define GEN6_PCODE_READY (1<<31) |
5006,6 → 5622,10 |
#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
|
#define GEN8_ROW_CHICKEN 0xe4f0 |
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) |
#define STALL_DOP_GATING_DISABLE (1<<5) |
|
#define GEN7_ROW_CHICKEN2 0xe4f4 |
#define GEN7_ROW_CHICKEN2_GT2 0xf4f4 |
#define DOP_CLOCK_GATING_DISABLE (1<<0) |
5017,7 → 5637,7 |
#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) |
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
|
#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020) |
#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) |
#define INTEL_AUDIO_DEVCL 0x808629FB |
#define INTEL_AUDIO_DEVBLC 0x80862801 |
#define INTEL_AUDIO_DEVCTG 0x80862802 |
5178,11 → 5798,12 |
#define TRANS_DDI_FUNC_CTL_B 0x61400 |
#define TRANS_DDI_FUNC_CTL_C 0x62400 |
#define TRANS_DDI_FUNC_CTL_EDP 0x6F400 |
#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ |
TRANS_DDI_FUNC_CTL_B) |
#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) |
|
#define TRANS_DDI_FUNC_ENABLE (1<<31) |
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
#define TRANS_DDI_PORT_MASK (7<<28) |
#define TRANS_DDI_PORT_SHIFT 28 |
#define TRANS_DDI_SELECT_PORT(x) ((x)<<28) |
#define TRANS_DDI_PORT_NONE (0<<28) |
#define TRANS_DDI_MODE_SELECT_MASK (7<<24) |
5203,6 → 5824,7 |
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) |
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) |
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) |
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) |
#define TRANS_DDI_BFI_ENABLE (1<<4) |
|
/* DisplayPort Transport Control */ |
5212,6 → 5834,7 |
#define DP_TP_CTL_ENABLE (1<<31) |
#define DP_TP_CTL_MODE_SST (0<<27) |
#define DP_TP_CTL_MODE_MST (1<<27) |
#define DP_TP_CTL_FORCE_ACT (1<<25) |
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
5227,7 → 5850,12 |
#define DP_TP_STATUS_B 0x64144 |
#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) |
#define DP_TP_STATUS_IDLE_DONE (1<<25) |
#define DP_TP_STATUS_ACT_SENT (1<<24) |
#define DP_TP_STATUS_MODE_STATUS_MST (1<<23) |
#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) |
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) |
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) |
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) |
|
/* DDI Buffer Control */ |
#define DDI_BUF_CTL_A 0x64000 |
5234,7 → 5862,6 |
#define DDI_BUF_CTL_B 0x64100 |
#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
#define DDI_BUF_CTL_ENABLE (1<<31) |
/* Haswell */ |
#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
5244,16 → 5871,6 |
#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ |
#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
/* Broadwell */ |
#define DDI_BUF_EMP_400MV_0DB_BDW (0<<24) /* Sel0 */ |
#define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24) /* Sel1 */ |
#define DDI_BUF_EMP_400MV_6DB_BDW (2<<24) /* Sel2 */ |
#define DDI_BUF_EMP_600MV_0DB_BDW (3<<24) /* Sel3 */ |
#define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24) /* Sel4 */ |
#define DDI_BUF_EMP_600MV_6DB_BDW (5<<24) /* Sel5 */ |
#define DDI_BUF_EMP_800MV_0DB_BDW (6<<24) /* Sel6 */ |
#define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24) /* Sel7 */ |
#define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24) /* Sel8 */ |
#define DDI_BUF_EMP_MASK (0xf<<24) |
#define DDI_BUF_PORT_REVERSAL (1<<16) |
#define DDI_BUF_IS_IDLE (1<<7) |
5311,20 → 5928,31 |
#define SPLL_PLL_ENABLE (1<<31) |
#define SPLL_PLL_SSC (1<<28) |
#define SPLL_PLL_NON_SSC (2<<28) |
#define SPLL_PLL_LCPLL (3<<28) |
#define SPLL_PLL_REF_MASK (3<<28) |
#define SPLL_PLL_FREQ_810MHz (0<<26) |
#define SPLL_PLL_FREQ_1350MHz (1<<26) |
#define SPLL_PLL_FREQ_2700MHz (2<<26) |
#define SPLL_PLL_FREQ_MASK (3<<26) |
|
/* WRPLL */ |
#define WRPLL_CTL1 0x46040 |
#define WRPLL_CTL2 0x46060 |
#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) |
#define WRPLL_PLL_ENABLE (1<<31) |
#define WRPLL_PLL_SELECT_SSC (0x01<<28) |
#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28) |
#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) |
#define WRPLL_PLL_SSC (1<<28) |
#define WRPLL_PLL_NON_SSC (2<<28) |
#define WRPLL_PLL_LCPLL (3<<28) |
#define WRPLL_PLL_REF_MASK (3<<28) |
/* WRPLL divider programming */ |
#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) |
#define WRPLL_DIVIDER_REF_MASK (0xff) |
#define WRPLL_DIVIDER_POST(x) ((x)<<8) |
#define WRPLL_DIVIDER_POST_MASK (0x3f<<8) |
#define WRPLL_DIVIDER_POST_SHIFT 8 |
#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) |
#define WRPLL_DIVIDER_FB_SHIFT 16 |
#define WRPLL_DIVIDER_FB_MASK (0xff<<16) |
|
/* Port clock selection */ |
#define PORT_CLK_SEL_A 0x46100 |
5334,9 → 5962,11 |
#define PORT_CLK_SEL_LCPLL_1350 (1<<29) |
#define PORT_CLK_SEL_LCPLL_810 (2<<29) |
#define PORT_CLK_SEL_SPLL (3<<29) |
#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) |
#define PORT_CLK_SEL_WRPLL1 (4<<29) |
#define PORT_CLK_SEL_WRPLL2 (5<<29) |
#define PORT_CLK_SEL_NONE (7<<29) |
#define PORT_CLK_SEL_MASK (7<<29) |
|
/* Transcoder clock selection */ |
#define TRANS_CLK_SEL_A 0x46140 |
5346,10 → 5976,12 |
#define TRANS_CLK_SEL_DISABLED (0x0<<29) |
#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) |
|
#define _TRANSA_MSA_MISC 0x60410 |
#define _TRANSB_MSA_MISC 0x61410 |
#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ |
_TRANSB_MSA_MISC) |
#define TRANSA_MSA_MISC 0x60410 |
#define TRANSB_MSA_MISC 0x61410 |
#define TRANSC_MSA_MISC 0x62410 |
#define TRANS_EDP_MSA_MISC 0x6f410 |
#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) |
|
#define TRANS_MSA_SYNC_CLK (1<<0) |
#define TRANS_MSA_6_BPC (0<<5) |
#define TRANS_MSA_8_BPC (1<<5) |
5372,7 → 6004,10 |
#define LCPLL_CD_SOURCE_FCLK (1<<21) |
#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
|
#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
* since on HSW we can't write to it using I915_WRITE. */ |
#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |
#define D_COMP_BDW 0x138144 |
#define D_COMP_RCOMP_IN_PROGRESS (1<<9) |
#define D_COMP_COMP_FORCE (1<<8) |
#define D_COMP_COMP_DISABLE (1<<0) |
5389,6 → 6024,8 |
|
/* SFUSE_STRAP */ |
#define SFUSE_STRAP 0xc2014 |
#define SFUSE_STRAP_FUSE_LOCK (1<<13) |
#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) |
#define SFUSE_STRAP_DDIB_DETECTED (1<<2) |
#define SFUSE_STRAP_DDIC_DETECTED (1<<1) |
#define SFUSE_STRAP_DDID_DETECTED (1<<0) |
5451,7 → 6088,8 |
|
#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL) |
#define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ |
_MIPIB_PORT_CTRL) |
#define DPI_ENABLE (1 << 31) /* A + B */ |
#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) |
5493,7 → 6131,8 |
|
#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) |
#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) |
#define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ |
_MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) |
#define TEARING_EFFECT_DELAY_SHIFT 0 |
#define TEARING_EFFECT_DELAY_MASK (0xffff << 0) |
|
5502,9 → 6141,10 |
|
/* MIPI DSI Controller and D-PHY registers */ |
|
#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000) |
#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800) |
#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY) |
#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) |
#define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) |
#define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ |
_MIPIB_DEVICE_READY) |
#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
#define ULPS_STATE_MASK (3 << 1) |
#define ULPS_STATE_ENTER (2 << 1) |
5512,12 → 6152,14 |
#define ULPS_STATE_NORMAL_OPERATION (0 << 1) |
#define DEVICE_READY (1 << 0) |
|
#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004) |
#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804) |
#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT) |
#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008) |
#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808) |
#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN) |
#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) |
#define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) |
#define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ |
_MIPIB_INTR_STAT) |
#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) |
#define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) |
#define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ |
_MIPIB_INTR_EN) |
#define TEARING_EFFECT (1 << 31) |
#define SPL_PKT_SENT_INTERRUPT (1 << 30) |
#define GEN_READ_DATA_AVAIL (1 << 29) |
5551,9 → 6193,10 |
#define RXSOT_SYNC_ERROR (1 << 1) |
#define RXSOT_ERROR (1 << 0) |
|
#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c) |
#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c) |
#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG) |
#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) |
#define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) |
#define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ |
_MIPIB_DSI_FUNC_PRG) |
#define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
#define CMD_MODE_NOT_SUPPORTED (0 << 13) |
#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) |
5574,78 → 6217,94 |
#define DATA_LANES_PRG_REG_SHIFT 0 |
#define DATA_LANES_PRG_REG_MASK (7 << 0) |
|
#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010) |
#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810) |
#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT) |
#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) |
#define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) |
#define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ |
_MIPIB_HS_TX_TIMEOUT) |
#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
|
#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014) |
#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814) |
#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT) |
#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) |
#define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) |
#define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ |
_MIPIB_LP_RX_TIMEOUT) |
#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
|
#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018) |
#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818) |
#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) |
#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) |
#define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) |
#define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ |
_MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) |
#define TURN_AROUND_TIMEOUT_MASK 0x3f |
|
#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c) |
#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c) |
#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) |
#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) |
#define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) |
#define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ |
_MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) |
#define DEVICE_RESET_TIMER_MASK 0xffff |
|
#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020) |
#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820) |
#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION) |
#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) |
#define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) |
#define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ |
_MIPIB_DPI_RESOLUTION) |
#define VERTICAL_ADDRESS_SHIFT 16 |
#define VERTICAL_ADDRESS_MASK (0xffff << 16) |
#define HORIZONTAL_ADDRESS_SHIFT 0 |
#define HORIZONTAL_ADDRESS_MASK 0xffff |
|
#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024) |
#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824) |
#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) |
#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) |
#define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) |
#define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ |
_MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) |
#define DBI_FIFO_EMPTY_HALF (0 << 0) |
#define DBI_FIFO_EMPTY_QUARTER (1 << 0) |
#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) |
|
/* regs below are bits 15:0 */ |
#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028) |
#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828) |
#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) |
#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) |
#define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) |
#define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ |
_MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) |
|
#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c) |
#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c) |
#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT) |
#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) |
#define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) |
#define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ |
_MIPIB_HBP_COUNT) |
|
#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030) |
#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830) |
#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT) |
#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) |
#define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) |
#define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ |
_MIPIB_HFP_COUNT) |
|
#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034) |
#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834) |
#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) |
#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) |
#define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) |
#define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ |
_MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) |
|
#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038) |
#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838) |
#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) |
#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) |
#define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) |
#define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ |
_MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) |
|
#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c) |
#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c) |
#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT) |
#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) |
#define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) |
#define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ |
_MIPIB_VBP_COUNT) |
|
#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040) |
#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840) |
#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT) |
#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) |
#define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) |
#define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ |
_MIPIB_VFP_COUNT) |
|
#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044) |
#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844) |
#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) |
#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) |
#define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) |
#define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ |
_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) |
|
/* regs above are bits 15:0 */ |
|
#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048) |
#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848) |
#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL) |
#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) |
#define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) |
#define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ |
_MIPIB_DPI_CONTROL) |
#define DPI_LP_MODE (1 << 6) |
#define BACKLIGHT_OFF (1 << 5) |
#define BACKLIGHT_ON (1 << 4) |
5654,27 → 6313,31 |
#define TURN_ON (1 << 1) |
#define SHUTDOWN (1 << 0) |
|
#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c) |
#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c) |
#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA) |
#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) |
#define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) |
#define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ |
_MIPIB_DPI_DATA) |
#define COMMAND_BYTE_SHIFT 0 |
#define COMMAND_BYTE_MASK (0x3f << 0) |
|
#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050) |
#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850) |
#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT) |
#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) |
#define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) |
#define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ |
_MIPIB_INIT_COUNT) |
#define MASTER_INIT_TIMER_SHIFT 0 |
#define MASTER_INIT_TIMER_MASK (0xffff << 0) |
|
#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054) |
#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854) |
#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) |
#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) |
#define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) |
#define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ |
_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) |
#define MAX_RETURN_PKT_SIZE_SHIFT 0 |
#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) |
|
#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058) |
#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858) |
#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) |
#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) |
#define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) |
#define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ |
_MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) |
#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
#define DISABLE_VIDEO_BTA (1 << 3) |
#define IP_TG_CONFIG (1 << 2) |
5682,9 → 6345,10 |
#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) |
#define VIDEO_MODE_BURST (3 << 0) |
|
#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c) |
#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c) |
#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE) |
#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) |
#define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) |
#define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ |
_MIPIB_EOT_DISABLE) |
#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) |
#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) |
5694,28 → 6358,33 |
#define CLOCKSTOP (1 << 1) |
#define EOT_DISABLE (1 << 0) |
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#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060) |
#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860) |
#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK) |
#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) |
#define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) |
#define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ |
_MIPIB_LP_BYTECLK) |
#define LP_BYTECLK_SHIFT 0 |
#define LP_BYTECLK_MASK (0xffff << 0) |
|
/* bits 31:0 */ |
#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064) |
#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864) |
#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA) |
#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) |
#define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) |
#define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ |
_MIPIB_LP_GEN_DATA) |
|
/* bits 31:0 */ |
#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068) |
#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868) |
#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA) |
#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) |
#define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) |
#define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ |
_MIPIB_HS_GEN_DATA) |
|
#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c) |
#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c) |
#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL) |
#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070) |
#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870) |
#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL) |
#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) |
#define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) |
#define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ |
_MIPIB_LP_GEN_CTRL) |
#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) |
#define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) |
#define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ |
_MIPIB_HS_GEN_CTRL) |
#define LONG_PACKET_WORD_COUNT_SHIFT 8 |
#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) |
#define SHORT_PACKET_PARAM_SHIFT 8 |
5726,9 → 6395,10 |
#define DATA_TYPE_MASK (3f << 0) |
/* data type values, see include/video/mipi_display.h */ |
|
#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074) |
#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874) |
#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT) |
#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) |
#define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) |
#define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ |
_MIPIB_GEN_FIFO_STAT) |
#define DPI_FIFO_EMPTY (1 << 28) |
#define DBI_FIFO_EMPTY (1 << 27) |
#define LP_CTRL_FIFO_EMPTY (1 << 26) |
5744,16 → 6414,18 |
#define HS_DATA_FIFO_HALF_EMPTY (1 << 1) |
#define HS_DATA_FIFO_FULL (1 << 0) |
|
#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078) |
#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878) |
#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) |
#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) |
#define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) |
#define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ |
_MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) |
#define DBI_HS_LP_MODE_MASK (1 << 0) |
#define DBI_LP_MODE (1 << 0) |
#define DBI_HS_MODE (0 << 0) |
|
#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080) |
#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880) |
#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM) |
#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) |
#define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) |
#define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ |
_MIPIB_DPHY_PARAM) |
#define EXIT_ZERO_COUNT_SHIFT 24 |
#define EXIT_ZERO_COUNT_MASK (0x3f << 24) |
#define TRAIL_COUNT_SHIFT 16 |
5764,34 → 6436,41 |
#define PREPARE_COUNT_MASK (0x3f << 0) |
|
/* bits 31:0 */ |
#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084) |
#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884) |
#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL) |
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) |
#define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) |
#define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ |
_MIPIB_DBI_BW_CTRL) |
|
#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088) |
#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888) |
#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) |
#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
+ 0xb088) |
#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
+ 0xb888) |
#define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ |
_MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) |
#define LP_HS_SSW_CNT_SHIFT 16 |
#define LP_HS_SSW_CNT_MASK (0xffff << 16) |
#define HS_LP_PWR_SW_CNT_SHIFT 0 |
#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) |
|
#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c) |
#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c) |
#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) |
#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) |
#define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) |
#define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ |
_MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) |
#define STOP_STATE_STALL_COUNTER_SHIFT 0 |
#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) |
|
#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090) |
#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890) |
#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) |
#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094) |
#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894) |
#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1) |
#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) |
#define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) |
#define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ |
_MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) |
#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) |
#define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) |
#define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ |
_MIPIB_INTR_EN_REG_1) |
#define RX_CONTENTION_DETECTED (1 << 0) |
|
/* XXX: only pipe A ?!? */ |
#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100) |
#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) |
#define DBI_TYPEC_ENABLE (1 << 31) |
#define DBI_TYPEC_WIP (1 << 30) |
#define DBI_TYPEC_OPTION_SHIFT 28 |
5805,9 → 6484,10 |
|
/* MIPI adapter registers */ |
|
#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104) |
#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904) |
#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL) |
#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) |
#define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) |
#define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ |
_MIPIB_CTRL) |
#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) |
#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) |
5819,22 → 6499,25 |
#define READ_REQUEST_PRIORITY_HIGH (3 << 3) |
#define RGB_FLIP_TO_BGR (1 << 2) |
|
#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108) |
#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908) |
#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS) |
#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) |
#define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) |
#define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ |
_MIPIB_DATA_ADDRESS) |
#define DATA_MEM_ADDRESS_SHIFT 5 |
#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) |
#define DATA_VALID (1 << 0) |
|
#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c) |
#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c) |
#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH) |
#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) |
#define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) |
#define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ |
_MIPIB_DATA_LENGTH) |
#define DATA_LENGTH_SHIFT 0 |
#define DATA_LENGTH_MASK (0xfffff << 0) |
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#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110) |
#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910) |
#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) |
#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) |
#define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) |
#define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ |
_MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) |
#define COMMAND_MEM_ADDRESS_SHIFT 5 |
#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) |
#define AUTO_PWG_ENABLE (1 << 2) |
5841,20 → 6524,27 |
#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) |
#define COMMAND_VALID (1 << 0) |
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#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114) |
#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914) |
#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH) |
#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) |
#define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) |
#define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ |
_MIPIB_COMMAND_LENGTH) |
#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) |
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#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118) |
#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918) |
#define MIPI_READ_DATA_RETURN(pipe, n) \ |
(_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ |
#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) |
#define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) |
#define MIPI_READ_DATA_RETURN(tc, n) \ |
(_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ |
+ 4 * (n)) /* n: 0...7 */ |
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#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138) |
#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938) |
#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) |
#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) |
#define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) |
#define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ |
_MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) |
#define READ_DATA_VALID(n) (1 << (n)) |
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/* For UMS only (deprecated): */ |
#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) |
#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) |
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#endif /* _I915_REG_H_ */ |