35,6 → 35,9 |
#include "i915_trace.h" |
#include "intel_drv.h" |
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#define DRM_WAKEUP( queue ) wake_up( queue ) |
#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) |
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#define MAX_NOPID ((u32)~0) |
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/** |
84,9 → 87,30 |
POSTING_READ(DEIMR); |
} |
} |
static void notify_ring(struct drm_device *dev, |
struct intel_ring_buffer *ring) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 seqno; |
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if (ring->obj == NULL) |
return; |
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seqno = ring->get_seqno(ring); |
trace_i915_gem_request_complete(ring, seqno); |
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ring->irq_seqno = seqno; |
wake_up_all(&ring->irq_queue); |
// if (i915_enable_hangcheck) { |
// dev_priv->hangcheck_count = 0; |
// mod_timer(&dev_priv->hangcheck_timer, |
// jiffies + |
// msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
// } |
} |
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|
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static int ironlake_irq_handler(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
123,12 → 147,12 |
ret = IRQ_HANDLED; |
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// if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
// notify_ring(dev, &dev_priv->ring[RCS]); |
// if (gt_iir & bsd_usr_interrupt) |
// notify_ring(dev, &dev_priv->ring[VCS]); |
// if (gt_iir & GT_BLT_USER_INTERRUPT) |
// notify_ring(dev, &dev_priv->ring[BCS]); |
if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
notify_ring(dev, &dev_priv->ring[RCS]); |
if (gt_iir & bsd_usr_interrupt) |
notify_ring(dev, &dev_priv->ring[VCS]); |
if (gt_iir & GT_BLT_USER_INTERRUPT) |
notify_ring(dev, &dev_priv->ring[BCS]); |
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// if (de_iir & DE_GSE) |
// intel_opregion_gse_intr(dev); |
275,11 → 299,11 |
u32 render_irqs; |
u32 hotplug_mask; |
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// DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
// if (HAS_BSD(dev)) |
// DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); |
// if (HAS_BLT(dev)) |
// DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); |
DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
if (HAS_BSD(dev)) |
DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); |
if (HAS_BLT(dev)) |
DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); |
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
dev_priv->irq_mask = ~display_mask; |