| 246,6 → 246,8 |
|---|
| u32 handle; |
| |
| size = roundup(size, PAGE_SIZE); |
| if (size == 0) |
| return -EINVAL; |
| |
| /* Allocate the new object */ |
| obj = i915_gem_alloc_object(dev, size); |
| 1565,13 → 1567,6 |
|---|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| size_t size) |
| { |
| 1593,7 → 1588,7 |
|---|
| obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| |
| if (IS_GEN6(dev)) { |
| if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| /* On Gen6, we can have the GPU use the LLC (the CPU |
| * cache) for about a 10% performance improvement |
| * compared to uncached. Graphics requests other than |
| 1787,7 → 1782,7 |
|---|
| INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
| for (i = 0; i < I915_NUM_RINGS; i++) |
| init_ring_lists(&dev_priv->ring[i]); |
| for (i = 0; i < 16; i++) |
| for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
| INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
| // INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| // i915_gem_retire_work_handler); |