35,9 → 35,6 |
static bool intel_enable_gtt(void); |
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#define PG_SW 0x003 |
#define PG_NOCACHE 0x018 |
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#define PCI_VENDOR_ID_INTEL 0x8086 |
#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 |
#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 |
49,43 → 46,7 |
#define AGP_USER_MEMORY (AGP_USER_TYPES) |
#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1) |
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static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
{ |
return *(const volatile uint8_t __force *) addr; |
} |
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static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
{ |
return *(const volatile uint16_t __force *) addr; |
} |
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static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
{ |
return *(const volatile uint32_t __force *) addr; |
} |
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#define readb __raw_readb |
#define readw __raw_readw |
#define readl __raw_readl |
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static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
{ *(volatile uint8_t __force *) addr = b;} |
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static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
{ *(volatile uint16_t __force *) addr = b;} |
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static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
{ *(volatile uint32_t __force *) addr = b;} |
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static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
{ *(volatile __u64 *)addr = b;} |
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#define writeb __raw_writeb |
#define writew __raw_writew |
#define writel __raw_writel |
#define writeq __raw_writeq |
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static inline int pci_read_config_word(struct pci_dev *dev, int where, |
u16 *val) |
{ |
800,3 → 761,8 |
return 1; |
} |
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const struct intel_gtt *intel_gtt_get(void) |
{ |
return &intel_private.base; |
} |
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