| 64,6 → 64,7 |
|---|
| #define I830_PTE_SYSTEM_CACHED 0x00000006 |
| /* GT PTE cache control fields */ |
| #define GEN6_PTE_UNCACHED 0x00000002 |
| #define HSW_PTE_UNCACHED 0x00000000 |
| #define GEN6_PTE_LLC 0x00000004 |
| #define GEN6_PTE_LLC_MLC 0x00000006 |
| #define GEN6_PTE_GFDT 0x00000008 |
| 96,6 → 97,7 |
|---|
| #define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) |
| |
| #define GFX_FLSH_CNTL 0x2170 /* 915+ */ |
| #define GFX_FLSH_CNTL_VLV 0x101008 |
| |
| #define I810_DRAM_CTL 0x3000 |
| #define I810_DRAM_ROW_0 0x00000001 |
| 211,6 → 213,7 |
|---|
| #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
| #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 |
| #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 |
| #define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069 |
| #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 |
| #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 |
| #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 |
| 234,8 → 237,48 |
|---|
| #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166 |
| #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */ |
| #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A |
| #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A |
| #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */ |
| #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */ |
| #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG 0x0422 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */ |
| #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG 0x0426 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */ |
| #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a |
| #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a |
| #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG 0x042a |
| #define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG 0x0C02 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG 0x0C12 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG 0x0C22 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG 0x0C06 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG 0x0C16 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG 0x0C26 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG 0x0C0A |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG 0x0C1A |
| #define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG 0x0C2A |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG 0x0A02 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG 0x0A12 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG 0x0A22 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG 0x0A06 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG 0x0A16 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG 0x0A26 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG 0x0A0A |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG 0x0A1A |
| #define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG 0x0A2A |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG 0x0D12 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG 0x0D22 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG 0x0D32 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG 0x0D16 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG 0x0D26 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG 0x0D36 |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG 0x0D1A |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG 0x0D2A |
| #define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG 0x0D3A |
| |
| int intel_gmch_probe(struct pci_dev *pdev, |
| struct agp_bridge_data *bridge); |
| void intel_gmch_remove(struct pci_dev *pdev); |
| #endif |