| /drivers/video/Intel-2D/gen4_render.c |
|---|
| 2391,11 → 2391,11 |
| // tmp->mask.offset[0] = -dst_x; |
| // tmp->mask.offset[1] = -dst_y; |
| tmp->u.gen4.wm_kernel = |
| gen4_choose_composite_kernel(tmp->op, |
| tmp->mask.bo != NULL, |
| tmp->has_component_alpha, |
| tmp->is_affine); |
| tmp->u.gen4.wm_kernel = WM_KERNEL_MASK; |
| // gen4_choose_composite_kernel(tmp->op, |
| // tmp->mask.bo != NULL, |
| // tmp->has_component_alpha, |
| // tmp->is_affine); |
| tmp->u.gen4.ve_id = gen4_choose_composite_emitter(sna, tmp); |
| tmp->blt = gen4_render_composite_blt; |
| /drivers/video/Intel-2D/gen5_render.c |
|---|
| 302,6 → 302,8 |
| static uint32_t gen5_get_dest_format(PictFormat format) |
| { |
| return GEN5_SURFACEFORMAT_B8G8R8A8_UNORM; |
| #if 0 |
| switch (format) { |
| default: |
| return -1; |
| 325,6 → 327,7 |
| case PICT_x4r4g4b4: |
| return GEN5_SURFACEFORMAT_B4G4R4A4_UNORM; |
| } |
| #endif |
| } |
| typedef struct gen5_surface_state_padded { |
| struct gen5_surface_state state; |
| 2447,11 → 2450,12 |
| tmp->mask.scale[1] = 1.f/mask->drawable.height; |
| tmp->u.gen5.wm_kernel = |
| gen5_choose_composite_kernel(tmp->op, |
| tmp->mask.bo != NULL, |
| tmp->has_component_alpha, |
| tmp->is_affine); |
| tmp->u.gen5.wm_kernel = WM_KERNEL_MASK; |
| // gen5_choose_composite_kernel(tmp->op, |
| // tmp->mask.bo != NULL, |
| // tmp->has_component_alpha, |
| // tmp->is_affine); |
| tmp->u.gen5.ve_id = gen4_choose_composite_emitter(sna, tmp); |
| tmp->blt = gen5_render_composite_blt; |
| /drivers/video/Intel-2D/gen6_render.c |
|---|
| 2727,9 → 2727,7 |
| op->done = gen6_render_copy_done; |
| return true; |
| } |
| #endif |
| #if 0 |
| static void |
| gen6_emit_fill_state(struct sna *sna, const struct sna_composite_op *op) |
| { |
| /drivers/video/Intel-2D/kgem.c |
|---|
| 5326,7 → 5326,7 |
| bo->domain = DOMAIN_GTT; |
| bo->unique_id = kgem_get_unique_id(kgem); |
| bo->pitch = fb->pitch; |
| bo->tiling = I915_TILING_NONE; |
| bo->tiling = I915_TILING_X; |
| bo->scanout = 1; |
| fb->fb_bo = bo; |