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/drivers/pci.inc
1,6 → 1,6
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;; ;;
;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;;
;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License ;;
;; ;;
;; GNU GENERAL PUBLIC LICENSE ;;
8,125 → 8,163
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
struct PCI_header
 
; PCI Bus defines
vendor_id dw ? ; 0x00
device_id dw ? ; 0x02
command dw ? ; 0x04
status dw ? ; 0x06
revision_id db ? ; 0x08
prog_if db ? ; 0x09
subclass db ? ; 0x0A
class_code db ? ; 0x0B
cache_line_size db ? ; 0x0C
latency_timer db ? ; 0x0D
header_type db ? ; 0x0E
bist db ? ; 0x0F
 
PCI_HEADER_TYPE = 0x0e ; 8 bit
PCI_BASE_ADDRESS_0 = 0x10 ; 32 bit
PCI_BASE_ADDRESS_1 = 0x14 ; 32 bits
PCI_BASE_ADDRESS_2 = 0x18 ; 32 bits
PCI_BASE_ADDRESS_3 = 0x1c ; 32 bits
PCI_BASE_ADDRESS_4 = 0x20 ; 32 bits
PCI_BASE_ADDRESS_5 = 0x24 ; 32 bits
ends
 
struct PCI_header00 PCI_header
 
base_addr_0 dd ? ; 0x10
base_addr_1 dd ? ; 0x14
base_addr_2 dd ? ; 0x18
base_addr_3 dd ? ; 0x1C
base_addr_4 dd ? ; 0x20
base_addr_5 dd ? ; 0x24
cardbus_cis_ptr dd ? ; 0x28
subsys_vendor dw ? ; 0x2C
subsys_id dw ? ; 0x2E
exp_rom_addr dd ? ; 0x30
cap_ptr db ? ; 0x34
rb 7 ; reserved
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3D
min_grant db ? ; 0x3E
max_latency db ? ; 0x3F
 
ends
 
struct PCI_header01 PCI_header
 
base_addr_0 dd ? ; 0x10
base_addr_1 dd ? ; 0x14
prim_bus_nr db ? ; 0x18
sec_bus_nr db ? ; 0x19
sub_bus_nr db ? ; 0x1A
sec_lat_tmr db ? ; 0x1B
io_base db ? ; 0x1C
io_limit db ? ; 0x1D
sec_status dw ? ; 0x1E
mem_base dw ? ; 0x20
mem_limit dw ? ; 0x22
pref_mem_base dw ? ; 0x24
pref_mem_limit dw ? ; 0x26
pref_base_up dd ? ; 0x28
pref_limit_up dd ? ; 0x2C
io_base_up dw ? ; 0x30
io_limit_up dw ? ; 0x32
cap_ptr db ? ; 0x34
rb 3 ; reserved
exp_rom_addr dd ? ; 0x38
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3E
bridge_ctrl dw ? ; 0x3F
 
ends
 
struct PCI_header02 PCI_header
 
base_addr dd ? ; 0x10
cap_list_offs db ? ; 0x14
rb 1 ; reserved
sec_stat dw ? ; 0x16
pci_bus_nr db ? ; 0x18
cardbus_bus_nr db ? ; 0x19
sub_bus_nr db ? ; 0x1A
cardbus_lat_tmr db ? ; 0x1B
mbar_0 dd ? ; 0x1C
mlimit_0 dd ? ; 0x20
mbar_1 dd ? ; 0x24
mlimit_1 dd ? ; 0x28
iobar_0 dd ? ; 0x2C
iolimit_0 dd ? ; 0x30
iobar_1 dd ? ; 0x34
iolimit_1 dd ? ; 0x38
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3D
bridge_ctrl dw ? ; 0x3E
subs_did dw ? ; 0x40
subs_vid dw ? ; 0x42
legacy_bar dd ? ; 0x44
 
ends
 
; Base address bits
PCI_BASE_ADDRESS_SPACE_IO = 0x01
PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC
PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0
 
; PCI programming
; command bits
PCI_CMD_PIO = 0x01 ; bit0: io space control
PCI_CMD_MMIO = 0x02 ; bit1: memory space control
PCI_CMD_MASTER = 0x04 ; bit2: device acts as a PCI master
 
PCI_VENDOR_ID = 0x00 ; 16 bit
PCI_DEVICE_ID = 0x02 ; 16 bits
PCI_REG_COMMAND = 0x4 ; command register
PCI_REG_STATUS = 0x6 ; status register
PCI_REVISION_ID = 0x08 ; 8 bits
PCI_REG_LATENCY = 0xd ; latency timer register
PCI_REG_CAP_PTR = 0x34 ; capabilities pointer
PCI_REG_IRQ = 0x3c
PCI_REG_CAPABILITY_ID = 0x0 ; capapility ID in pm register block
PCI_REG_PM_STATUS = 0x4 ; power management status register
PCI_REG_PM_CTRL = 0x4 ; power management control register
PCI_BIT_PIO = 1 ; bit0: io space control
PCI_BIT_MMIO = 2 ; bit1: memory space control
PCI_BIT_MASTER = 4 ; bit2: device acts as a PCI master
; status bits
PCI_STATUS_CAPA = 0x10 ; bit4: new capabilities available
 
 
macro PCI_find_io {
if used PCI_find_io
proc PCI_find_io stdcall bus, dev
 
local .check, .inc, .got
 
push esi
xor eax, eax
mov esi, PCI_BASE_ADDRESS_0
mov esi, PCI_header00.base_addr_0
.check:
stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi
 
invoke PciRead32, [bus], [dev], esi
test eax, PCI_BASE_ADDRESS_IO_MASK
jz .inc
 
test eax, PCI_BASE_ADDRESS_SPACE_IO
jz .inc
 
and eax, PCI_BASE_ADDRESS_IO_MASK
jmp .got
pop esi
ret
 
.inc:
add esi, 4
cmp esi, PCI_BASE_ADDRESS_5
cmp esi, PCI_header00.base_addr_5
jbe .check
pop esi
xor eax, eax
ret
 
.got:
mov [device.io_addr], eax
endp
end if
 
}
 
if used PCI_find_mmio32
proc PCI_find_mmio32 stdcall bus, dev
 
macro PCI_find_mmio32 {
 
local .check, .inc, .got
 
mov esi, PCI_BASE_ADDRESS_0
push esi
mov esi, PCI_header00.base_addr_0
.check:
stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi
 
invoke PciRead32, [bus], [dev], esi
test eax, PCI_BASE_ADDRESS_SPACE_IO ; mmio address?
jnz .inc
 
test eax, 100b ; 64 bit?
jnz .inc
and eax, not 1111b
jmp .got
pop esi
ret
 
.inc:
add esi, 4
cmp esi, PCI_BASE_ADDRESS_5
cmp esi, PCI_header00.base_addr_5
jbe .check
xor eax, eax
pop esi
ret
 
.got:
mov [device.mmio_addr], eax
}
 
macro PCI_find_irq {
 
stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_IRQ
mov [device.irq_line], al
 
}
 
macro PCI_find_rev {
 
stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REVISION_ID
mov [device.revision], al
 
}
 
macro PCI_make_bus_master bus, dev {
 
stdcall PciRead32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND
or al, PCI_BIT_MASTER
stdcall PciWrite32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND, eax
 
}
 
macro PCI_adjust_latency min {
 
local .not
 
stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY
cmp al, min
ja .not
mov al, min
stdcall PciWrite8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY, eax
.not:
 
}
endp
end if
Property changes:
Deleted: svn:eol-style
-native
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