/drivers/include/uapi/asm/e820.h |
---|
32,7 → 32,18 |
#define E820_ACPI 3 |
#define E820_NVS 4 |
#define E820_UNUSABLE 5 |
#define E820_PMEM 7 |
/* |
* This is a non-standardized way to represent ADR or NVDIMM regions that |
* persist over a reboot. The kernel will ignore their special capabilities |
* unless the CONFIG_X86_PMEM_LEGACY option is set. |
* |
* ( Note that older platforms also used 6 for the same type of memory, |
* but newer versions switched to 12 as 6 was assigned differently. Some |
* time they will learn... ) |
*/ |
#define E820_PRAM 12 |
/* |
* reserved RAM used by kernel itself |
/drivers/include/uapi/asm/msr.h |
---|
1,8 → 1,6 |
#ifndef _UAPI_ASM_X86_MSR_H |
#define _UAPI_ASM_X86_MSR_H |
#include <asm/msr-index.h> |
#ifndef __ASSEMBLY__ |
#include <linux/types.h> |
/drivers/include/uapi/asm/posix_types.h |
---|
1,5 → 1,9 |
# ifdef CONFIG_X86_32 |
#ifndef __KERNEL__ |
# ifdef __i386__ |
# include <asm/posix_types_32.h> |
# elif defined(__ILP32__) |
# include <asm/posix_types_x32.h> |
# else |
# include <asm/posix_types_64.h> |
# endif |
#endif |
/drivers/include/uapi/asm/processor-flags.h |
---|
37,8 → 37,6 |
#define X86_EFLAGS_VM _BITUL(X86_EFLAGS_VM_BIT) |
#define X86_EFLAGS_AC_BIT 18 /* Alignment Check/Access Control */ |
#define X86_EFLAGS_AC _BITUL(X86_EFLAGS_AC_BIT) |
#define X86_EFLAGS_AC_BIT 18 /* Alignment Check/Access Control */ |
#define X86_EFLAGS_AC _BITUL(X86_EFLAGS_AC_BIT) |
#define X86_EFLAGS_VIF_BIT 19 /* Virtual Interrupt Flag */ |
#define X86_EFLAGS_VIF _BITUL(X86_EFLAGS_VIF_BIT) |
#define X86_EFLAGS_VIP_BIT 20 /* Virtual Interrupt Pending */ |
/drivers/include/uapi/asm/ptrace-abi.h |
---|
0,0 → 1,93 |
#ifndef _ASM_X86_PTRACE_ABI_H |
#define _ASM_X86_PTRACE_ABI_H |
#ifdef __i386__ |
#define EBX 0 |
#define ECX 1 |
#define EDX 2 |
#define ESI 3 |
#define EDI 4 |
#define EBP 5 |
#define EAX 6 |
#define DS 7 |
#define ES 8 |
#define FS 9 |
#define GS 10 |
#define ORIG_EAX 11 |
#define EIP 12 |
#define CS 13 |
#define EFL 14 |
#define UESP 15 |
#define SS 16 |
#define FRAME_SIZE 17 |
#else /* __i386__ */ |
#if defined(__ASSEMBLY__) || defined(__FRAME_OFFSETS) |
/* |
* C ABI says these regs are callee-preserved. They aren't saved on kernel entry |
* unless syscall needs a complete, fully filled "struct pt_regs". |
*/ |
#define R15 0 |
#define R14 8 |
#define R13 16 |
#define R12 24 |
#define RBP 32 |
#define RBX 40 |
/* These regs are callee-clobbered. Always saved on kernel entry. */ |
#define R11 48 |
#define R10 56 |
#define R9 64 |
#define R8 72 |
#define RAX 80 |
#define RCX 88 |
#define RDX 96 |
#define RSI 104 |
#define RDI 112 |
/* |
* On syscall entry, this is syscall#. On CPU exception, this is error code. |
* On hw interrupt, it's IRQ number: |
*/ |
#define ORIG_RAX 120 |
/* Return frame for iretq */ |
#define RIP 128 |
#define CS 136 |
#define EFLAGS 144 |
#define RSP 152 |
#define SS 160 |
#endif /* __ASSEMBLY__ */ |
/* top of stack page */ |
#define FRAME_SIZE 168 |
#endif /* !__i386__ */ |
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ |
#define PTRACE_GETREGS 12 |
#define PTRACE_SETREGS 13 |
#define PTRACE_GETFPREGS 14 |
#define PTRACE_SETFPREGS 15 |
#define PTRACE_GETFPXREGS 18 |
#define PTRACE_SETFPXREGS 19 |
#define PTRACE_OLDSETOPTIONS 21 |
/* only useful for access 32bit programs / kernels */ |
#define PTRACE_GET_THREAD_AREA 25 |
#define PTRACE_SET_THREAD_AREA 26 |
#ifdef __x86_64__ |
# define PTRACE_ARCH_PRCTL 30 |
#endif |
#define PTRACE_SYSEMU 31 |
#define PTRACE_SYSEMU_SINGLESTEP 32 |
#define PTRACE_SINGLEBLOCK 33 /* resume execution until next branch */ |
#ifndef __ASSEMBLY__ |
#include <linux/types.h> |
#endif |
#endif /* _ASM_X86_PTRACE_ABI_H */ |
/drivers/include/uapi/asm/ptrace.h |
---|
1,262 → 1,85 |
#ifndef _ASM_X86_PTRACE_H |
#define _ASM_X86_PTRACE_H |
#ifndef _UAPI_ASM_X86_PTRACE_H |
#define _UAPI_ASM_X86_PTRACE_H |
#include <asm/segment.h> |
#include <asm/page_types.h> |
#include <uapi/asm/ptrace.h> |
#include <linux/compiler.h> /* For __user */ |
#include <asm/ptrace-abi.h> |
#include <asm/processor-flags.h> |
#ifndef __ASSEMBLY__ |
#ifdef __i386__ |
/* this struct defines the way the registers are stored on the |
stack during a system call. */ |
#ifndef __KERNEL__ |
struct pt_regs { |
unsigned long bx; |
unsigned long cx; |
unsigned long dx; |
unsigned long si; |
unsigned long di; |
unsigned long bp; |
unsigned long ax; |
unsigned long ds; |
unsigned long es; |
unsigned long fs; |
unsigned long gs; |
unsigned long orig_ax; |
unsigned long ip; |
unsigned long cs; |
unsigned long flags; |
unsigned long sp; |
unsigned long ss; |
long ebx; |
long ecx; |
long edx; |
long esi; |
long edi; |
long ebp; |
long eax; |
int xds; |
int xes; |
int xfs; |
int xgs; |
long orig_eax; |
long eip; |
int xcs; |
long eflags; |
long esp; |
int xss; |
}; |
#endif /* __KERNEL__ */ |
#else /* __i386__ */ |
#ifndef __KERNEL__ |
struct pt_regs { |
/* |
* C ABI says these regs are callee-preserved. They aren't saved on kernel entry |
* unless syscall needs a complete, fully filled "struct pt_regs". |
*/ |
unsigned long r15; |
unsigned long r14; |
unsigned long r13; |
unsigned long r12; |
unsigned long bp; |
unsigned long bx; |
/* arguments: non interrupts/non tracing syscalls only save up to here*/ |
unsigned long rbp; |
unsigned long rbx; |
/* These regs are callee-clobbered. Always saved on kernel entry. */ |
unsigned long r11; |
unsigned long r10; |
unsigned long r9; |
unsigned long r8; |
unsigned long ax; |
unsigned long cx; |
unsigned long dx; |
unsigned long si; |
unsigned long di; |
unsigned long orig_ax; |
/* end of arguments */ |
/* cpu exception frame or undefined */ |
unsigned long ip; |
unsigned long rax; |
unsigned long rcx; |
unsigned long rdx; |
unsigned long rsi; |
unsigned long rdi; |
/* |
* On syscall entry, this is syscall#. On CPU exception, this is error code. |
* On hw interrupt, it's IRQ number: |
*/ |
unsigned long orig_rax; |
/* Return frame for iretq */ |
unsigned long rip; |
unsigned long cs; |
unsigned long flags; |
unsigned long sp; |
unsigned long eflags; |
unsigned long rsp; |
unsigned long ss; |
/* top of stack page */ |
}; |
#endif /* __KERNEL__ */ |
#endif /* !__i386__ */ |
#ifdef CONFIG_PARAVIRT |
#include <asm/paravirt_types.h> |
#endif |
struct cpuinfo_x86; |
struct task_struct; |
extern unsigned long profile_pc(struct pt_regs *regs); |
#define profile_pc profile_pc |
#endif /* !__ASSEMBLY__ */ |
extern unsigned long |
convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs); |
extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, |
int error_code, int si_code); |
extern unsigned long syscall_trace_enter_phase1(struct pt_regs *, u32 arch); |
extern long syscall_trace_enter_phase2(struct pt_regs *, u32 arch, |
unsigned long phase1_result); |
extern long syscall_trace_enter(struct pt_regs *); |
extern void syscall_trace_leave(struct pt_regs *); |
static inline unsigned long regs_return_value(struct pt_regs *regs) |
{ |
return regs->ax; |
} |
/* |
* user_mode_vm(regs) determines whether a register set came from user mode. |
* This is true if V8086 mode was enabled OR if the register set was from |
* protected mode with RPL-3 CS value. This tricky test checks that with |
* one comparison. Many places in the kernel can bypass this full check |
* if they have already ruled out V8086 mode, so user_mode(regs) can be used. |
*/ |
static inline int user_mode(struct pt_regs *regs) |
{ |
#ifdef CONFIG_X86_32 |
return (regs->cs & SEGMENT_RPL_MASK) == USER_RPL; |
#else |
return !!(regs->cs & 3); |
#endif |
} |
static inline int user_mode_vm(struct pt_regs *regs) |
{ |
#ifdef CONFIG_X86_32 |
return ((regs->cs & SEGMENT_RPL_MASK) | (regs->flags & X86_VM_MASK)) >= |
USER_RPL; |
#else |
return user_mode(regs); |
#endif |
} |
static inline int v8086_mode(struct pt_regs *regs) |
{ |
#ifdef CONFIG_X86_32 |
return (regs->flags & X86_VM_MASK); |
#else |
return 0; /* No V86 mode support in long mode */ |
#endif |
} |
#ifdef CONFIG_X86_64 |
static inline bool user_64bit_mode(struct pt_regs *regs) |
{ |
#ifndef CONFIG_PARAVIRT |
/* |
* On non-paravirt systems, this is the only long mode CPL 3 |
* selector. We do not allow long mode selectors in the LDT. |
*/ |
return regs->cs == __USER_CS; |
#else |
/* Headers are too twisted for this to go in paravirt.h. */ |
return regs->cs == __USER_CS || regs->cs == pv_info.extra_user_64bit_cs; |
#endif |
} |
#define current_user_stack_pointer() this_cpu_read(old_rsp) |
/* ia32 vs. x32 difference */ |
#define compat_user_stack_pointer() \ |
(test_thread_flag(TIF_IA32) \ |
? current_pt_regs()->sp \ |
: this_cpu_read(old_rsp)) |
#endif |
#ifdef CONFIG_X86_32 |
extern unsigned long kernel_stack_pointer(struct pt_regs *regs); |
#else |
static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) |
{ |
return regs->sp; |
} |
#endif |
#define GET_IP(regs) ((regs)->ip) |
#define GET_FP(regs) ((regs)->bp) |
#define GET_USP(regs) ((regs)->sp) |
#include <asm-generic/ptrace.h> |
/* Query offset/name of register from its name/offset */ |
extern int regs_query_register_offset(const char *name); |
extern const char *regs_query_register_name(unsigned int offset); |
#define MAX_REG_OFFSET (offsetof(struct pt_regs, ss)) |
/** |
* regs_get_register() - get register value from its offset |
* @regs: pt_regs from which register value is gotten. |
* @offset: offset number of the register. |
* |
* regs_get_register returns the value of a register. The @offset is the |
* offset of the register in struct pt_regs address which specified by @regs. |
* If @offset is bigger than MAX_REG_OFFSET, this returns 0. |
*/ |
static inline unsigned long regs_get_register(struct pt_regs *regs, |
unsigned int offset) |
{ |
if (unlikely(offset > MAX_REG_OFFSET)) |
return 0; |
#ifdef CONFIG_X86_32 |
/* |
* Traps from the kernel do not save sp and ss. |
* Use the helper function to retrieve sp. |
*/ |
if (offset == offsetof(struct pt_regs, sp) && |
regs->cs == __KERNEL_CS) |
return kernel_stack_pointer(regs); |
#endif |
return *(unsigned long *)((unsigned long)regs + offset); |
} |
/** |
* regs_within_kernel_stack() - check the address in the stack |
* @regs: pt_regs which contains kernel stack pointer. |
* @addr: address which is checked. |
* |
* regs_within_kernel_stack() checks @addr is within the kernel stack page(s). |
* If @addr is within the kernel stack, it returns true. If not, returns false. |
*/ |
static inline int regs_within_kernel_stack(struct pt_regs *regs, |
unsigned long addr) |
{ |
return ((addr & ~(THREAD_SIZE - 1)) == |
(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); |
} |
/** |
* regs_get_kernel_stack_nth() - get Nth entry of the stack |
* @regs: pt_regs which contains kernel stack pointer. |
* @n: stack entry number. |
* |
* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which |
* is specified by @regs. If the @n th entry is NOT in the kernel stack, |
* this returns 0. |
*/ |
static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, |
unsigned int n) |
{ |
unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); |
addr += n; |
if (regs_within_kernel_stack(regs, (unsigned long)addr)) |
return *addr; |
else |
return 0; |
} |
#define arch_has_single_step() (1) |
#ifdef CONFIG_X86_DEBUGCTLMSR |
#define arch_has_block_step() (1) |
#else |
#define arch_has_block_step() (boot_cpu_data.x86 >= 6) |
#endif |
#define ARCH_HAS_USER_SINGLE_STEP_INFO |
/* |
* When hitting ptrace_stop(), we cannot return using SYSRET because |
* that does not restore the full CPU state, only a minimal set. The |
* ptracer can change arbitrary register values, which is usually okay |
* because the usual ptrace stops run off the signal delivery path which |
* forces IRET; however, ptrace_event() stops happen in arbitrary places |
* in the kernel and don't force IRET path. |
* |
* So force IRET path after a ptrace stop. |
*/ |
#define arch_ptrace_stop_needed(code, info) \ |
({ \ |
set_thread_flag(TIF_NOTIFY_RESUME); \ |
false; \ |
}) |
struct user_desc; |
extern int do_get_thread_area(struct task_struct *p, int idx, |
struct user_desc __user *info); |
extern int do_set_thread_area(struct task_struct *p, int idx, |
struct user_desc __user *info, int can_allocate); |
#endif /* !__ASSEMBLY__ */ |
#endif /* _ASM_X86_PTRACE_H */ |
#endif /* _UAPI_ASM_X86_PTRACE_H */ |
/drivers/include/uapi/asm/sigcontext.h |
---|
1,6 → 1,19 |
#ifndef _UAPI_ASM_X86_SIGCONTEXT_H |
#define _UAPI_ASM_X86_SIGCONTEXT_H |
/* |
* Linux signal context definitions. The sigcontext includes a complex |
* hierarchy of CPU and FPU state, available to user-space (on the stack) when |
* a signal handler is executed. |
* |
* As over the years this ABI grew from its very simple roots towards |
* supporting more and more CPU state organically, some of the details (which |
* were rather clever hacks back in the days) became a bit quirky by today. |
* |
* The current ABI includes flexible provisions for future extensions, so we |
* won't have to grow new quirks for quite some time. Promise! |
*/ |
#include <linux/compiler.h> |
#include <linux/types.h> |
9,155 → 22,306 |
#define FP_XSTATE_MAGIC2_SIZE sizeof(FP_XSTATE_MAGIC2) |
/* |
* bytes 464..511 in the current 512byte layout of fxsave/fxrstor frame |
* are reserved for SW usage. On cpu's supporting xsave/xrstor, these bytes |
* are used to extended the fpstate pointer in the sigcontext, which now |
* includes the extended state information along with fpstate information. |
* Bytes 464..511 in the current 512-byte layout of the FXSAVE/FXRSTOR frame |
* are reserved for SW usage. On CPUs supporting XSAVE/XRSTOR, these bytes are |
* used to extend the fpstate pointer in the sigcontext, which now includes the |
* extended state information along with fpstate information. |
* |
* Presence of FP_XSTATE_MAGIC1 at the beginning of this SW reserved |
* area and FP_XSTATE_MAGIC2 at the end of memory layout |
* (extended_size - FP_XSTATE_MAGIC2_SIZE) indicates the presence of the |
* extended state information in the memory layout pointed by the fpstate |
* pointer in sigcontext. |
* If sw_reserved.magic1 == FP_XSTATE_MAGIC1 then there's a |
* sw_reserved.extended_size bytes large extended context area present. (The |
* last 32-bit word of this extended area (at the |
* fpstate+extended_size-FP_XSTATE_MAGIC2_SIZE address) is set to |
* FP_XSTATE_MAGIC2 so that you can sanity check your size calculations.) |
* |
* This extended area typically grows with newer CPUs that have larger and |
* larger XSAVE areas. |
*/ |
struct _fpx_sw_bytes { |
__u32 magic1; /* FP_XSTATE_MAGIC1 */ |
__u32 extended_size; /* total size of the layout referred by |
* fpstate pointer in the sigcontext. |
/* |
* If set to FP_XSTATE_MAGIC1 then this is an xstate context. |
* 0 if a legacy frame. |
*/ |
__u64 xstate_bv; |
/* feature bit mask (including fp/sse/extended |
* state) that is present in the memory |
* layout. |
__u32 magic1; |
/* |
* Total size of the fpstate area: |
* |
* - if magic1 == 0 then it's sizeof(struct _fpstate) |
* - if magic1 == FP_XSTATE_MAGIC1 then it's sizeof(struct _xstate) |
* plus extensions (if any) |
*/ |
__u32 xstate_size; /* actual xsave state size, based on the |
* features saved in the layout. |
* 'extended_size' will be greater than |
* 'xstate_size'. |
__u32 extended_size; |
/* |
* Feature bit mask (including FP/SSE/extended state) that is present |
* in the memory layout: |
*/ |
__u32 padding[7]; /* for future use. */ |
__u64 xfeatures; |
/* |
* Actual XSAVE state size, based on the xfeatures saved in the layout. |
* 'extended_size' is greater than 'xstate_size': |
*/ |
__u32 xstate_size; |
/* For future use: */ |
__u32 padding[7]; |
}; |
#ifdef __i386__ |
/* |
* As documented in the iBCS2 standard.. |
* As documented in the iBCS2 standard: |
* |
* The first part of "struct _fpstate" is just the normal i387 |
* hardware setup, the extra "status" word is used to save the |
* coprocessor status word before entering the handler. |
* The first part of "struct _fpstate" is just the normal i387 hardware setup, |
* the extra "status" word is used to save the coprocessor status word before |
* entering the handler. |
* |
* Pentium III FXSR, SSE support |
* Gareth Hughes <gareth@valinux.com>, May 2000 |
* |
* The FPU state data structure has had to grow to accommodate the |
* extended FPU state required by the Streaming SIMD Extensions. |
* There is no documented standard to accomplish this at the moment. |
* The FPU state data structure has had to grow to accommodate the extended FPU |
* state required by the Streaming SIMD Extensions. There is no documented |
* standard to accomplish this at the moment. |
*/ |
/* 10-byte legacy floating point register: */ |
struct _fpreg { |
unsigned short significand[4]; |
unsigned short exponent; |
__u16 significand[4]; |
__u16 exponent; |
}; |
/* 16-byte floating point register: */ |
struct _fpxreg { |
unsigned short significand[4]; |
unsigned short exponent; |
unsigned short padding[3]; |
__u16 significand[4]; |
__u16 exponent; |
__u16 padding[3]; |
}; |
/* 16-byte XMM register: */ |
struct _xmmreg { |
unsigned long element[4]; |
__u32 element[4]; |
}; |
struct _fpstate { |
/* Regular FPU environment */ |
unsigned long cw; |
unsigned long sw; |
unsigned long tag; |
unsigned long ipoff; |
unsigned long cssel; |
unsigned long dataoff; |
unsigned long datasel; |
#define X86_FXSR_MAGIC 0x0000 |
/* |
* The 32-bit FPU frame: |
*/ |
struct _fpstate_32 { |
/* Legacy FPU environment: */ |
__u32 cw; |
__u32 sw; |
__u32 tag; |
__u32 ipoff; |
__u32 cssel; |
__u32 dataoff; |
__u32 datasel; |
struct _fpreg _st[8]; |
unsigned short status; |
unsigned short magic; /* 0xffff = regular FPU data only */ |
__u16 status; |
__u16 magic; /* 0xffff: regular FPU data only */ |
/* 0x0000: FXSR FPU data */ |
/* FXSR FPU environment */ |
unsigned long _fxsr_env[6]; /* FXSR FPU env is ignored */ |
unsigned long mxcsr; |
unsigned long reserved; |
__u32 _fxsr_env[6]; /* FXSR FPU env is ignored */ |
__u32 mxcsr; |
__u32 reserved; |
struct _fpxreg _fxsr_st[8]; /* FXSR FPU reg data is ignored */ |
struct _xmmreg _xmm[8]; |
unsigned long padding1[44]; |
struct _xmmreg _xmm[8]; /* First 8 XMM registers */ |
union { |
__u32 padding1[44]; /* Second 8 XMM registers plus padding */ |
__u32 padding[44]; /* Alias name for old user-space */ |
}; |
union { |
unsigned long padding2[12]; |
struct _fpx_sw_bytes sw_reserved; /* represents the extended |
* state info */ |
__u32 padding2[12]; |
struct _fpx_sw_bytes sw_reserved; /* Potential extended state is encoded here */ |
}; |
}; |
#define X86_FXSR_MAGIC 0x0000 |
#ifndef __KERNEL__ |
/* |
* User-space might still rely on the old definition: |
* The 64-bit FPU frame. (FXSAVE format and later) |
* |
* Note1: If sw_reserved.magic1 == FP_XSTATE_MAGIC1 then the structure is |
* larger: 'struct _xstate'. Note that 'struct _xstate' embedds |
* 'struct _fpstate' so that you can always assume the _fpstate portion |
* exists so that you can check the magic value. |
* |
* Note2: Reserved fields may someday contain valuable data. Always |
* save/restore them when you change signal frames. |
*/ |
struct sigcontext { |
unsigned short gs, __gsh; |
unsigned short fs, __fsh; |
unsigned short es, __esh; |
unsigned short ds, __dsh; |
unsigned long edi; |
unsigned long esi; |
unsigned long ebp; |
unsigned long esp; |
unsigned long ebx; |
unsigned long edx; |
unsigned long ecx; |
unsigned long eax; |
unsigned long trapno; |
unsigned long err; |
unsigned long eip; |
unsigned short cs, __csh; |
unsigned long eflags; |
unsigned long esp_at_signal; |
unsigned short ss, __ssh; |
struct _fpstate __user *fpstate; |
unsigned long oldmask; |
unsigned long cr2; |
}; |
#endif /* !__KERNEL__ */ |
#else /* __i386__ */ |
/* FXSAVE frame */ |
/* Note: reserved1/2 may someday contain valuable data. Always save/restore |
them when you change signal frames. */ |
struct _fpstate { |
struct _fpstate_64 { |
__u16 cwd; |
__u16 swd; |
__u16 twd; /* Note this is not the same as the |
32bit/x87/FSAVE twd */ |
/* Note this is not the same as the 32-bit/x87/FSAVE twd: */ |
__u16 twd; |
__u16 fop; |
__u64 rip; |
__u64 rdp; |
__u32 mxcsr; |
__u32 mxcsr_mask; |
__u32 st_space[32]; /* 8*16 bytes for each FP-reg */ |
__u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg */ |
__u32 st_space[32]; /* 8x FP registers, 16 bytes each */ |
__u32 xmm_space[64]; /* 16x XMM registers, 16 bytes each */ |
__u32 reserved2[12]; |
union { |
__u32 reserved3[12]; |
struct _fpx_sw_bytes sw_reserved; /* represents the extended |
* state information */ |
struct _fpx_sw_bytes sw_reserved; /* Potential extended state is encoded here */ |
}; |
}; |
#ifndef __KERNEL__ |
#ifdef __i386__ |
# define _fpstate _fpstate_32 |
#else |
# define _fpstate _fpstate_64 |
#endif |
struct _header { |
__u64 xfeatures; |
__u64 reserved1[2]; |
__u64 reserved2[5]; |
}; |
struct _ymmh_state { |
/* 16x YMM registers, 16 bytes each: */ |
__u32 ymmh_space[64]; |
}; |
/* |
* User-space might still rely on the old definition: |
* Extended state pointed to by sigcontext::fpstate. |
* |
* In addition to the fpstate, information encoded in _xstate::xstate_hdr |
* indicates the presence of other extended state information supported |
* by the CPU and kernel: |
*/ |
struct _xstate { |
struct _fpstate fpstate; |
struct _header xstate_hdr; |
struct _ymmh_state ymmh; |
/* New processor state extensions go here: */ |
}; |
/* |
* The 32-bit signal frame: |
*/ |
struct sigcontext_32 { |
__u16 gs, __gsh; |
__u16 fs, __fsh; |
__u16 es, __esh; |
__u16 ds, __dsh; |
__u32 di; |
__u32 si; |
__u32 bp; |
__u32 sp; |
__u32 bx; |
__u32 dx; |
__u32 cx; |
__u32 ax; |
__u32 trapno; |
__u32 err; |
__u32 ip; |
__u16 cs, __csh; |
__u32 flags; |
__u32 sp_at_signal; |
__u16 ss, __ssh; |
/* |
* fpstate is really (struct _fpstate *) or (struct _xstate *) |
* depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved |
* bytes of (struct _fpstate) and FP_XSTATE_MAGIC2 present at the end |
* of extended memory layout. See comments at the definition of |
* (struct _fpx_sw_bytes) |
*/ |
__u32 fpstate; /* Zero when no FPU/extended context */ |
__u32 oldmask; |
__u32 cr2; |
}; |
/* |
* The 64-bit signal frame: |
*/ |
struct sigcontext_64 { |
__u64 r8; |
__u64 r9; |
__u64 r10; |
__u64 r11; |
__u64 r12; |
__u64 r13; |
__u64 r14; |
__u64 r15; |
__u64 di; |
__u64 si; |
__u64 bp; |
__u64 bx; |
__u64 dx; |
__u64 ax; |
__u64 cx; |
__u64 sp; |
__u64 ip; |
__u64 flags; |
__u16 cs; |
__u16 gs; |
__u16 fs; |
__u16 __pad0; |
__u64 err; |
__u64 trapno; |
__u64 oldmask; |
__u64 cr2; |
/* |
* fpstate is really (struct _fpstate *) or (struct _xstate *) |
* depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved |
* bytes of (struct _fpstate) and FP_XSTATE_MAGIC2 present at the end |
* of extended memory layout. See comments at the definition of |
* (struct _fpx_sw_bytes) |
*/ |
__u64 fpstate; /* Zero when no FPU/extended context */ |
__u64 reserved1[8]; |
}; |
/* |
* Create the real 'struct sigcontext' type: |
*/ |
#ifdef __KERNEL__ |
# ifdef __i386__ |
# define sigcontext sigcontext_32 |
# else |
# define sigcontext sigcontext_64 |
# endif |
#endif |
/* |
* The old user-space sigcontext definition, just in case user-space still |
* relies on it. The kernel definition (in asm/sigcontext.h) has unified |
* field names but otherwise the same layout. |
*/ |
#ifndef __KERNEL__ |
#define _fpstate_ia32 _fpstate_32 |
#define sigcontext_ia32 sigcontext_32 |
# ifdef __i386__ |
struct sigcontext { |
__u16 gs, __gsh; |
__u16 fs, __fsh; |
__u16 es, __esh; |
__u16 ds, __dsh; |
__u32 edi; |
__u32 esi; |
__u32 ebp; |
__u32 esp; |
__u32 ebx; |
__u32 edx; |
__u32 ecx; |
__u32 eax; |
__u32 trapno; |
__u32 err; |
__u32 eip; |
__u16 cs, __csh; |
__u32 eflags; |
__u32 esp_at_signal; |
__u16 ss, __ssh; |
struct _fpstate __user *fpstate; |
__u32 oldmask; |
__u32 cr2; |
}; |
# else /* __x86_64__: */ |
struct sigcontext { |
__u64 r8; |
__u64 r9; |
__u64 r10; |
184,38 → 348,13 |
__u64 trapno; |
__u64 oldmask; |
__u64 cr2; |
struct _fpstate __user *fpstate; /* zero when no FPU context */ |
struct _fpstate __user *fpstate; /* Zero when no FPU context */ |
#ifdef __ILP32__ |
__u32 __fpstate_pad; |
#endif |
__u64 reserved1[8]; |
}; |
# endif /* __x86_64__ */ |
#endif /* !__KERNEL__ */ |
#endif /* !__i386__ */ |
struct _xsave_hdr { |
__u64 xstate_bv; |
__u64 reserved1[2]; |
__u64 reserved2[5]; |
}; |
struct _ymmh_state { |
/* 16 * 16 bytes for each YMMH-reg */ |
__u32 ymmh_space[64]; |
}; |
/* |
* Extended state pointed by the fpstate pointer in the sigcontext. |
* In addition to the fpstate, information encoded in the xstate_hdr |
* indicates the presence of other extended state information |
* supported by the processor and OS. |
*/ |
struct _xstate { |
struct _fpstate fpstate; |
struct _xsave_hdr xstate_hdr; |
struct _ymmh_state ymmh; |
/* new processor state extensions go here */ |
}; |
#endif /* _UAPI_ASM_X86_SIGCONTEXT_H */ |
/drivers/include/uapi/asm-generic/errno.h |
---|
6,7 → 6,16 |
#define EDEADLK 35 /* Resource deadlock would occur */ |
#define ENAMETOOLONG 36 /* File name too long */ |
#define ENOLCK 37 /* No record locks available */ |
#define ENOSYS 38 /* Function not implemented */ |
/* |
* This error code is special: arch syscall entry code will return |
* -ENOSYS if users try to call a syscall that doesn't exist. To keep |
* failures of syscalls that really do exist distinguishable from |
* failures due to attempts to use a nonexistent syscall, syscall |
* implementations should refrain from returning -ENOSYS. |
*/ |
#define ENOSYS 38 /* Invalid system call number */ |
#define ENOTEMPTY 39 /* Directory not empty */ |
#define ELOOP 40 /* Too many symbolic links encountered */ |
#define EWOULDBLOCK EAGAIN /* Operation would block */ |
/drivers/include/uapi/drm/drm.h |
---|
630,6 → 630,7 |
*/ |
#define DRM_CAP_CURSOR_WIDTH 0x8 |
#define DRM_CAP_CURSOR_HEIGHT 0x9 |
#define DRM_CAP_ADDFB2_MODIFIERS 0x10 |
/** DRM_IOCTL_GET_CAP ioctl argument type */ |
struct drm_get_cap { |
654,6 → 655,13 |
*/ |
#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 |
/** |
* DRM_CLIENT_CAP_ATOMIC |
* |
* If set to 1, the DRM core will expose atomic properties to userspace |
*/ |
#define DRM_CLIENT_CAP_ATOMIC 3 |
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ |
struct drm_set_client_cap { |
__u64 capability; |
777,6 → 785,9 |
#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) |
#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) |
#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) |
#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) |
#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) |
#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) |
/** |
* Device specific ioctls should only be in their respective headers |
/drivers/include/uapi/drm/drm_fourcc.h |
---|
34,6 → 34,13 |
/* color index */ |
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ |
/* 8 bpp Red */ |
#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ |
/* 16 bpp RG */ |
#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ |
#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ |
/* 8 bpp RGB */ |
#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ |
#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ |
109,9 → 116,6 |
#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ |
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ |
/* special NV12 tiled format */ |
#define DRM_FORMAT_NV12MT fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */ |
/* |
* 3 plane YCbCr |
* index 0: Y plane, [7:0] Y |
132,4 → 136,97 |
#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ |
#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ |
/* |
* Format Modifiers: |
* |
* Format modifiers describe, typically, a re-ordering or modification |
* of the data in a plane of an FB. This can be used to express tiled/ |
* swizzled formats, or compression, or a combination of the two. |
* |
* The upper 8 bits of the format modifier are a vendor-id as assigned |
* below. The lower 56 bits are assigned as vendor sees fit. |
*/ |
/* Vendor Ids: */ |
#define DRM_FORMAT_MOD_NONE 0 |
#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 |
#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 |
#define DRM_FORMAT_MOD_VENDOR_NV 0x03 |
#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 |
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 |
/* add more to the end as needed */ |
#define fourcc_mod_code(vendor, val) \ |
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) |
/* |
* Format Modifier tokens: |
* |
* When adding a new token please document the layout with a code comment, |
* similar to the fourcc codes above. drm_fourcc.h is considered the |
* authoritative source for all of these. |
*/ |
/* Intel framebuffer modifiers */ |
/* |
* Intel X-tiling layout |
* |
* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) |
* in row-major layout. Within the tile bytes are laid out row-major, with |
* a platform-dependent stride. On top of that the memory can apply |
* platform-depending swizzling of some higher address bits into bit6. |
* |
* This format is highly platforms specific and not useful for cross-driver |
* sharing. It exists since on a given platform it does uniquely identify the |
* layout in a simple way for i915-specific userspace. |
*/ |
#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) |
/* |
* Intel Y-tiling layout |
* |
* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) |
* in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) |
* chunks column-major, with a platform-dependent height. On top of that the |
* memory can apply platform-depending swizzling of some higher address bits |
* into bit6. |
* |
* This format is highly platforms specific and not useful for cross-driver |
* sharing. It exists since on a given platform it does uniquely identify the |
* layout in a simple way for i915-specific userspace. |
*/ |
#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) |
/* |
* Intel Yf-tiling layout |
* |
* This is a tiled layout using 4Kb tiles in row-major layout. |
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which |
* are arranged in four groups (two wide, two high) with column-major layout. |
* Each group therefore consits out of four 256 byte units, which are also laid |
* out as 2x2 column-major. |
* 256 byte units are made out of four 64 byte blocks of pixels, producing |
* either a square block or a 2:1 unit. |
* 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width |
* in pixel depends on the pixel depth. |
*/ |
#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) |
/* |
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
* |
* Macroblocks are laid in a Z-shape, and each pixel data is following the |
* standard NV12 style. |
* As for NV12, an image is the result of two frame buffers: one for Y, |
* one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). |
* Alignment requirements are (for each buffer): |
* - multiple of 128 pixels for the width |
* - multiple of 32 pixels for the height |
* |
* For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html |
*/ |
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) |
#endif /* DRM_FOURCC_H */ |
/drivers/include/uapi/drm/drm_mode.h |
---|
105,8 → 105,16 |
struct drm_mode_modeinfo { |
__u32 clock; |
__u16 hdisplay, hsync_start, hsync_end, htotal, hskew; |
__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; |
__u16 hdisplay; |
__u16 hsync_start; |
__u16 hsync_end; |
__u16 htotal; |
__u16 hskew; |
__u16 vdisplay; |
__u16 vsync_start; |
__u16 vsync_end; |
__u16 vtotal; |
__u16 vscan; |
__u32 vrefresh; |
124,8 → 132,10 |
__u32 count_crtcs; |
__u32 count_connectors; |
__u32 count_encoders; |
__u32 min_width, max_width; |
__u32 min_height, max_height; |
__u32 min_width; |
__u32 max_width; |
__u32 min_height; |
__u32 max_height; |
}; |
struct drm_mode_crtc { |
135,7 → 145,8 |
__u32 crtc_id; /**< Id */ |
__u32 fb_id; /**< Id of framebuffer */ |
__u32 x, y; /**< Position on the frameuffer */ |
__u32 x; /**< x Position on the framebuffer */ |
__u32 y; /**< y Position on the framebuffer */ |
__u32 gamma_size; |
__u32 mode_valid; |
153,12 → 164,16 |
__u32 flags; /* see above flags */ |
/* Signed dest location allows it to be partially off screen */ |
__s32 crtc_x, crtc_y; |
__u32 crtc_w, crtc_h; |
__s32 crtc_x; |
__s32 crtc_y; |
__u32 crtc_w; |
__u32 crtc_h; |
/* Source values are 16.16 fixed point */ |
__u32 src_x, src_y; |
__u32 src_h, src_w; |
__u32 src_x; |
__u32 src_y; |
__u32 src_h; |
__u32 src_w; |
}; |
struct drm_mode_get_plane { |
244,7 → 259,8 |
__u32 connector_type_id; |
__u32 connection; |
__u32 mm_width, mm_height; /**< HxW in millimeters */ |
__u32 mm_width; /**< width in millimeters */ |
__u32 mm_height; /**< height in millimeters */ |
__u32 subpixel; |
__u32 pad; |
272,6 → 288,13 |
#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1) |
#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2) |
/* the PROP_ATOMIC flag is used to hide properties from userspace that |
* is not aware of atomic properties. This is mostly to work around |
* older userspace (DDX drivers) that read/write each prop they find, |
* witout being aware that this could be triggering a lengthy modeset. |
*/ |
#define DRM_MODE_PROP_ATOMIC 0x80000000 |
struct drm_mode_property_enum { |
__u64 value; |
char name[DRM_PROP_NAME_LEN]; |
320,7 → 343,8 |
struct drm_mode_fb_cmd { |
__u32 fb_id; |
__u32 width, height; |
__u32 width; |
__u32 height; |
__u32 pitch; |
__u32 bpp; |
__u32 depth; |
329,16 → 353,18 |
}; |
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ |
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ |
struct drm_mode_fb_cmd2 { |
__u32 fb_id; |
__u32 width, height; |
__u32 width; |
__u32 height; |
__u32 pixel_format; /* fourcc code from drm_fourcc.h */ |
__u32 flags; /* see above flags */ |
/* |
* In case of planar formats, this ioctl allows up to 4 |
* buffer objects with offets and pitches per plane. |
* buffer objects with offsets and pitches per plane. |
* The pitch and offset order is dictated by the fourcc, |
* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: |
* |
346,13 → 372,21 |
* followed by an interleaved U/V plane containing |
* 8 bit 2x2 subsampled colour difference samples. |
* |
* So it would consist of Y as offset[0] and UV as |
* offeset[1]. Note that offset[0] will generally |
* be 0. |
* So it would consist of Y as offsets[0] and UV as |
* offsets[1]. Note that offsets[0] will generally |
* be 0 (but this is not required). |
* |
* To accommodate tiled, compressed, etc formats, a per-plane |
* modifier can be specified. The default value of zero |
* indicates "native" format as specified by the fourcc. |
* Vendor specific modifier token. This allows, for example, |
* different tiling/swizzling pattern on different planes. |
* See discussion above of DRM_FORMAT_MOD_xxx. |
*/ |
__u32 handles[4]; |
__u32 pitches[4]; /* pitch for each plane */ |
__u32 offsets[4]; /* offset of each plane */ |
__u64 modifier[4]; /* ie, tiling, compressed (per plane) */ |
}; |
#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 |
519,4 → 553,47 |
uint32_t handle; |
}; |
/* page-flip flags are valid, plus: */ |
#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100 |
#define DRM_MODE_ATOMIC_NONBLOCK 0x0200 |
#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400 |
#define DRM_MODE_ATOMIC_FLAGS (\ |
DRM_MODE_PAGE_FLIP_EVENT |\ |
DRM_MODE_PAGE_FLIP_ASYNC |\ |
DRM_MODE_ATOMIC_TEST_ONLY |\ |
DRM_MODE_ATOMIC_NONBLOCK |\ |
DRM_MODE_ATOMIC_ALLOW_MODESET) |
struct drm_mode_atomic { |
__u32 flags; |
__u32 count_objs; |
__u64 objs_ptr; |
__u64 count_props_ptr; |
__u64 props_ptr; |
__u64 prop_values_ptr; |
__u64 reserved; |
__u64 user_data; |
}; |
/** |
* Create a new 'blob' data property, copying length bytes from data pointer, |
* and returning new blob ID. |
*/ |
struct drm_mode_create_blob { |
/** Pointer to data to copy. */ |
__u64 data; |
/** Length of data to copy. */ |
__u32 length; |
/** Return: new property ID. */ |
__u32 blob_id; |
}; |
/** |
* Destroy a user-created blob property. |
*/ |
struct drm_mode_destroy_blob { |
__u32 blob_id; |
}; |
#endif |
/drivers/include/uapi/drm/i915_drm.h |
---|
171,8 → 171,12 |
#define I915_BOX_TEXTURE_LOAD 0x8 |
#define I915_BOX_LOST_CONTEXT 0x10 |
/* I915 specific ioctls |
* The device specific ioctl range is 0x40 to 0x79. |
/* |
* i915 specific ioctls. |
* |
* The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie |
* [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset |
* against DRM_COMMAND_BASE and should be between [0x0, 0x60). |
*/ |
#define DRM_I915_INIT 0x00 |
#define DRM_I915_FLUSH 0x01 |
224,6 → 228,8 |
#define DRM_I915_REG_READ 0x31 |
#define DRM_I915_GET_RESET_STATS 0x32 |
#define DRM_I915_GEM_USERPTR 0x33 |
#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 |
#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 |
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
268,7 → 274,7 |
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) |
#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) |
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) |
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) |
275,6 → 281,8 |
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) |
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) |
#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) |
#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) |
#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) |
/* Allow drivers to submit batchbuffers directly to hardware, relying |
* on the security mechanisms provided by hardware. |
341,9 → 349,20 |
#define I915_PARAM_HAS_WT 27 |
#define I915_PARAM_CMD_PARSER_VERSION 28 |
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
#define I915_PARAM_MMAP_VERSION 30 |
#define I915_PARAM_HAS_BSD2 31 |
#define I915_PARAM_REVISION 32 |
#define I915_PARAM_SUBSLICE_TOTAL 33 |
#define I915_PARAM_EU_TOTAL 34 |
#define I915_PARAM_HAS_GPU_RESET 35 |
#define I915_PARAM_HAS_RESOURCE_STREAMER 36 |
typedef struct drm_i915_getparam { |
int param; |
__s32 param; |
/* |
* WARNING: Using pointers instead of fixed-size u64 means we need to write |
* compat32 code. Don't repeat this mistake. |
*/ |
int __user *value; |
} drm_i915_getparam_t; |
488,6 → 507,14 |
* This is a fixed-size type for 32/64 compatibility. |
*/ |
__u64 addr_ptr; |
/** |
* Flags for extended behaviour. |
* |
* Added in version 2. |
*/ |
__u64 flags; |
#define I915_MMAP_WC 0x1 |
}; |
struct drm_i915_gem_mmap_gtt { |
663,7 → 690,8 |
#define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
#define EXEC_OBJECT_NEEDS_GTT (1<<1) |
#define EXEC_OBJECT_WRITE (1<<2) |
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) |
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) |
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_SUPPORTS_48B_ADDRESS<<1) |
__u64 flags; |
__u64 rsvd1; |
737,8 → 765,19 |
*/ |
#define I915_EXEC_HANDLE_LUT (1<<12) |
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) |
/** Used for switching BSD rings on the platforms with two BSD rings */ |
#define I915_EXEC_BSD_MASK (3<<13) |
#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ |
#define I915_EXEC_BSD_RING1 (1<<13) |
#define I915_EXEC_BSD_RING2 (2<<13) |
/** Tell the kernel that the batchbuffer is processed by |
* the resource streamer. |
*/ |
#define I915_EXEC_RESOURCE_STREAMER (1<<15) |
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) |
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
#define i915_execbuffer2_set_context_id(eb2, context) \ |
(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
973,6 → 1012,7 |
/* flags */ |
#define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
#define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) |
struct drm_intel_overlay_attrs { |
__u32 flags; |
__u32 color_key; |
1042,6 → 1082,14 |
__u64 offset; |
__u64 val; /* Return value */ |
}; |
/* Known registers: |
* |
* Render engine timestamp - 0x2358 + 64bit - gen7+ |
* - Note this register returns an invalid value if using the default |
* single instruction 8byte read, in order to workaround that use |
* offset (0x2538 | 1) instead. |
* |
*/ |
struct drm_i915_reset_stats { |
__u32 ctx_id; |
1073,6 → 1121,16 |
__u32 handle; |
}; |
struct drm_i915_gem_context_param { |
__u32 ctx_id; |
__u32 size; |
__u64 param; |
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 |
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 |
__u64 value; |
}; |
struct drm_i915_mask { |
__u32 handle; |
__u32 width; |
1100,6 → 1158,7 |
__u32 height; |
__u32 bo_pitch; |
__u32 bo_map; |
__u32 forced; |
}; |
/drivers/include/uapi/drm/radeon_drm.h |
---|
33,7 → 33,7 |
#ifndef __RADEON_DRM_H__ |
#define __RADEON_DRM_H__ |
#include <drm/drm.h> |
#include "drm.h" |
/* WARNING: If you change any of these defines, make sure to change the |
* defines in the X server file (radeon_sarea.h) |
1034,6 → 1034,12 |
#define RADEON_INFO_VRAM_USAGE 0x1e |
#define RADEON_INFO_GTT_USAGE 0x1f |
#define RADEON_INFO_ACTIVE_CU_COUNT 0x20 |
#define RADEON_INFO_CURRENT_GPU_TEMP 0x21 |
#define RADEON_INFO_CURRENT_GPU_SCLK 0x22 |
#define RADEON_INFO_CURRENT_GPU_MCLK 0x23 |
#define RADEON_INFO_READ_REG 0x24 |
#define RADEON_INFO_VA_UNMAP_WORKING 0x25 |
#define RADEON_INFO_GPU_RESET_COUNTER 0x26 |
struct drm_radeon_info { |
uint32_t request; |
/drivers/include/uapi/drm/vmwgfx_drm.h |
---|
1,6 → 1,6 |
/************************************************************************** |
* |
* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA |
* Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
64,6 → 64,7 |
#define DRM_VMW_GB_SURFACE_CREATE 23 |
#define DRM_VMW_GB_SURFACE_REF 24 |
#define DRM_VMW_SYNCCPU 25 |
#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 |
/*************************************************************************/ |
/** |
88,6 → 89,8 |
#define DRM_VMW_PARAM_3D_CAPS_SIZE 8 |
#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 |
#define DRM_VMW_PARAM_MAX_MOB_SIZE 10 |
#define DRM_VMW_PARAM_SCREEN_TARGET 11 |
#define DRM_VMW_PARAM_DX 12 |
/** |
* enum drm_vmw_handle_type - handle type for ref ioctls |
296,7 → 299,7 |
* Argument to the DRM_VMW_EXECBUF Ioctl. |
*/ |
#define DRM_VMW_EXECBUF_VERSION 1 |
#define DRM_VMW_EXECBUF_VERSION 2 |
struct drm_vmw_execbuf_arg { |
uint64_t commands; |
305,6 → 308,8 |
uint64_t fence_rep; |
uint32_t version; |
uint32_t flags; |
uint32_t context_handle; |
uint32_t pad64; |
}; |
/** |
825,7 → 830,6 |
enum drm_vmw_shader_type { |
drm_vmw_shader_type_vs = 0, |
drm_vmw_shader_type_ps, |
drm_vmw_shader_type_gs |
}; |
907,6 → 911,8 |
* @buffer_handle Buffer handle of backup buffer. SVGA3D_INVALID_ID |
* if none. |
* @base_size Size of the base mip level for all faces. |
* @array_size Must be zero for non-DX hardware, and if non-zero |
* svga3d_flags must have proper bind flags setup. |
* |
* Input argument to the DRM_VMW_GB_SURFACE_CREATE Ioctl. |
* Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl. |
919,7 → 925,7 |
uint32_t multisample_count; |
uint32_t autogen_filter; |
uint32_t buffer_handle; |
uint32_t pad64; |
uint32_t array_size; |
struct drm_vmw_size base_size; |
}; |
1059,4 → 1065,28 |
uint32_t pad64; |
}; |
/*************************************************************************/ |
/** |
* DRM_VMW_CREATE_EXTENDED_CONTEXT - Create a host context. |
* |
* Allocates a device unique context id, and queues a create context command |
* for the host. Does not wait for host completion. |
*/ |
enum drm_vmw_extended_context { |
drm_vmw_context_legacy, |
drm_vmw_context_dx |
}; |
/** |
* union drm_vmw_extended_context_arg |
* |
* @req: Context type. |
* @rep: Context identifier. |
* |
* Argument to the DRM_VMW_CREATE_EXTENDED_CONTEXT Ioctl. |
*/ |
union drm_vmw_extended_context_arg { |
enum drm_vmw_extended_context req; |
struct drm_vmw_context_arg rep; |
}; |
#endif |
/drivers/include/uapi/linux/media-bus-format.h |
---|
0,0 → 1,137 |
/* |
* Media Bus API header |
* |
* Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License version 2 as |
* published by the Free Software Foundation. |
*/ |
#ifndef __LINUX_MEDIA_BUS_FORMAT_H |
#define __LINUX_MEDIA_BUS_FORMAT_H |
/* |
* These bus formats uniquely identify data formats on the data bus. Format 0 |
* is reserved, MEDIA_BUS_FMT_FIXED shall be used by host-client pairs, where |
* the data format is fixed. Additionally, "2X8" means that one pixel is |
* transferred in two 8-bit samples, "BE" or "LE" specify in which order those |
* samples are transferred over the bus: "LE" means that the least significant |
* bits are transferred first, "BE" means that the most significant bits are |
* transferred first, and "PADHI" and "PADLO" define which bits - low or high, |
* in the incomplete high byte, are filled with padding bits. |
* |
* The bus formats are grouped by type, bus_width, bits per component, samples |
* per pixel and order of subsamples. Numerical values are sorted using generic |
* numerical sort order (8 thus comes before 10). |
* |
* As their value can't change when a new bus format is inserted in the |
* enumeration, the bus formats are explicitly given a numerical value. The next |
* free values for each category are listed below, update them when inserting |
* new pixel codes. |
*/ |
#define MEDIA_BUS_FMT_FIXED 0x0001 |
/* RGB - next is 0x1018 */ |
#define MEDIA_BUS_FMT_RGB444_1X12 0x1016 |
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 |
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 |
#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 |
#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 |
#define MEDIA_BUS_FMT_RGB565_1X16 0x1017 |
#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 |
#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006 |
#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007 |
#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008 |
#define MEDIA_BUS_FMT_RGB666_1X18 0x1009 |
#define MEDIA_BUS_FMT_RBG888_1X24 0x100e |
#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015 |
#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010 |
#define MEDIA_BUS_FMT_BGR888_1X24 0x1013 |
#define MEDIA_BUS_FMT_GBR888_1X24 0x1014 |
#define MEDIA_BUS_FMT_RGB888_1X24 0x100a |
#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b |
#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c |
#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 |
#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 |
#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d |
#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f |
/* YUV (including grey) - next is 0x2026 */ |
#define MEDIA_BUS_FMT_Y8_1X8 0x2001 |
#define MEDIA_BUS_FMT_UV8_1X8 0x2015 |
#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 |
#define MEDIA_BUS_FMT_VYUY8_1_5X8 0x2003 |
#define MEDIA_BUS_FMT_YUYV8_1_5X8 0x2004 |
#define MEDIA_BUS_FMT_YVYU8_1_5X8 0x2005 |
#define MEDIA_BUS_FMT_UYVY8_2X8 0x2006 |
#define MEDIA_BUS_FMT_VYUY8_2X8 0x2007 |
#define MEDIA_BUS_FMT_YUYV8_2X8 0x2008 |
#define MEDIA_BUS_FMT_YVYU8_2X8 0x2009 |
#define MEDIA_BUS_FMT_Y10_1X10 0x200a |
#define MEDIA_BUS_FMT_UYVY10_2X10 0x2018 |
#define MEDIA_BUS_FMT_VYUY10_2X10 0x2019 |
#define MEDIA_BUS_FMT_YUYV10_2X10 0x200b |
#define MEDIA_BUS_FMT_YVYU10_2X10 0x200c |
#define MEDIA_BUS_FMT_Y12_1X12 0x2013 |
#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c |
#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d |
#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e |
#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f |
#define MEDIA_BUS_FMT_UYVY8_1X16 0x200f |
#define MEDIA_BUS_FMT_VYUY8_1X16 0x2010 |
#define MEDIA_BUS_FMT_YUYV8_1X16 0x2011 |
#define MEDIA_BUS_FMT_YVYU8_1X16 0x2012 |
#define MEDIA_BUS_FMT_YDYUYDYV8_1X16 0x2014 |
#define MEDIA_BUS_FMT_UYVY10_1X20 0x201a |
#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b |
#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d |
#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e |
#define MEDIA_BUS_FMT_VUY8_1X24 0x2024 |
#define MEDIA_BUS_FMT_YUV8_1X24 0x2025 |
#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020 |
#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021 |
#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 |
#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 |
#define MEDIA_BUS_FMT_YUV10_1X30 0x2016 |
#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 |
/* Bayer - next is 0x3019 */ |
#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 |
#define MEDIA_BUS_FMT_SGBRG8_1X8 0x3013 |
#define MEDIA_BUS_FMT_SGRBG8_1X8 0x3002 |
#define MEDIA_BUS_FMT_SRGGB8_1X8 0x3014 |
#define MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8 0x3015 |
#define MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8 0x3016 |
#define MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8 0x3017 |
#define MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8 0x3018 |
#define MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 0x300b |
#define MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 0x300c |
#define MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 0x3009 |
#define MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 0x300d |
#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE 0x3003 |
#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE 0x3004 |
#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE 0x3005 |
#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE 0x3006 |
#define MEDIA_BUS_FMT_SBGGR10_1X10 0x3007 |
#define MEDIA_BUS_FMT_SGBRG10_1X10 0x300e |
#define MEDIA_BUS_FMT_SGRBG10_1X10 0x300a |
#define MEDIA_BUS_FMT_SRGGB10_1X10 0x300f |
#define MEDIA_BUS_FMT_SBGGR12_1X12 0x3008 |
#define MEDIA_BUS_FMT_SGBRG12_1X12 0x3010 |
#define MEDIA_BUS_FMT_SGRBG12_1X12 0x3011 |
#define MEDIA_BUS_FMT_SRGGB12_1X12 0x3012 |
/* JPEG compressed formats - next is 0x4002 */ |
#define MEDIA_BUS_FMT_JPEG_1X8 0x4001 |
/* Vendor specific formats - next is 0x5002 */ |
/* S5C73M3 sensor specific interleaved UYVY and JPEG */ |
#define MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8 0x5001 |
/* HSV - next is 0x6002 */ |
#define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001 |
#endif /* __LINUX_MEDIA_BUS_FORMAT_H */ |
/drivers/include/uapi/linux/swab.h |
---|
0,0 → 1,288 |
#ifndef _UAPI_LINUX_SWAB_H |
#define _UAPI_LINUX_SWAB_H |
#include <linux/types.h> |
#include <linux/compiler.h> |
#include <asm/swab.h> |
/* |
* casts are necessary for constants, because we never know how for sure |
* how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. |
*/ |
#define ___constant_swab16(x) ((__u16)( \ |
(((__u16)(x) & (__u16)0x00ffU) << 8) | \ |
(((__u16)(x) & (__u16)0xff00U) >> 8))) |
#define ___constant_swab32(x) ((__u32)( \ |
(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ |
(((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ |
(((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ |
(((__u32)(x) & (__u32)0xff000000UL) >> 24))) |
#define ___constant_swab64(x) ((__u64)( \ |
(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ |
(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ |
(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ |
(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ |
(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ |
(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ |
(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ |
(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56))) |
#define ___constant_swahw32(x) ((__u32)( \ |
(((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ |
(((__u32)(x) & (__u32)0xffff0000UL) >> 16))) |
#define ___constant_swahb32(x) ((__u32)( \ |
(((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ |
(((__u32)(x) & (__u32)0xff00ff00UL) >> 8))) |
/* |
* Implement the following as inlines, but define the interface using |
* macros to allow constant folding when possible: |
* ___swab16, ___swab32, ___swab64, ___swahw32, ___swahb32 |
*/ |
static inline __attribute_const__ __u16 __fswab16(__u16 val) |
{ |
#ifdef __HAVE_BUILTIN_BSWAP16__ |
return __builtin_bswap16(val); |
#elif defined (__arch_swab16) |
return __arch_swab16(val); |
#else |
return ___constant_swab16(val); |
#endif |
} |
static inline __attribute_const__ __u32 __fswab32(__u32 val) |
{ |
#ifdef __HAVE_BUILTIN_BSWAP32__ |
return __builtin_bswap32(val); |
#elif defined(__arch_swab32) |
return __arch_swab32(val); |
#else |
return ___constant_swab32(val); |
#endif |
} |
static inline __attribute_const__ __u64 __fswab64(__u64 val) |
{ |
#ifdef __HAVE_BUILTIN_BSWAP64__ |
return __builtin_bswap64(val); |
#elif defined (__arch_swab64) |
return __arch_swab64(val); |
#elif defined(__SWAB_64_THRU_32__) |
__u32 h = val >> 32; |
__u32 l = val & ((1ULL << 32) - 1); |
return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); |
#else |
return ___constant_swab64(val); |
#endif |
} |
static inline __attribute_const__ __u32 __fswahw32(__u32 val) |
{ |
#ifdef __arch_swahw32 |
return __arch_swahw32(val); |
#else |
return ___constant_swahw32(val); |
#endif |
} |
static inline __attribute_const__ __u32 __fswahb32(__u32 val) |
{ |
#ifdef __arch_swahb32 |
return __arch_swahb32(val); |
#else |
return ___constant_swahb32(val); |
#endif |
} |
/** |
* __swab16 - return a byteswapped 16-bit value |
* @x: value to byteswap |
*/ |
#define __swab16(x) \ |
(__builtin_constant_p((__u16)(x)) ? \ |
___constant_swab16(x) : \ |
__fswab16(x)) |
/** |
* __swab32 - return a byteswapped 32-bit value |
* @x: value to byteswap |
*/ |
#define __swab32(x) \ |
(__builtin_constant_p((__u32)(x)) ? \ |
___constant_swab32(x) : \ |
__fswab32(x)) |
/** |
* __swab64 - return a byteswapped 64-bit value |
* @x: value to byteswap |
*/ |
#define __swab64(x) \ |
(__builtin_constant_p((__u64)(x)) ? \ |
___constant_swab64(x) : \ |
__fswab64(x)) |
/** |
* __swahw32 - return a word-swapped 32-bit value |
* @x: value to wordswap |
* |
* __swahw32(0x12340000) is 0x00001234 |
*/ |
#define __swahw32(x) \ |
(__builtin_constant_p((__u32)(x)) ? \ |
___constant_swahw32(x) : \ |
__fswahw32(x)) |
/** |
* __swahb32 - return a high and low byte-swapped 32-bit value |
* @x: value to byteswap |
* |
* __swahb32(0x12345678) is 0x34127856 |
*/ |
#define __swahb32(x) \ |
(__builtin_constant_p((__u32)(x)) ? \ |
___constant_swahb32(x) : \ |
__fswahb32(x)) |
/** |
* __swab16p - return a byteswapped 16-bit value from a pointer |
* @p: pointer to a naturally-aligned 16-bit value |
*/ |
static inline __u16 __swab16p(const __u16 *p) |
{ |
#ifdef __arch_swab16p |
return __arch_swab16p(p); |
#else |
return __swab16(*p); |
#endif |
} |
/** |
* __swab32p - return a byteswapped 32-bit value from a pointer |
* @p: pointer to a naturally-aligned 32-bit value |
*/ |
static inline __u32 __swab32p(const __u32 *p) |
{ |
#ifdef __arch_swab32p |
return __arch_swab32p(p); |
#else |
return __swab32(*p); |
#endif |
} |
/** |
* __swab64p - return a byteswapped 64-bit value from a pointer |
* @p: pointer to a naturally-aligned 64-bit value |
*/ |
static inline __u64 __swab64p(const __u64 *p) |
{ |
#ifdef __arch_swab64p |
return __arch_swab64p(p); |
#else |
return __swab64(*p); |
#endif |
} |
/** |
* __swahw32p - return a wordswapped 32-bit value from a pointer |
* @p: pointer to a naturally-aligned 32-bit value |
* |
* See __swahw32() for details of wordswapping. |
*/ |
static inline __u32 __swahw32p(const __u32 *p) |
{ |
#ifdef __arch_swahw32p |
return __arch_swahw32p(p); |
#else |
return __swahw32(*p); |
#endif |
} |
/** |
* __swahb32p - return a high and low byteswapped 32-bit value from a pointer |
* @p: pointer to a naturally-aligned 32-bit value |
* |
* See __swahb32() for details of high/low byteswapping. |
*/ |
static inline __u32 __swahb32p(const __u32 *p) |
{ |
#ifdef __arch_swahb32p |
return __arch_swahb32p(p); |
#else |
return __swahb32(*p); |
#endif |
} |
/** |
* __swab16s - byteswap a 16-bit value in-place |
* @p: pointer to a naturally-aligned 16-bit value |
*/ |
static inline void __swab16s(__u16 *p) |
{ |
#ifdef __arch_swab16s |
__arch_swab16s(p); |
#else |
*p = __swab16p(p); |
#endif |
} |
/** |
* __swab32s - byteswap a 32-bit value in-place |
* @p: pointer to a naturally-aligned 32-bit value |
*/ |
static inline void __swab32s(__u32 *p) |
{ |
#ifdef __arch_swab32s |
__arch_swab32s(p); |
#else |
*p = __swab32p(p); |
#endif |
} |
/** |
* __swab64s - byteswap a 64-bit value in-place |
* @p: pointer to a naturally-aligned 64-bit value |
*/ |
static inline void __swab64s(__u64 *p) |
{ |
#ifdef __arch_swab64s |
__arch_swab64s(p); |
#else |
*p = __swab64p(p); |
#endif |
} |
/** |
* __swahw32s - wordswap a 32-bit value in-place |
* @p: pointer to a naturally-aligned 32-bit value |
* |
* See __swahw32() for details of wordswapping |
*/ |
static inline void __swahw32s(__u32 *p) |
{ |
#ifdef __arch_swahw32s |
__arch_swahw32s(p); |
#else |
*p = __swahw32p(p); |
#endif |
} |
/** |
* __swahb32s - high and low byteswap a 32-bit value in-place |
* @p: pointer to a naturally-aligned 32-bit value |
* |
* See __swahb32() for details of high and low byte swapping |
*/ |
static inline void __swahb32s(__u32 *p) |
{ |
#ifdef __arch_swahb32s |
__arch_swahb32s(p); |
#else |
*p = __swahb32p(p); |
#endif |
} |
#endif /* _UAPI_LINUX_SWAB_H */ |