WebSVN – Kolibri OS – Path Comparison – / – /drivers/include/linux/ Rev 3030 and /drivers/include/linux/ Rev 3031

Regard whitespace Rev 3030 → Rev 3031

 /drivers/include/linux/asm/alternative.h
 ,7 → 129,7
  * use this macro(s) if you need more than one output parameter
  * in alternative_io
  */
-#define ASM_OUTPUT2(a, b) a, b
+#define ASM_OUTPUT2(a) a
 struct paravirt_patch_site;
 #ifdef CONFIG_PARAVIRT

 /drivers/include/linux/asm/atomic_32.h
 ,8 → 266,8
         u64 __aligned(8) counter;
 } atomic64_t;
-#define ATOMIC64_INIT(val)      { (val) }
 extern u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old_val, u64 new_val);
 /**
 ,8 → 278,22
  * Atomically xchgs the value of @ptr to @new_val and returns
  * the old value.
  */
-extern u64 atomic64_xchg(atomic64_t *ptr, u64 new_val);
+static inline long long atomic64_xchg(atomic64_t *v, long long n)
+{
+    long long o;
+    unsigned high = (unsigned)(n >> 32);
+    unsigned low = (unsigned)n;
+    asm volatile(
+    "1:                 \n\t"
+    "cmpxchg8b (%%esi)  \n\t"
+    "jnz 1b             \n\t"
+    :"=&A" (o)
+    :"S" (v), "b" (low), "c" (high)
+    : "memory", "cc");
+    return o;
+}
 /**
  * atomic64_set - set atomic64 variable
  * @ptr:      pointer to type atomic64_t
 ,8 → 301,21
  *
  * Atomically sets the value of @ptr to @new_val.
  */
-extern void atomic64_set(atomic64_t *ptr, u64 new_val);
+static inline void atomic64_set(atomic64_t *v, long long i)
+{
+    unsigned high = (unsigned)(i >> 32);
+    unsigned low = (unsigned)i;
+    asm volatile (
+    "1:                 \n\t"
+    "cmpxchg8b (%%esi)  \n\t"
+    "jnz 1b             \n\t"
+    :
+    :"S" (v), "b" (low), "c" (high)
+    : "eax", "edx", "memory", "cc");
+}
 /**
  * atomic64_read - read atomic64 variable
  * @ptr:      pointer to type atomic64_t
 ,7 → 344,6
         return res;
 }
-extern u64 atomic64_read(atomic64_t *ptr);
 /**
  * atomic64_add_return - add and return

 /drivers/include/linux/asm/bitops.h
 ,6 → 15,8
 #include <linux/compiler.h>
 #include <asm/alternative.h>
+#define BIT_64(n)                       (U64_C(1) << (n))
 /*
  * These have to be done with inline assembly: that way the bit-setting
  * is guaranteed to be atomic. All bit operations return 0 if the bit
 ,6 → 264,13
  * This operation is non-atomic and can be reordered.
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
+ *
+ * Note: the operation is performed atomically with respect to
+ * the local CPU, but not other CPUs. Portable code should not
+ * rely on this behaviour.
+ * KVM relies on this behaviour on x86 for modifying memory that is also
+ * accessed from a hypervisor on the same CPU if running in a VM: don't change
+ * this without also updating arch/x86/kernel/kvm.c
  */
 static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
 ,7 → 318,7
 static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
 {
         return ((1UL << (nr % BITS_PER_LONG)) &
-                (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
+                (addr[nr / BITS_PER_LONG])) != 0;
 }
 static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
 ,7 → 355,7
  */
 static inline unsigned long __ffs(unsigned long word)
 {
-        asm("bsf %1,%0"
+        asm("rep; bsf %1,%0"
                 : "=r" (word)
                 : "rm" (word));
         return word;
 ,7 → 369,7
  */
 static inline unsigned long ffz(unsigned long word)
 {
-        asm("bsf %1,%0"
+        asm("rep; bsf %1,%0"
                 : "=r" (word)
                 : "r" (~word));
         return word;
 ,6 → 389,8
         return word;
 }
+#undef ADDR
 #ifdef __KERNEL__
 /**
  * ffs - find first set bit in word
 ,7 → 409,7
 #ifdef CONFIG_X86_CMOV
         asm("bsfl %1,%0\n\t"
             "cmovzl %2,%0"
-            : "=r" (r) : "rm" (x), "r" (-1));
+            : "=&r" (r) : "rm" (x), "r" (-1));
 #else
         asm("bsfl %1,%0\n\t"
             "jnz 1f\n\t"

 /drivers/include/linux/asm/cpufeature.h
 ,7 → 6,7
 #include <asm/required-features.h>
-#define NCAPINTS        9       /* N 32-bit words worth of info */
+#define NCAPINTS        10      /* N 32-bit words worth of info */
 /*
  * Note: If the comment begins with a quoted string, that string is used
 ,7 → 89,7
 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
 #define X86_FEATURE_11AP        (3*32+19) /* "" Bad local APIC aka 11AP */
 #define X86_FEATURE_NOPL        (3*32+20) /* The NOPL (0F 1F) instructions */
-#define X86_FEATURE_AMDC1E      (3*32+21) /* AMD C1E detected */
+                                          /* 21 available, was AMD_C1E */
 #define X86_FEATURE_XTOPOLOGY   (3*32+22) /* cpu topology enum extensions */
 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
 ,6 → 97,7
 #define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */
 #define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
 #define X86_FEATURE_APERFMPERF  (3*32+28) /* APERFMPERF */
+#define X86_FEATURE_EAGER_FPU   (3*32+29) /* "eagerfpu" Non lazy FPU restore */
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* "pni" SSE-3 */
 ,6 → 115,7
 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
 #define X86_FEATURE_PDCM        (4*32+15) /* Performance Capabilities */
+#define X86_FEATURE_PCID        (4*32+17) /* Process Context Identifiers */
 #define X86_FEATURE_DCA         (4*32+18) /* Direct Cache Access */
 #define X86_FEATURE_XMM4_1      (4*32+19) /* "sse4_1" SSE-4.1 */
 #define X86_FEATURE_XMM4_2      (4*32+20) /* "sse4_2" SSE-4.2 */
 ,10 → 122,13
 #define X86_FEATURE_X2APIC      (4*32+21) /* x2APIC */
 #define X86_FEATURE_MOVBE       (4*32+22) /* MOVBE instruction */
 #define X86_FEATURE_POPCNT      (4*32+23) /* POPCNT instruction */
+#define X86_FEATURE_TSC_DEADLINE_TIMER  (4*32+24) /* Tsc deadline timer */
 #define X86_FEATURE_AES         (4*32+25) /* AES instructions */
 #define X86_FEATURE_XSAVE       (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
 #define X86_FEATURE_OSXSAVE     (4*32+27) /* "" XSAVE enabled in the OS */
 #define X86_FEATURE_AVX         (4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_F16C        (4*32+29) /* 16-bit fp conversions */
+#define X86_FEATURE_RDRAND      (4*32+30) /* The RDRAND instruction */
 #define X86_FEATURE_HYPERVISOR  (4*32+31) /* Running on a hypervisor */
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
 ,24 → 155,63
 #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
 #define X86_FEATURE_OSVW        (6*32+ 9) /* OS Visible Workaround */
 #define X86_FEATURE_IBS         (6*32+10) /* Instruction Based Sampling */
-#define X86_FEATURE_SSE5        (6*32+11) /* SSE-5 */
+#define X86_FEATURE_XOP         (6*32+11) /* extended AVX instructions */
 #define X86_FEATURE_SKINIT      (6*32+12) /* SKINIT/STGI instructions */
 #define X86_FEATURE_WDT         (6*32+13) /* Watchdog timer */
+#define X86_FEATURE_LWP         (6*32+15) /* Light Weight Profiling */
+#define X86_FEATURE_FMA4        (6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_TCE         (6*32+17) /* translation cache extension */
+#define X86_FEATURE_NODEID_MSR  (6*32+19) /* NodeId MSR */
+#define X86_FEATURE_TBM         (6*32+21) /* trailing bit manipulations */
+#define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
+#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
 /*
  * Auxiliary flags: Linux defined - For features scattered in various
- * CPUID levels like 0x6, 0xA etc
+ * CPUID levels like 0x6, 0xA etc, word 7
  */
 #define X86_FEATURE_IDA         (7*32+ 0) /* Intel Dynamic Acceleration */
 #define X86_FEATURE_ARAT        (7*32+ 1) /* Always Running APIC Timer */
+#define X86_FEATURE_CPB         (7*32+ 2) /* AMD Core Performance Boost */
+#define X86_FEATURE_EPB         (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
+#define X86_FEATURE_XSAVEOPT    (7*32+ 4) /* Optimized Xsave */
+#define X86_FEATURE_PLN         (7*32+ 5) /* Intel Power Limit Notification */
+#define X86_FEATURE_PTS         (7*32+ 6) /* Intel Package Thermal Status */
+#define X86_FEATURE_DTHERM      (7*32+ 7) /* Digital Thermal Sensor */
+#define X86_FEATURE_HW_PSTATE   (7*32+ 8) /* AMD HW-PState */
-/* Virtualization flags: Linux defined */
+/* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
 #define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
 #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
+#define X86_FEATURE_NPT         (8*32+ 5) /* AMD Nested Page Table support */
+#define X86_FEATURE_LBRV        (8*32+ 6) /* AMD LBR Virtualization support */
+#define X86_FEATURE_SVML        (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
+#define X86_FEATURE_NRIPS       (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
+#define X86_FEATURE_TSCRATEMSR  (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
+#define X86_FEATURE_VMCBCLEAN   (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
+#define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */
+#define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */
+#define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */
+#define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */
+/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
+#define X86_FEATURE_FSGSBASE    (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
+#define X86_FEATURE_BMI1        (9*32+ 3) /* 1st group bit manipulation extensions */
+#define X86_FEATURE_HLE         (9*32+ 4) /* Hardware Lock Elision */
+#define X86_FEATURE_AVX2        (9*32+ 5) /* AVX2 instructions */
+#define X86_FEATURE_SMEP        (9*32+ 7) /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_BMI2        (9*32+ 8) /* 2nd group bit manipulation extensions */
+#define X86_FEATURE_ERMS        (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
+#define X86_FEATURE_INVPCID     (9*32+10) /* Invalidate Processor Context ID */
+#define X86_FEATURE_RTM         (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_RDSEED      (9*32+18) /* The RDSEED instruction */
+#define X86_FEATURE_ADX         (9*32+19) /* The ADCX and ADOX instructions */
+#define X86_FEATURE_SMAP        (9*32+20) /* Supervisor Mode Access Prevention */
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 #include <linux/bitops.h>
 ,8 → 222,7
 #define test_cpu_cap(c, bit)                                            \
          test_bit(bit, (unsigned long *)((c)->x86_capability))
-#define cpu_has(c, bit)                                                 \
-        (__builtin_constant_p(bit) &&                                   \
+#define REQUIRED_MASK_BIT_SET(bit)                                      \
          ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||     \
            (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||     \
            (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||     \
 ,10 → 230,18
            (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||     \
            (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||     \
            (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||     \
-           (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )      \
-          ? 1 :                                                         \
+           (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ||     \
+           (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) ||     \
+           (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )
+#define cpu_has(c, bit)                                                 \
+        (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :  \
          test_cpu_cap(c, bit))
+#define this_cpu_has(bit)                                               \
+        (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :  \
+         x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
 #define boot_cpu_has(bit)       cpu_has(&boot_cpu_data, bit)
 #define set_cpu_cap(c, bit)     set_bit(bit, (unsigned long *)((c)->x86_capability))
 ,7 → 270,9
 #define cpu_has_xmm             boot_cpu_has(X86_FEATURE_XMM)
 #define cpu_has_xmm2            boot_cpu_has(X86_FEATURE_XMM2)
 #define cpu_has_xmm3            boot_cpu_has(X86_FEATURE_XMM3)
+#define cpu_has_ssse3           boot_cpu_has(X86_FEATURE_SSSE3)
 #define cpu_has_aes             boot_cpu_has(X86_FEATURE_AES)
+#define cpu_has_avx             boot_cpu_has(X86_FEATURE_AVX)
 #define cpu_has_ht              boot_cpu_has(X86_FEATURE_HT)
 #define cpu_has_mp              boot_cpu_has(X86_FEATURE_MP)
 #define cpu_has_nx              boot_cpu_has(X86_FEATURE_NX)
 ,8 → 300,14
 #define cpu_has_xmm4_2          boot_cpu_has(X86_FEATURE_XMM4_2)
 #define cpu_has_x2apic          boot_cpu_has(X86_FEATURE_X2APIC)
 #define cpu_has_xsave           boot_cpu_has(X86_FEATURE_XSAVE)
+#define cpu_has_xsaveopt        boot_cpu_has(X86_FEATURE_XSAVEOPT)
+#define cpu_has_osxsave         boot_cpu_has(X86_FEATURE_OSXSAVE)
 #define cpu_has_hypervisor      boot_cpu_has(X86_FEATURE_HYPERVISOR)
 #define cpu_has_pclmulqdq       boot_cpu_has(X86_FEATURE_PCLMULQDQ)
+#define cpu_has_perfctr_core    boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
+#define cpu_has_cx8             boot_cpu_has(X86_FEATURE_CX8)
+#define cpu_has_cx16            boot_cpu_has(X86_FEATURE_CX16)
+#define cpu_has_eager_fpu       boot_cpu_has(X86_FEATURE_EAGER_FPU)
 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
 # define cpu_has_invlpg         1

 /drivers/include/linux/asm/div64.h
 ,6 → 4,7
 #ifdef CONFIG_X86_32
 #include <linux/types.h>
+#include <linux/log2.h>
 /*
  * do_div() is NOT a C function. It wants to return
 ,6 → 22,10
 ({                                                              \
         unsigned long __upper, __low, __high, __mod, __base;    \
         __base = (base);                                        \
+        if (__builtin_constant_p(__base) && is_power_of_2(__base)) { \
+                __mod = n & (__base - 1);                       \
+                n >>= ilog2(__base);                            \
+        } else {                                                \
         asm("":"=a" (__low), "=d" (__high) : "A" (n));          \
         __upper = __high;                                       \
         if (__high) {                                           \
 ,6 → 35,7
         asm("divl %2":"=a" (__low), "=d" (__mod)                \
             : "rm" (__base), "0" (__low), "1" (__upper));        \
         asm("":"=A" (n) : "a" (__low), "d" (__high));           \
+        }                                                       \
         __mod;                                                  \
 })

/drivers/include/linux/asm/required-features.h
84,5 → 84,7
#define REQUIRED_MASK5 0
#define REQUIRED_MASK6 0
#define REQUIRED_MASK7 0
#define REQUIRED_MASK8 0
#define REQUIRED_MASK9 0

#endif /* _ASM_X86_REQUIRED_FEATURES_H */

/drivers/include/linux/backlight.h
--- bitops.h (revision 3030)
+++ bitops.h (revision 3031)
@@ -26,6 +26,23 @@
(bit) < (size); \
(bit) = find_next_bit((addr), (size), (bit) + 1))

+/* same as for_each_set_bit() but use bit as value to start with */
+#define for_each_set_bit_from(bit, addr, size) \
+ for ((bit) = find_next_bit((addr), (size), (bit)); \
+ (bit) < (size); \
+ (bit) = find_next_bit((addr), (size), (bit) + 1))
+
+#define for_each_clear_bit(bit, addr, size) \
+ for ((bit) = find_first_zero_bit((addr), (size)); \
+ (bit) < (size); \
+ (bit) = find_next_zero_bit((addr), (size), (bit) + 1))
+
+/* same as for_each_clear_bit() but use bit as value to start with */
+#define for_each_clear_bit_from(bit, addr, size) \
+ for ((bit) = find_next_zero_bit((addr), (size), (bit)); \
+ (bit) < (size); \
+ (bit) = find_next_zero_bit((addr), (size), (bit) + 1))
+
static __inline__ int get_bitmask_order(unsigned int count)
{
int order;
@@ -50,6 +67,26 @@
}

/**
+ * rol64 - rotate a 64-bit value left
+ * @word: value to rotate
+ * @shift: bits to roll
+ */
+static inline __u64 rol64(__u64 word, unsigned int shift)
+{
+ return (word << shift) \| (word >> (64 - shift));
+}
+
+/**
+ * ror64 - rotate a 64-bit value right
+ * @word: value to rotate
+ * @shift: bits to roll
+ */
+static inline __u64 ror64(__u64 word, unsigned int shift)
+{
+ return (word >> shift) \| (word << (64 - shift));
+}
+
+/**
* rol32 - rotate a 32-bit value left
* @word: value to rotate
* @shift: bits to roll

 /drivers/include/linux/bug.h
 ,0 → 1,12
+#ifndef _ASM_GENERIC_BUG_H
+#define _ASM_GENERIC_BUG_H
+#define WARN(condition, format...) ({                               \
+    int __ret_warn_on = !!(condition);                              \
+    unlikely(__ret_warn_on);                                        \
+})
+#endif

/drivers/include/linux/compiler-gcc.h
83,6 → 83,7
#define __pure __attribute__((pure))
#define __aligned(x) __attribute__((aligned(x)))
#define __printf(a,b) __attribute__((format(printf,a,b)))
#define __scanf(a, b) __attribute__((format(scanf, a, b)))
#define noinline __attribute__((noinline))
#define __attribute_const__ __attribute__((__const__))
#define __maybe_unused __attribute__((unused))

 /drivers/include/linux/compiler-gcc4.h
 ,6 → 29,7
    the kernel context */
 #define __cold                  __attribute__((__cold__))
+#define __linktime_error(message) __attribute__((__error__(message)))
 #if __GNUC_MINOR__ >= 5
 /*
 ,10 → 49,17
 #endif
 #endif
+#if __GNUC_MINOR__ >= 6
+/*
+ * Tell the optimizer that something else uses this function or variable.
+ */
+#define __visible __attribute__((externally_visible))
+#endif
 #if __GNUC_MINOR__ > 0
 #define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
 #endif
-#if __GNUC_MINOR__ >= 4 && !defined(__CHECKER__)
+#if __GNUC_MINOR__ >= 3 && !defined(__CHECKER__)
 #define __compiletime_warning(message) __attribute__((warning(message)))
 #define __compiletime_error(message) __attribute__((error(message)))
 #endif

 /drivers/include/linux/compiler.h
 ,7 → 236,7
 /*
  * Rather then using noinline to prevent stack consumption, use
- * noinline_for_stack instead.  For documentaiton reasons.
+ * noinline_for_stack instead.  For documentation reasons.
  */
 #define noinline_for_stack noinline
 ,6 → 278,10
 # define __section(S) __attribute__ ((__section__(#S)))
 #endif
+#ifndef __visible
+#define __visible
+#endif
 /* Are two types/vars the same type (ignoring qualifiers)? */
 #ifndef __same_type
 # define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
 ,7 → 297,9
 #ifndef __compiletime_error
 # define __compiletime_error(message)
 #endif
+#ifndef __linktime_error
+# define __linktime_error(message)
+#endif
 /*
  * Prevent the compiler from merging or refetching accesses.  The compiler
  * is also forbidden from reordering successive instances of ACCESS_ONCE(),

/drivers/include/linux/delay.h
--- dmapool.h (revision 3030)
+++ dmapool.h (revision 3031)
@@ -21,6 +21,12 @@

void dma_pool_free(struct dma_pool pool, void vaddr, dma_addr_t addr);

+/*
+ * Managed DMA pool
+ */
+struct dma_pool dmam_pool_create(const char name, struct device *dev,
+ size_t size, size_t align, size_t allocation);
+void dmam_pool_destroy(struct dma_pool *pool);

#endif

 /drivers/include/linux/errno-base.h
 ,0 → 1,39
+#ifndef _ASM_GENERIC_ERRNO_BASE_H
+#define _ASM_GENERIC_ERRNO_BASE_H
+#define EPERM            1      /* Operation not permitted */
+#define ENOENT           2      /* No such file or directory */
+#define ESRCH            3      /* No such process */
+#define EINTR            4      /* Interrupted system call */
+#define EIO          5  /* I/O error */
+#define ENXIO            6      /* No such device or address */
+#define E2BIG            7      /* Argument list too long */
+#define ENOEXEC          8      /* Exec format error */
+#define EBADF            9      /* Bad file number */
+#define ECHILD          10      /* No child processes */
+#define EAGAIN          11      /* Try again */
+#define ENOMEM          12      /* Out of memory */
+#define EACCES          13      /* Permission denied */
+#define EFAULT          14      /* Bad address */
+#define ENOTBLK         15      /* Block device required */
+#define EBUSY           16      /* Device or resource busy */
+#define EEXIST          17      /* File exists */
+#define EXDEV           18      /* Cross-device link */
+#define ENODEV          19      /* No such device */
+#define ENOTDIR         20      /* Not a directory */
+#define EISDIR          21      /* Is a directory */
+#define EINVAL          22      /* Invalid argument */
+#define ENFILE          23      /* File table overflow */
+#define EMFILE          24      /* Too many open files */
+#define ENOTTY          25      /* Not a typewriter */
+#define ETXTBSY         26      /* Text file busy */
+#define EFBIG           27      /* File too large */
+#define ENOSPC          28      /* No space left on device */
+#define ESPIPE          29      /* Illegal seek */
+#define EROFS           30      /* Read-only file system */
+#define EMLINK          31      /* Too many links */
+#define EPIPE           32      /* Broken pipe */
+#define EDOM            33      /* Math argument out of domain of func */
+#define ERANGE          34      /* Math result not representable */
+#endif

 /drivers/include/linux/export.h
 ,0 → 1,19
+#ifndef _LINUX_EXPORT_H
+#define _LINUX_EXPORT_H
+/*
+ * Export symbols from the kernel to modules.  Forked from module.h
+ * to reduce the amount of pointless cruft we feed to gcc when only
+ * exporting a simple symbol or two.
+ *
+ * If you feel the need to add #include <linux/foo.h> to this file
+ * then you are doing something wrong and should go away silently.
+ */
+#define EXPORT_SYMBOL(sym)
+#define EXPORT_SYMBOL_GPL(sym)
+#define EXPORT_SYMBOL_GPL_FUTURE(sym)
+#define EXPORT_UNUSED_SYMBOL(sym)
+#define EXPORT_UNUSED_SYMBOL_GPL(sym)
+#define THIS_MODULE ((struct module *)0)
+#endif /* _LINUX_EXPORT_H */

 /drivers/include/linux/fb.h
 ,6 → 549,10
 #define FB_EVENT_FB_UNBIND              0x0E
 /*      CONSOLE-SPECIFIC: remap all consoles to new fb - for vga switcheroo */
 #define FB_EVENT_REMAP_ALL_CONSOLE      0x0F
+/*      A hardware display blank early change occured */
+#define FB_EARLY_EVENT_BLANK            0x10
+/*      A hardware display blank revert early change occured */
+#define FB_R_EARLY_EVENT_BLANK          0x11
 struct fb_event {
         struct fb_info *info;
 ,6 → 603,7
         struct mutex lock; /* mutex that protects the page list */
         struct list_head pagelist; /* list of touched pages */
         /* callback */
+        void (*first_io)(struct fb_info *info);
         void (*deferred_io)(struct fb_info *info, struct list_head *pagelist);
 };
 #endif
 ,6 → 995,7
 /* drivers/video/fbmem.c */
 extern int register_framebuffer(struct fb_info *fb_info);
 extern int unregister_framebuffer(struct fb_info *fb_info);
+extern int unlink_framebuffer(struct fb_info *fb_info);
 extern void remove_conflicting_framebuffers(struct apertures_struct *a,
                                 const char *name, bool primary);
 extern int fb_prepare_logo(struct fb_info *fb_info, int rotate);
 ,6 → 1118,7
 /* drivers/video/fbcmap.c */
 extern int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp);
+extern int fb_alloc_cmap_gfp(struct fb_cmap *cmap, int len, int transp, gfp_t flags);
 extern void fb_dealloc_cmap(struct fb_cmap *cmap);
 extern int fb_copy_cmap(const struct fb_cmap *from, struct fb_cmap *to);
 extern int fb_cmap_to_user(const struct fb_cmap *from, struct fb_cmap_user *to);
 ,6 → 1146,7
 extern const char *fb_mode_option;
 extern const struct fb_videomode vesa_modes[];
+extern const struct fb_videomode cea_modes[64];
 struct fb_modelist {
         struct list_head list;

 /drivers/include/linux/i2c-algo-bit.h
 ,7 → 15,8
     You should have received a copy of the GNU General Public License
     along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
+    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+    MA 02110-1301 USA.                                                       */
 /* ------------------------------------------------------------------------- */
 /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
 ,5 → 50,6
 int i2c_bit_add_bus(struct i2c_adapter *);
 int i2c_bit_add_numbered_bus(struct i2c_adapter *);
+extern const struct i2c_algorithm i2c_bit_algo;
 #endif /* _LINUX_I2C_ALGO_BIT_H */

 /drivers/include/linux/i2c.h
 ,12 → 17,12
     You should have received a copy of the GNU General Public License
     along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
+    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+    MA 02110-1301 USA.                                                       */
 /* ------------------------------------------------------------------------- */
 /* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
    Frodo Looijaard <frodol@dds.nl> */
 #ifndef _LINUX_I2C_H
 #define _LINUX_I2C_H
 ,6 → 32,8
 #include <linux/i2c-id.h>
 #include <linux/mod_devicetable.h>
+extern struct bus_type i2c_bus_type;
+extern struct device_type i2c_adapter_type;
 /* --- General options ------------------------------------------------ */
 ,7 → 72,7
  * The driver.owner field should be set to the module owner of this driver.
  * The driver.name field should be set to the name of this driver.
  *
- * For automatic device detection, both @detect and @address_data must
+ * For automatic device detection, both @detect and @address_list must
  * be defined. @class should also be set, otherwise only devices forced
  * with module parameters will be created. The detect function must
  * fill at least the name field of the i2c_board_info structure it is
 ,6 → 273,8
 #define I2C_CLIENT_TEN  0x10            /* we have a ten bit chip address */
                                         /* Must equal I2C_M_TEN below */
 #define I2C_CLIENT_WAKE 0x80            /* for board_info; true iff can wake */
+#define I2C_CLIENT_SCCB 0x9000          /* Use Omnivision SCCB protocol */
+                                        /* Must match I2C_M_STOP|IGNORE_NAK */
 /* i2c adapter classes (bitmask) */
 #define I2C_CLASS_HWMON         (1<<0)  /* lm_sensors, ... */

 /drivers/include/linux/ioport.h
 ,8 → 35,9
 #define IORESOURCE_BITS         0x000000ff      /* Bus-specific bits */
 #define IORESOURCE_TYPE_BITS    0x00001f00      /* Resource type */
-#define IORESOURCE_IO           0x00000100
+#define IORESOURCE_IO           0x00000100      /* PCI/ISA I/O ports */
 #define IORESOURCE_MEM          0x00000200
+#define IORESOURCE_REG          0x00000300      /* Register offsets */
 #define IORESOURCE_IRQ          0x00000400
 #define IORESOURCE_DMA          0x00000800
 #define IORESOURCE_BUS          0x00001000

 /drivers/include/linux/jiffies.h
 ,16 → 71,10
 /* a value TUSEC for TICK_USEC (can be set bij adjtimex)                */
 #define TICK_USEC_TO_NSEC(TUSEC) (SH_DIV (TUSEC * USER_HZ * 1000, ACTHZ, 8))
-#define jiffies   GetTimerTicks()
-#if (BITS_PER_LONG < 64)
-u64 get_jiffies_64(void);
-#else
 static inline u64 get_jiffies_64(void)
 {
-        return (u64)jiffies;
+    return (u64)GetTimerTicks();
 }
-#endif
 /*
  *      These inlines deal with timer wrapping correctly. You are
 ,7 → 289,13
 extern unsigned long timeval_to_jiffies(const struct timeval *value);
 extern void jiffies_to_timeval(const unsigned long jiffies,
                                struct timeval *value);
 extern clock_t jiffies_to_clock_t(unsigned long x);
+static inline clock_t jiffies_delta_to_clock_t(long delta)
+{
+        return jiffies_to_clock_t(max(0L, delta));
+}
 extern unsigned long clock_t_to_jiffies(unsigned long x);
 extern u64 jiffies_64_to_clock_t(u64 x);
 extern u64 nsec_to_clock_t(u64 x);

 /drivers/include/linux/kernel.h
 ,6 → 29,7
 #define LLONG_MAX   ((long long)(~0ULL>>1))
 #define LLONG_MIN   (-LLONG_MAX - 1)
 #define ULLONG_MAX  (~0ULL)
+#define SIZE_MAX        (~(size_t)0)
 #define ALIGN(x,a)      __ALIGN_MASK(x,(typeof(x))(a)-1)
 #define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
 ,7 → 307,10
         writel(val >> 32, addr+4);
 }
+#define swap(a, b) \
+        do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
 #define mmiowb() barrier()
 #define dev_err(dev, format, arg...)            \
 ,6 → 333,34
     unsigned int    dma_length;
 };
+struct sg_table {
+    struct scatterlist *sgl;        /* the list */
+    unsigned int nents;             /* number of mapped entries */
+    unsigned int orig_nents;        /* original size of list */
+};
+#define SG_MAX_SINGLE_ALLOC             (4096 / sizeof(struct scatterlist))
+struct scatterlist *sg_next(struct scatterlist *sg);
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)         ((sg)->length)
+#define sg_is_chain(sg)         ((sg)->page_link & 0x01)
+#define sg_is_last(sg)          ((sg)->page_link & 0x02)
+#define sg_chain_ptr(sg)        \
+        ((struct scatterlist *) ((sg)->page_link & ~0x03))
+static inline addr_t sg_page(struct scatterlist *sg)
+{
+    return (addr_t)((sg)->page_link & ~0x3);
+}
+#define for_each_sg(sglist, sg, nr, __i)        \
+        for (__i = 0, sg = (sglist); __i < (nr); __i++, sg = sg_next(sg))
 struct page
 {
     unsigned int addr;
 ,6 → 379,10
                                      */
 };
+struct pagelist {
+    dma_addr_t    *page;
+    unsigned int   nents;
+};
 #endif

 /drivers/include/linux/log2.h
 ,0 → 1,208
+/* Integer base 2 logarithm calculation
+ *
+ * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _LINUX_LOG2_H
+#define _LINUX_LOG2_H
+#include <linux/types.h>
+#include <linux/bitops.h>
+/*
+ * deal with unrepresentable constant logarithms
+ */
+extern __attribute__((const, noreturn))
+int ____ilog2_NaN(void);
+/*
+ * non-constant log of base 2 calculators
+ * - the arch may override these in asm/bitops.h if they can be implemented
+ *   more efficiently than using fls() and fls64()
+ * - the arch is not required to handle n==0 if implementing the fallback
+ */
+#ifndef CONFIG_ARCH_HAS_ILOG2_U32
+static inline __attribute__((const))
+int __ilog2_u32(u32 n)
+{
+        return fls(n) - 1;
+}
+#endif
+#ifndef CONFIG_ARCH_HAS_ILOG2_U64
+static inline __attribute__((const))
+int __ilog2_u64(u64 n)
+{
+        return fls64(n) - 1;
+}
+#endif
+/*
+ *  Determine whether some value is a power of two, where zero is
+ * *not* considered a power of two.
+ */
+static inline __attribute__((const))
+bool is_power_of_2(unsigned long n)
+{
+        return (n != 0 && ((n & (n - 1)) == 0));
+}
+/*
+ * round up to nearest power of two
+ */
+static inline __attribute__((const))
+unsigned long __roundup_pow_of_two(unsigned long n)
+{
+        return 1UL << fls_long(n - 1);
+}
+/*
+ * round down to nearest power of two
+ */
+static inline __attribute__((const))
+unsigned long __rounddown_pow_of_two(unsigned long n)
+{
+        return 1UL << (fls_long(n) - 1);
+}
+/**
+ * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value
+ * @n - parameter
+ *
+ * constant-capable log of base 2 calculation
+ * - this can be used to initialise global variables from constant data, hence
+ *   the massive ternary operator construction
+ *
+ * selects the appropriately-sized optimised version depending on sizeof(n)
+ */
+#define ilog2(n)                                \
+(                                               \
+        __builtin_constant_p(n) ? (             \
+                (n) < 1 ? ____ilog2_NaN() :     \
+                (n) & (1ULL << 63) ? 63 :       \
+                (n) & (1ULL << 62) ? 62 :       \
+                (n) & (1ULL << 61) ? 61 :       \
+                (n) & (1ULL << 60) ? 60 :       \
+                (n) & (1ULL << 59) ? 59 :       \
+                (n) & (1ULL << 58) ? 58 :       \
+                (n) & (1ULL << 57) ? 57 :       \
+                (n) & (1ULL << 56) ? 56 :       \
+                (n) & (1ULL << 55) ? 55 :       \
+                (n) & (1ULL << 54) ? 54 :       \
+                (n) & (1ULL << 53) ? 53 :       \
+                (n) & (1ULL << 52) ? 52 :       \
+                (n) & (1ULL << 51) ? 51 :       \
+                (n) & (1ULL << 50) ? 50 :       \
+                (n) & (1ULL << 49) ? 49 :       \
+                (n) & (1ULL << 48) ? 48 :       \
+                (n) & (1ULL << 47) ? 47 :       \
+                (n) & (1ULL << 46) ? 46 :       \
+                (n) & (1ULL << 45) ? 45 :       \
+                (n) & (1ULL << 44) ? 44 :       \
+                (n) & (1ULL << 43) ? 43 :       \
+                (n) & (1ULL << 42) ? 42 :       \
+                (n) & (1ULL << 41) ? 41 :       \
+                (n) & (1ULL << 40) ? 40 :       \
+                (n) & (1ULL << 39) ? 39 :       \
+                (n) & (1ULL << 38) ? 38 :       \
+                (n) & (1ULL << 37) ? 37 :       \
+                (n) & (1ULL << 36) ? 36 :       \
+                (n) & (1ULL << 35) ? 35 :       \
+                (n) & (1ULL << 34) ? 34 :       \
+                (n) & (1ULL << 33) ? 33 :       \
+                (n) & (1ULL << 32) ? 32 :       \
+                (n) & (1ULL << 31) ? 31 :       \
+                (n) & (1ULL << 30) ? 30 :       \
+                (n) & (1ULL << 29) ? 29 :       \
+                (n) & (1ULL << 28) ? 28 :       \
+                (n) & (1ULL << 27) ? 27 :       \
+                (n) & (1ULL << 26) ? 26 :       \
+                (n) & (1ULL << 25) ? 25 :       \
+                (n) & (1ULL << 24) ? 24 :       \
+                (n) & (1ULL << 23) ? 23 :       \
+                (n) & (1ULL << 22) ? 22 :       \
+                (n) & (1ULL << 21) ? 21 :       \
+                (n) & (1ULL << 20) ? 20 :       \
+                (n) & (1ULL << 19) ? 19 :       \
+                (n) & (1ULL << 18) ? 18 :       \
+                (n) & (1ULL << 17) ? 17 :       \
+                (n) & (1ULL << 16) ? 16 :       \
+                (n) & (1ULL << 15) ? 15 :       \
+                (n) & (1ULL << 14) ? 14 :       \
+                (n) & (1ULL << 13) ? 13 :       \
+                (n) & (1ULL << 12) ? 12 :       \
+                (n) & (1ULL << 11) ? 11 :       \
+                (n) & (1ULL << 10) ? 10 :       \
+                (n) & (1ULL <<  9) ?  9 :       \
+                (n) & (1ULL <<  8) ?  8 :       \
+                (n) & (1ULL <<  7) ?  7 :       \
+                (n) & (1ULL <<  6) ?  6 :       \
+                (n) & (1ULL <<  5) ?  5 :       \
+                (n) & (1ULL <<  4) ?  4 :       \
+                (n) & (1ULL <<  3) ?  3 :       \
+                (n) & (1ULL <<  2) ?  2 :       \
+                (n) & (1ULL <<  1) ?  1 :       \
+                (n) & (1ULL <<  0) ?  0 :       \
+                ____ilog2_NaN()                 \
+                                   ) :          \
+        (sizeof(n) <= 4) ?                      \
+        __ilog2_u32(n) :                        \
+        __ilog2_u64(n)                          \
+ )
+/**
+ * roundup_pow_of_two - round the given value up to nearest power of two
+ * @n - parameter
+ *
+ * round the given value up to the nearest power of two
+ * - the result is undefined when n == 0
+ * - this can be used to initialise global variables from constant data
+ */
+#define roundup_pow_of_two(n)                   \
+(                                               \
+        __builtin_constant_p(n) ? (             \
+                (n == 1) ? 1 :                  \
+                (1UL << (ilog2((n) - 1) + 1))   \
+                                   ) :          \
+        __roundup_pow_of_two(n)                 \
+ )
+/**
+ * rounddown_pow_of_two - round the given value down to nearest power of two
+ * @n - parameter
+ *
+ * round the given value down to the nearest power of two
+ * - the result is undefined when n == 0
+ * - this can be used to initialise global variables from constant data
+ */
+#define rounddown_pow_of_two(n)                 \
+(                                               \
+        __builtin_constant_p(n) ? (             \
+                (1UL << ilog2(n))) :            \
+        __rounddown_pow_of_two(n)               \
+ )
+/**
+ * order_base_2 - calculate the (rounded up) base 2 order of the argument
+ * @n: parameter
+ *
+ * The first few values calculated by this routine:
+ *  ob2(0) = 0
+ *  ob2(1) = 0
+ *  ob2(2) = 1
+ *  ob2(3) = 2
+ *  ob2(4) = 2
+ *  ob2(5) = 3
+ *  ... and so on.
+ */
+#define order_base_2(n) ilog2(roundup_pow_of_two(n))
+#endif /* _LINUX_LOG2_H */

 /drivers/include/linux/math64.h
 ,0 → 1,121
+#ifndef _LINUX_MATH64_H
+#define _LINUX_MATH64_H
+#include <linux/types.h>
+#include <asm/div64.h>
+#if BITS_PER_LONG == 64
+#define div64_long(x,y) div64_s64((x),(y))
+/**
+ * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
+ *
+ * This is commonly provided by 32bit archs to provide an optimized 64bit
+ * divide.
+ */
+static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+        *remainder = dividend % divisor;
+        return dividend / divisor;
+}
+/**
+ * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
+ */
+static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
+{
+        *remainder = dividend % divisor;
+        return dividend / divisor;
+}
+/**
+ * div64_u64 - unsigned 64bit divide with 64bit divisor
+ */
+static inline u64 div64_u64(u64 dividend, u64 divisor)
+{
+        return dividend / divisor;
+}
+/**
+ * div64_s64 - signed 64bit divide with 64bit divisor
+ */
+static inline s64 div64_s64(s64 dividend, s64 divisor)
+{
+        return dividend / divisor;
+}
+#elif BITS_PER_LONG == 32
+#define div64_long(x,y) div_s64((x),(y))
+#ifndef div_u64_rem
+static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+        *remainder = do_div(dividend, divisor);
+        return dividend;
+}
+#endif
+#ifndef div_s64_rem
+extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
+#endif
+#ifndef div64_u64
+extern u64 div64_u64(u64 dividend, u64 divisor);
+#endif
+#ifndef div64_s64
+extern s64 div64_s64(s64 dividend, s64 divisor);
+#endif
+#endif /* BITS_PER_LONG */
+/**
+ * div_u64 - unsigned 64bit divide with 32bit divisor
+ *
+ * This is the most common 64bit divide and should be used if possible,
+ * as many 32bit archs can optimize this variant better than a full 64bit
+ * divide.
+ */
+#ifndef div_u64
+static inline u64 div_u64(u64 dividend, u32 divisor)
+{
+        u32 remainder;
+        return div_u64_rem(dividend, divisor, &remainder);
+}
+#endif
+/**
+ * div_s64 - signed 64bit divide with 32bit divisor
+ */
+#ifndef div_s64
+static inline s64 div_s64(s64 dividend, s32 divisor)
+{
+        s32 remainder;
+        return div_s64_rem(dividend, divisor, &remainder);
+}
+#endif
+u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder);
+static __always_inline u32
+__iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder)
+{
+        u32 ret = 0;
+        while (dividend >= divisor) {
+                /* The following asm() prevents the compiler from
+                   optimising this loop into a modulo operation.  */
+                asm("" : "+rm"(dividend));
+                dividend -= divisor;
+                ret++;
+        }
+        *remainder = dividend;
+        return ret;
+}
+#endif /* _LINUX_MATH64_H */

 /drivers/include/linux/mod_devicetable.h
 ,6 → 78,9
  *      of a given interface; other interfaces may support other classes.
  * @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass.
  * @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass.
+ * @bInterfaceNumber: Number of interface; composite devices may use
+ *      fixed interface numbers to differentiate between vendor-specific
+ *      interfaces.
  * @driver_info: Holds information used by the driver.  Usually it holds
  *      a pointer to a descriptor understood by the driver, or perhaps
  *      device flags.
 ,12 → 133,15
 #define USB_DEVICE_ID_MATCH_INT_CLASS           0x0080
 #define USB_DEVICE_ID_MATCH_INT_SUBCLASS        0x0100
 #define USB_DEVICE_ID_MATCH_INT_PROTOCOL        0x0200
+#define USB_DEVICE_ID_MATCH_INT_NUMBER          0x0400
 #define HID_ANY_ID                              (~0)
+#define HID_BUS_ANY                             0xffff
+#define HID_GROUP_ANY                           0x0000
 struct hid_device_id {
         __u16 bus;
-        __u16 pad1;
+        __u16 group;
         __u32 vendor;
         __u32 product;
         kernel_ulong_t driver_data
 ,7 → 228,7
         char    type[32];
         char    compatible[128];
 #ifdef __KERNEL__
-        void    *data;
+        const void *data;
 #else
         kernel_ulong_t data;
 #endif

 /drivers/include/linux/module.h
 ,15 → 11,14
 #include <linux/kernel.h>
-#define EXPORT_SYMBOL(x)
 #define MODULE_FIRMWARE(x)
+#define MODULE_AUTHOR(x);
+#define MODULE_DESCRIPTION(x);
+#define MODULE_LICENSE(x);
+#define MODULE_PARM_DESC(_parm, desc)
-#define MODULE_AUTHOR(x)
-#define MODULE_DESCRIPTION(x)
-#define MODULE_LICENSE(x)
 struct module {};
 #endif /* _LINUX_MODULE_H */

/drivers/include/linux/moduleparam.h
0,0 → 1,3

#define MODULE_PARM_DESC(_parm, desc)
#define module_param_named(name, value, type, perm)

 /drivers/include/linux/pci.h
 ,11 → 13,10
  *      PCI to PCI Bridge Specification
  *      PCI System Design Guide
  */
 #ifndef LINUX_PCI_H
 #define LINUX_PCI_H
-#include <types.h>
+#include <linux/types.h>
 #include <list.h>
 #include <linux/pci_regs.h>     /* The pci register defines */
 #include <ioport.h>
 ,6 → 275,20
 #define PCI_D3cold      ((pci_power_t __force) 4)
 #define PCI_UNKNOWN     ((pci_power_t __force) 5)
 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
+/* Remember to update this when the list above changes! */
+extern const char *pci_power_names[];
+static inline const char *pci_power_name(pci_power_t state)
+{
+        return pci_power_names[1 + (int) state];
+}
+#define PCI_PM_D2_DELAY         200
+#define PCI_PM_D3_WAIT          10
+#define PCI_PM_D3COLD_WAIT      100
+#define PCI_PM_BUS_WAIT         50
 /** The pci_channel state describes connectivity between the CPU and
  *  the pci device.  If some PCI bus between here and the pci device
  *  has crashed or locked up, this info is reflected here.
 ,9 → 359,10
         u8              revision;       /* PCI revision, low byte of class word */
         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
         u8              pcie_cap;       /* PCI-E capability offset */
-        u8              pcie_type;      /* PCI-E device/port type */
+        u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
         u8              rom_base_reg;   /* which config register controls the ROM */
         u8              pin;            /* which interrupt pin this device uses */
+        u16             pcie_flags_reg; /* cached PCI-E Capabilities Register */
  //   struct pci_driver *driver;  /* which driver has allocated this device */
     uint64_t     dma_mask;   /* Mask of the bits of bus address this
 ,14 → 381,25
     unsigned int    pme_support:5;  /* Bitmask of states from which PME#
                        can be generated */
         unsigned int    pme_interrupt:1;
+        unsigned int    pme_poll:1;     /* Poll device's PME status bit */
     unsigned int    d1_support:1;   /* Low power state D1 is supported */
     unsigned int    d2_support:1;   /* Low power state D2 is supported */
-    unsigned int    no_d1d2:1;  /* Only allow D0 and D3 */
+        unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
+        unsigned int    no_d3cold:1;    /* D3cold is forbidden */
+        unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
                                                    decoding during bar sizing */
         unsigned int    wakeup_prepared:1;
+        unsigned int    runtime_d3cold:1;       /* whether go through runtime
+                                                   D3cold, not set for devices
+                                                   powered on/off by the
+                                                   corresponding bridge */
         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
+        unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
+#ifdef CONFIG_PCIEASPM
+        struct pcie_link_state  *link_state;    /* ASPM link state. */
+#endif
         pci_channel_state_t error_state;        /* current connectivity state */
     struct  device  dev;        /* Generic device interface */
 ,7 → 412,6
      */
     unsigned int    irq;
     struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
-        resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
     /* These fields are used by common fixups */
     unsigned int    transparent:1;  /* Transparent PCI bridge */
 ,7 → 420,7
     unsigned int    is_added:1;
     unsigned int    is_busmaster:1; /* device is busmaster */
     unsigned int    no_msi:1;   /* device may not use msi */
-    unsigned int    block_ucfg_access:1;    /* userspace config space access is blocked */
+        unsigned int    block_cfg_access:1;     /* config space access is blocked */
     unsigned int    broken_parity_status:1; /* Device generates false positive parity */
     unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
     unsigned int    msi_enabled:1;
 ,15 → 435,15
     unsigned int    is_virtfn:1;
         unsigned int    reset_fn:1;
         unsigned int    is_hotplug_bridge:1;
+        unsigned int    __aer_firmware_first_valid:1;
+        unsigned int    __aer_firmware_first:1;
+        unsigned int    broken_intx_masking:1;
+        unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
 //    pci_dev_flags_t dev_flags;
-//    atomic_t    enable_cnt;   /* pci_enable_device has been called */
+        atomic_t        enable_cnt;     /* pci_enable_device has been called */
-//    u32     saved_config_space[16]; /* config space saved at suspend time */
-//    struct hlist_head saved_cap_space;
-//    struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
-//    int rom_attr_enabled;       /* has display of the rom attribute been enabled? */
-//    struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
-//    struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
 };
 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
 ,6 → 467,7
     struct list_head slots;     /* list of slots on this bus */
     struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
     struct list_head resources; /* address space routed to this bus */
+        struct resource busn_res;       /* bus numbers routed to this bus */
     struct pci_ops  *ops;       /* configuration access functions */
     void        *sysdata;   /* hook for sys-specific extension */
 ,8 → 475,6
     unsigned char   number;     /* bus number */
     unsigned char   primary;    /* number of primary bridge */
-    unsigned char   secondary;  /* number of secondary bridge */
-    unsigned char   subordinate;    /* max number of subordinate buses */
     unsigned char   max_bus_speed;  /* enum pci_bus_speed */
     unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
 ,6 → 594,16
     return !!pci_pcie_cap(dev);
 }
+/**
+ * pci_pcie_type - get the PCIe device/port type
+ * @dev: PCI device
+ */
+static inline int pci_pcie_type(const struct pci_dev *dev)
+{
+        return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
+}
 static inline int pci_iov_init(struct pci_dev *dev)
 {
     return -ENODEV;

 /drivers/include/linux/pci_regs.h
 ,6 → 26,7
  * Under PCI, each device has 256 bytes of configuration address space,
  * of which the first 64 bytes are standardized as follows:
  */
+#define PCI_STD_HEADER_SIZEOF   64
 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 #define PCI_COMMAND             0x04    /* 16 bits */
 ,7 → 126,8
 #define  PCI_IO_RANGE_TYPE_MASK 0x0fUL  /* I/O bridging type */
 #define  PCI_IO_RANGE_TYPE_16   0x00
 #define  PCI_IO_RANGE_TYPE_32   0x01
-#define  PCI_IO_RANGE_MASK      (~0x0fUL)
+#define  PCI_IO_RANGE_MASK      (~0x0fUL) /* Standard 4K I/O windows */
+#define  PCI_IO_1K_RANGE_MASK   (~0x03UL) /* Intel 1K I/O windows */
 #define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
 #define PCI_MEMORY_BASE         0x20    /* Memory range behind */
 #define PCI_MEMORY_LIMIT        0x22
 ,9 → 211,12
 #define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
 #define  PCI_CAP_ID_SSVID       0x0D    /* Bridge subsystem vendor/device ID */
 #define  PCI_CAP_ID_AGP3        0x0E    /* AGP Target PCI-PCI bridge */
+#define  PCI_CAP_ID_SECDEV      0x0F    /* Secure Device */
 #define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
 #define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
+#define  PCI_CAP_ID_SATA        0x12    /* SATA Data/Index Conf. */
 #define  PCI_CAP_ID_AF          0x13    /* PCI Advanced Features */
+#define  PCI_CAP_ID_MAX         PCI_CAP_ID_AF
 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 #define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF          4
 ,6 → 281,7
 #define  PCI_VPD_ADDR_MASK      0x7fff  /* Address mask */
 #define  PCI_VPD_ADDR_F         0x8000  /* Write 0, 1 indicates completion */
 #define PCI_VPD_DATA            4       /* 32-bits of data returned here */
+#define PCI_CAP_VPD_SIZEOF      8
 /* Slot Identification */
 ,8 → 303,10
 #define PCI_MSI_ADDRESS_HI      8       /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
 #define PCI_MSI_DATA_32         8       /* 16 bits of data for 32-bit devices */
 #define PCI_MSI_MASK_32         12      /* Mask bits register for 32-bit devices */
+#define PCI_MSI_PENDING_32      16      /* Pending intrs for 32-bit devices */
 #define PCI_MSI_DATA_64         12      /* 16 bits of data for 64-bit devices */
 #define PCI_MSI_MASK_64         16      /* Mask bits register for 64-bit devices */
+#define PCI_MSI_PENDING_64      20      /* Pending intrs for 64-bit devices */
 /* MSI-X registers */
 #define PCI_MSIX_FLAGS          2
 ,6 → 316,7
 #define PCI_MSIX_TABLE          4
 #define PCI_MSIX_PBA            8
 #define PCI_MSIX_FLAGS_BIRMASK  (7 << 0)
+#define PCI_CAP_MSIX_SIZEOF     12      /* size of MSIX registers */
 /* MSI-X entry's format */
 #define PCI_MSIX_ENTRY_SIZE             16
 ,6 → 347,7
 #define  PCI_AF_CTRL_FLR        0x01
 #define PCI_AF_STATUS           5
 #define  PCI_AF_STATUS_TP       0x01
+#define PCI_CAP_AF_SIZEOF       6       /* size of AF registers */
 /* PCI-X registers */
 ,6 → 384,10
 #define  PCI_X_STATUS_SPL_ERR   0x20000000      /* Rcvd Split Completion Error Msg */
 #define  PCI_X_STATUS_266MHZ    0x40000000      /* 266 MHz capable */
 #define  PCI_X_STATUS_533MHZ    0x80000000      /* 533 MHz capable */
+#define PCI_X_ECC_CSR           8       /* ECC control and status */
+#define PCI_CAP_PCIX_SIZEOF_V0  8       /* size of registers for Version 0 */
+#define PCI_CAP_PCIX_SIZEOF_V1  24      /* size for Version 1 */
+#define PCI_CAP_PCIX_SIZEOF_V2  PCI_CAP_PCIX_SIZEOF_V1  /* Same for v2 */
 /* PCI Bridge Subsystem ID registers */
 ,8 → 405,9
 #define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
+#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIE Bridge */
 #define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
-#define  PCI_EXP_TYPE_RC_EC     0x10    /* Root Complex Event Collector */
+#define  PCI_EXP_TYPE_RC_EC     0xa     /* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP          4       /* Device capabilities */
 ,6 → 476,7
 #define  PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
 #define  PCI_EXP_LNKSTA_LBMS    0x4000  /* Link Bandwidth Management Status */
 #define  PCI_EXP_LNKSTA_LABS    0x8000  /* Link Autonomous Bandwidth Status */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1  20      /* v1 endpoints end here */
 #define PCI_EXP_SLTCAP          20      /* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_ABP     0x00000001 /* Attention Button Present */
 #define  PCI_EXP_SLTCAP_PCP     0x00000002 /* Power Controller Present */
 ,6 → 522,12
 #define PCI_EXP_RTSTA           32      /* Root Status */
 #define PCI_EXP_RTSTA_PME       0x10000 /* PME status */
 #define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */
+/*
+ * Note that the following PCI Express 'Capability Structure' registers
+ * were introduced with 'Capability Version' 0x2 (v2).  These registers
+ * do not exist on devices with Capability Version 1.  Use pci_pcie_cap2()
+ * to use these fields safely.
+ */
 #define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
 #define  PCI_EXP_DEVCAP2_ARI    0x20    /* Alternative Routing-ID */
 #define  PCI_EXP_DEVCAP2_LTR    0x800   /* Latency tolerance reporting */
 ,7 → 542,14
 #define  PCI_EXP_OBFF_MSGA_EN   0x2000  /* OBFF enable with Message type A */
 #define  PCI_EXP_OBFF_MSGB_EN   0x4000  /* OBFF enable with Message type B */
 #define  PCI_EXP_OBFF_WAKE_EN   0x6000  /* OBFF using WAKE# signaling */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2  44      /* v2 endpoints end here */
+#define PCI_EXP_LNKCAP2         44      /* Link Capability 2 */
+#define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */
+#define  PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
+#define PCI_EXP_LNKSTA2         50      /* Link Status 2 */
 #define PCI_EXP_SLTCTL2         56      /* Slot Control 2 */
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 ,21 → 557,43
 #define PCI_EXT_CAP_VER(header)         ((header >> 16) & 0xf)
 #define PCI_EXT_CAP_NEXT(header)        ((header >> 20) & 0xffc)
-#define PCI_EXT_CAP_ID_ERR      1
-#define PCI_EXT_CAP_ID_VC       2
-#define PCI_EXT_CAP_ID_DSN      3
-#define PCI_EXT_CAP_ID_PWR      4
-#define PCI_EXT_CAP_ID_VNDR     11
-#define PCI_EXT_CAP_ID_ACS      13
-#define PCI_EXT_CAP_ID_ARI      14
-#define PCI_EXT_CAP_ID_ATS      15
-#define PCI_EXT_CAP_ID_SRIOV    16
-#define PCI_EXT_CAP_ID_LTR      24
+#define PCI_EXT_CAP_ID_ERR      0x01    /* Advanced Error Reporting */
+#define PCI_EXT_CAP_ID_VC       0x02    /* Virtual Channel Capability */
+#define PCI_EXT_CAP_ID_DSN      0x03    /* Device Serial Number */
+#define PCI_EXT_CAP_ID_PWR      0x04    /* Power Budgeting */
+#define PCI_EXT_CAP_ID_RCLD     0x05    /* Root Complex Link Declaration */
+#define PCI_EXT_CAP_ID_RCILC    0x06    /* Root Complex Internal Link Control */
+#define PCI_EXT_CAP_ID_RCEC     0x07    /* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_MFVC     0x08    /* Multi-Function VC Capability */
+#define PCI_EXT_CAP_ID_VC9      0x09    /* same as _VC */
+#define PCI_EXT_CAP_ID_RCRB     0x0A    /* Root Complex RB? */
+#define PCI_EXT_CAP_ID_VNDR     0x0B    /* Vendor Specific */
+#define PCI_EXT_CAP_ID_CAC      0x0C    /* Config Access - obsolete */
+#define PCI_EXT_CAP_ID_ACS      0x0D    /* Access Control Services */
+#define PCI_EXT_CAP_ID_ARI      0x0E    /* Alternate Routing ID */
+#define PCI_EXT_CAP_ID_ATS      0x0F    /* Address Translation Services */
+#define PCI_EXT_CAP_ID_SRIOV    0x10    /* Single Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_MRIOV    0x11    /* Multi Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_MCAST    0x12    /* Multicast */
+#define PCI_EXT_CAP_ID_PRI      0x13    /* Page Request Interface */
+#define PCI_EXT_CAP_ID_AMD_XXX  0x14    /* reserved for AMD */
+#define PCI_EXT_CAP_ID_REBAR    0x15    /* resizable BAR */
+#define PCI_EXT_CAP_ID_DPA      0x16    /* dynamic power alloc */
+#define PCI_EXT_CAP_ID_TPH      0x17    /* TPH request */
+#define PCI_EXT_CAP_ID_LTR      0x18    /* latency tolerance reporting */
+#define PCI_EXT_CAP_ID_SECPCI   0x19    /* Secondary PCIe */
+#define PCI_EXT_CAP_ID_PMUX     0x1A    /* Protocol Multiplexing */
+#define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
+#define PCI_EXT_CAP_ID_MAX      PCI_EXT_CAP_ID_PASID
+#define PCI_EXT_CAP_DSN_SIZEOF  12
+#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
 #define  PCI_ERR_UNC_TRAIN      0x00000001      /* Training */
 #define  PCI_ERR_UNC_DLP        0x00000010      /* Data Link Protocol */
+#define  PCI_ERR_UNC_SURPDN     0x00000020      /* Surprise Down */
 #define  PCI_ERR_UNC_POISON_TLP 0x00001000      /* Poisoned TLP */
 #define  PCI_ERR_UNC_FCP        0x00002000      /* Flow Control Protocol */
 #define  PCI_ERR_UNC_COMP_TIME  0x00004000      /* Completion Timeout */
 ,6 → 603,11
 #define  PCI_ERR_UNC_MALF_TLP   0x00040000      /* Malformed TLP */
 #define  PCI_ERR_UNC_ECRC       0x00080000      /* ECRC Error Status */
 #define  PCI_ERR_UNC_UNSUP      0x00100000      /* Unsupported Request */
+#define  PCI_ERR_UNC_ACSV       0x00200000      /* ACS Violation */
+#define  PCI_ERR_UNC_INTN       0x00400000      /* internal error */
+#define  PCI_ERR_UNC_MCBTLP     0x00800000      /* MC blocked TLP */
+#define  PCI_ERR_UNC_ATOMEG     0x01000000      /* Atomic egress blocked */
+#define  PCI_ERR_UNC_TLPPRE     0x02000000      /* TLP prefix blocked */
 #define PCI_ERR_UNCOR_MASK      8       /* Uncorrectable Error Mask */
         /* Same bits as above */
 #define PCI_ERR_UNCOR_SEVER     12      /* Uncorrectable Error Severity */
 ,6 → 618,9
 #define  PCI_ERR_COR_BAD_DLLP   0x00000080      /* Bad DLLP Status */
 #define  PCI_ERR_COR_REP_ROLL   0x00000100      /* REPLAY_NUM Rollover */
 #define  PCI_ERR_COR_REP_TIMER  0x00001000      /* Replay Timer Timeout */
+#define  PCI_ERR_COR_ADV_NFAT   0x00002000      /* Advisory Non-Fatal */
+#define  PCI_ERR_COR_INTERNAL   0x00004000      /* Corrected Internal */
+#define  PCI_ERR_COR_LOG_OVER   0x00008000      /* Header Log Overflow */
 #define PCI_ERR_COR_MASK        20      /* Correctable Error Mask */
         /* Same bits as above */
 #define PCI_ERR_CAP             24      /* Advanced Error Capabilities */
 ,12 → 652,18
 /* Virtual Channel */
 #define PCI_VC_PORT_REG1        4
+#define  PCI_VC_REG1_EVCC       0x7     /* extended vc count */
 #define PCI_VC_PORT_REG2        8
+#define  PCI_VC_REG2_32_PHASE   0x2
+#define  PCI_VC_REG2_64_PHASE   0x4
+#define  PCI_VC_REG2_128_PHASE  0x8
 #define PCI_VC_PORT_CTRL        12
 #define PCI_VC_PORT_STATUS      14
 #define PCI_VC_RES_CAP          16
 #define PCI_VC_RES_CTRL         20
 #define PCI_VC_RES_STATUS       26
+#define PCI_CAP_VC_BASE_SIZEOF          0x10
+#define PCI_CAP_VC_PER_VC_SIZEOF        0x0C
 /* Power Budgeting */
 #define PCI_PWR_DSR             4       /* Data Select Register */
 ,7 → 676,14
 #define  PCI_PWR_DATA_RAIL(x)   (((x) >> 18) & 7)   /* Power Rail */
 #define PCI_PWR_CAP             12      /* Capability */
 #define  PCI_PWR_CAP_BUDGET(x)  ((x) & 1)       /* Included in system budget */
+#define PCI_EXT_CAP_PWR_SIZEOF  16
+/* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
+#define PCI_VNDR_HEADER         4       /* Vendor-Specific Header */
+#define  PCI_VNDR_HEADER_ID(x)  ((x) & 0xffff)
+#define  PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf)
+#define  PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff)
 /*
  * Hypertransport sub capability types
  *
 ,6 → 715,8
 #define HT_CAPTYPE_ERROR_RETRY  0xC0    /* Retry on error configuration */
 #define HT_CAPTYPE_GEN3         0xD0    /* Generation 3 hypertransport configuration */
 #define HT_CAPTYPE_PM           0xE0    /* Hypertransport powermanagement configuration */
+#define HT_CAP_SIZEOF_LONG      28      /* slave & primary */
+#define HT_CAP_SIZEOF_SHORT     24      /* host & secondary */
 /* Alternative Routing-ID Interpretation */
 #define PCI_ARI_CAP             0x04    /* ARI Capability Register */
 ,6 → 727,7
 #define  PCI_ARI_CTRL_MFVC      0x0001  /* MFVC Function Groups Enable */
 #define  PCI_ARI_CTRL_ACS       0x0002  /* ACS Function Groups Enable */
 #define  PCI_ARI_CTRL_FG(x)     (((x) >> 4) & 7) /* Function Group */
+#define PCI_EXT_CAP_ARI_SIZEOF  8
 /* Address Translation Service */
 #define PCI_ATS_CAP             0x04    /* ATS Capability Register */
 ,26 → 737,29
 #define  PCI_ATS_CTRL_ENABLE    0x8000  /* ATS Enable */
 #define  PCI_ATS_CTRL_STU(x)    ((x) & 0x1f)    /* Smallest Translation Unit */
 #define  PCI_ATS_MIN_STU        12      /* shift of minimum STU block */
+#define PCI_EXT_CAP_ATS_SIZEOF  8
 /* Page Request Interface */
-#define PCI_PRI_CAP             0x13    /* PRI capability ID */
-#define PCI_PRI_CONTROL_OFF     0x04    /* Offset of control register */
-#define PCI_PRI_STATUS_OFF      0x06    /* Offset of status register */
-#define PCI_PRI_ENABLE          0x0001  /* Enable mask */
-#define PCI_PRI_RESET           0x0002  /* Reset bit mask */
-#define PCI_PRI_STATUS_RF       0x0001  /* Request Failure */
-#define PCI_PRI_STATUS_UPRGI    0x0002  /* Unexpected PRG index */
-#define PCI_PRI_STATUS_STOPPED  0x0100  /* PRI Stopped */
-#define PCI_PRI_MAX_REQ_OFF     0x08    /* Cap offset for max reqs supported */
-#define PCI_PRI_ALLOC_REQ_OFF   0x0c    /* Cap offset for max reqs allowed */
+#define PCI_PRI_CTRL            0x04    /* PRI control register */
+#define  PCI_PRI_CTRL_ENABLE    0x01    /* Enable */
+#define  PCI_PRI_CTRL_RESET     0x02    /* Reset */
+#define PCI_PRI_STATUS          0x06    /* PRI status register */
+#define  PCI_PRI_STATUS_RF      0x001   /* Response Failure */
+#define  PCI_PRI_STATUS_UPRGI   0x002   /* Unexpected PRG index */
+#define  PCI_PRI_STATUS_STOPPED 0x100   /* PRI Stopped */
+#define PCI_PRI_MAX_REQ         0x08    /* PRI max reqs supported */
+#define PCI_PRI_ALLOC_REQ       0x0c    /* PRI max reqs allowed */
+#define PCI_EXT_CAP_PRI_SIZEOF  16
 /* PASID capability */
-#define PCI_PASID_CAP           0x1b    /* PASID capability ID */
-#define PCI_PASID_CAP_OFF       0x04    /* PASID feature register */
-#define PCI_PASID_CONTROL_OFF   0x06    /* PASID control register */
-#define PCI_PASID_ENABLE        0x01    /* Enable/Supported bit */
-#define PCI_PASID_EXEC          0x02    /* Exec permissions Enable/Supported */
-#define PCI_PASID_PRIV          0x04    /* Priviledge Mode Enable/Support */
+#define PCI_PASID_CAP           0x04    /* PASID feature register */
+#define  PCI_PASID_CAP_EXEC     0x02    /* Exec permissions Supported */
+#define  PCI_PASID_CAP_PRIV     0x04    /* Priviledge Mode Supported */
+#define PCI_PASID_CTRL          0x06    /* PASID control register */
+#define  PCI_PASID_CTRL_ENABLE  0x01    /* Enable bit */
+#define  PCI_PASID_CTRL_EXEC    0x02    /* Exec permissions Enable */
+#define  PCI_PASID_CTRL_PRIV    0x04    /* Priviledge Mode Enable */
+#define PCI_EXT_CAP_PASID_SIZEOF        8
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */
 ,6 → 791,7
 #define  PCI_SRIOV_VFM_MI       0x1     /* Dormant.MigrateIn */
 #define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
 #define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
+#define PCI_EXT_CAP_SRIOV_SIZEOF 64
 #define PCI_LTR_MAX_SNOOP_LAT   0x4
 #define PCI_LTR_MAX_NOSNOOP_LAT 0x6
 ,6 → 798,7
 #define  PCI_LTR_VALUE_MASK     0x000003ff
 #define  PCI_LTR_SCALE_MASK     0x00001c00
 #define  PCI_LTR_SCALE_SHIFT    10
+#define PCI_EXT_CAP_LTR_SIZEOF  8
 /* Access Control Service */
 #define PCI_ACS_CAP             0x04    /* ACS Capability Register */
 ,7 → 809,38
 #define  PCI_ACS_UF             0x10    /* Upstream Forwarding */
 #define  PCI_ACS_EC             0x20    /* P2P Egress Control */
 #define  PCI_ACS_DT             0x40    /* Direct Translated P2P */
+#define PCI_ACS_EGRESS_BITS     0x05    /* ACS Egress Control Vector Size */
 #define PCI_ACS_CTRL            0x06    /* ACS Control Register */
 #define PCI_ACS_EGRESS_CTL_V    0x08    /* ACS Egress Control Vector */
+#define PCI_VSEC_HDR            4       /* extended cap - vendor specific */
+#define  PCI_VSEC_HDR_LEN_SHIFT 20      /* shift for length field */
+/* sata capability */
+#define PCI_SATA_REGS           4       /* SATA REGs specifier */
+#define  PCI_SATA_REGS_MASK     0xF     /* location - BAR#/inline */
+#define  PCI_SATA_REGS_INLINE   0xF     /* REGS in config space */
+#define PCI_SATA_SIZEOF_SHORT   8
+#define PCI_SATA_SIZEOF_LONG    16
+/* resizable BARs */
+#define PCI_REBAR_CTRL          8       /* control register */
+#define  PCI_REBAR_CTRL_NBAR_MASK       (7 << 5)        /* mask for # bars */
+#define  PCI_REBAR_CTRL_NBAR_SHIFT      5       /* shift for # bars */
+/* dynamic power allocation */
+#define PCI_DPA_CAP             4       /* capability register */
+#define  PCI_DPA_CAP_SUBSTATE_MASK      0x1F    /* # substates - 1 */
+#define PCI_DPA_BASE_SIZEOF     16      /* size with 0 substates */
+/* TPH Requester */
+#define PCI_TPH_CAP             4       /* capability register */
+#define  PCI_TPH_CAP_LOC_MASK   0x600   /* location mask */
+#define   PCI_TPH_LOC_NONE      0x000   /* no location */
+#define   PCI_TPH_LOC_CAP       0x200   /* in capability */
+#define   PCI_TPH_LOC_MSIX      0x400   /* in MSI-X */
+#define PCI_TPH_CAP_ST_MASK     0x07FF0000      /* st table mask */
+#define PCI_TPH_CAP_ST_SHIFT    16      /* st table shift */
+#define PCI_TPH_BASE_SIZEOF     12      /* size with no st table */
 #endif /* LINUX_PCI_REGS_H */

 /drivers/include/linux/poison.h
 ,12 → 40,6
 #define RED_INACTIVE    0x09F911029D74E35BULL   /* when obj is inactive */
 #define RED_ACTIVE      0xD84156C5635688C0ULL   /* when obj is active */
-#ifdef CONFIG_PHYS_ADDR_T_64BIT
-#define MEMBLOCK_INACTIVE       0x3a84fb0144c9e71bULL
-#else
-#define MEMBLOCK_INACTIVE       0x44c9e71bUL
-#endif
 #define SLUB_RED_INACTIVE       0xbb
 #define SLUB_RED_ACTIVE         0xcc

 /drivers/include/linux/spinlock.h
 ,4 → 344,10
 # include <linux/spinlock_api_up.h>
 #endif
+struct rw_semaphore {
+    signed long             count;
+    spinlock_t              wait_lock;
+    struct list_head        wait_list;
+};
 #endif /* __LINUX_SPINLOCK_H */

 /drivers/include/linux/spinlock_api_up.h
 ,7 → 31,7
   do { local_bh_disable(); __LOCK(lock); } while (0)
 #define __LOCK_IRQ(lock) \
-  do { local_irq_disable(); __LOCK(lock); } while (0)
+  do { asm volatile ("cli \n"); __LOCK(lock); } while (0)
 #define __LOCK_IRQSAVE(lock, flags) \
   do {                              \
 ,7 → 51,7
           __release(lock); (void)(lock); } while (0)
 #define __UNLOCK_IRQ(lock) \
-  do { local_irq_enable(); __UNLOCK(lock); } while (0)
+  do { asm volatile ("sti \n"); __UNLOCK(lock); } while (0)
 #define __UNLOCK_IRQRESTORE(lock, flags)    \
   do {                                      \

 /drivers/include/linux/types.h
 ,7 → 24,8
 typedef __kernel_dev_t          dev_t;
 typedef __kernel_ino_t          ino_t;
 typedef __kernel_mode_t         mode_t;
-typedef __kernel_nlink_t        nlink_t;
+typedef unsigned short          umode_t;
+typedef __u32                   nlink_t;
 typedef __kernel_off_t          off_t;
 typedef __kernel_pid_t          pid_t;
 typedef __kernel_daddr_t        daddr_t;
 ,9 → 253,7
 typedef unsigned int         addr_t;
 typedef unsigned int         count_t;
-# define WARN(condition, format...)
 #define false                0
 #define true                 1
 ,14 → 266,6
 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
-#define DRM_NAME    "drm"     /**< Name in kernel, /dev, and /proc */
-#define DRM_INFO(fmt, arg...)  dbgprintf("DRM: "fmt , ##arg)
-#define DRM_ERROR(fmt, arg...) \
-    printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg)
 #define BUILD_BUG_ON_ZERO(e) (sizeof(char[1 - 2 * !!(e)]) - 1)
 ,24 → 336,7
 #define PAGE_MASK       (~(PAGE_SIZE-1))
-#define do_div(n, base)                     \
-({                              \
-    unsigned long __upper, __low, __high, __mod, __base;    \
-    __base = (base);                    \
-    asm("":"=a" (__low), "=d" (__high) : "A" (n));      \
-    __upper = __high;                   \
-    if (__high) {                       \
-        __upper = __high % (__base);            \
-        __high = __high / (__base);         \
-    }                           \
-    asm("divl %2":"=a" (__low), "=d" (__mod)        \
-        : "rm" (__base), "0" (__low), "1" (__upper));   \
-    asm("":"=A" (n) : "a" (__low), "d" (__high));       \
-    __mod;                          \
-})
 #define ENTER()   dbgprintf("enter %s\n",__FUNCTION__)
 #define LEAVE()   dbgprintf("leave %s\n",__FUNCTION__)
 ,4 → 349,9
 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
+#ifndef __read_mostly
+#define __read_mostly
+#endif
 #endif /* _LINUX_TYPES_H */

 /drivers/include/linux/wait.h
 ,6 → 36,40
 } while (0)
+#define wait_event_timeout(wq, condition, timeout)          \
+({                                                          \
+    long __ret = timeout;                                   \
+do{                                                         \
+    wait_queue_t __wait = {                                 \
+        .task_list = LIST_HEAD_INIT(__wait.task_list),      \
+        .evnt      = CreateEvent(NULL, MANUAL_DESTROY),     \
+    };                                                      \
+    u32  flags;                                             \
+                                                            \
+    spin_lock_irqsave(&wq.lock, flags);                     \
+    if (list_empty(&__wait.task_list))                      \
+        __add_wait_queue(&wq, &__wait);                     \
+    spin_unlock_irqrestore(&wq.lock, flags);                \
+                                                            \
+    for(;;){                                                \
+        if (condition)                                      \
+            break;                                          \
+        WaitEvent(__wait.evnt);                             \
+    };                                                      \
+    if (!list_empty_careful(&__wait.task_list)) {           \
+        spin_lock_irqsave(&wq.lock, flags);                 \
+        list_del_init(&__wait.task_list);                   \
+        spin_unlock_irqrestore(&wq.lock, flags);            \
+    };                                                      \
+    DestroyEvent(__wait.evnt);                              \
+} while (0);                                                \
+    __ret;                                                  \
+})
 #define wait_event(wq, condition)                           \
 do{                                                         \
     wait_queue_t __wait = {                                 \
 ,6 → 97,8
 } while (0)
 static inline
 void wake_up_all(wait_queue_head_t *q)
 {
 ,10 → 163,13
     struct work_struct work;
 };
 struct workqueue_struct *alloc_workqueue_key(const char *fmt,
                            unsigned int flags, int max_active);
+#define alloc_ordered_workqueue(fmt, flags, args...)            \
+        alloc_workqueue(fmt, WQ_UNBOUND | (flags), 1, ##args)
 int queue_delayed_work(struct workqueue_struct *wq,
                         struct delayed_work *dwork, unsigned long delay);
 ,5 → 179,12
         (_work)->work.func = _func;             \
     } while (0)
+struct completion {
+    unsigned int done;
+    wait_queue_head_t wait;
+};
 #endif

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