208,40 → 208,41 |
#define INTEL_VLV_D_IDS(info) \ |
INTEL_VGA_DEVICE(0x0155, info) |
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#define _INTEL_BDW_M(gt, id, info) \ |
INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) |
#define _INTEL_BDW_D(gt, id, info) \ |
INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) |
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#define _INTEL_BDW_M_IDS(gt, info) \ |
_INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \ |
_INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \ |
_INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \ |
_INTEL_BDW_M(gt, 0x160E, info) /* ULX */ |
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#define _INTEL_BDW_D_IDS(gt, info) \ |
_INTEL_BDW_D(gt, 0x160A, info), /* Server */ \ |
_INTEL_BDW_D(gt, 0x160D, info) /* Workstation */ |
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#define INTEL_BDW_GT12M_IDS(info) \ |
_INTEL_BDW_M_IDS(1, info), \ |
_INTEL_BDW_M_IDS(2, info) |
INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ |
INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ |
INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ |
INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ |
INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ |
INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ |
INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ |
INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */ |
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#define INTEL_BDW_GT12D_IDS(info) \ |
_INTEL_BDW_D_IDS(1, info), \ |
_INTEL_BDW_D_IDS(2, info) |
INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ |
INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \ |
INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ |
INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ |
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#define INTEL_BDW_GT3M_IDS(info) \ |
_INTEL_BDW_M_IDS(3, info) |
INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ |
INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ |
INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ |
INTEL_VGA_DEVICE(0x162E, info) /* ULX */ |
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#define INTEL_BDW_GT3D_IDS(info) \ |
_INTEL_BDW_D_IDS(3, info) |
INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ |
INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ |
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#define INTEL_BDW_RSVDM_IDS(info) \ |
_INTEL_BDW_M_IDS(4, info) |
INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ |
INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ |
INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ |
INTEL_VGA_DEVICE(0x163E, info) /* ULX */ |
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#define INTEL_BDW_RSVDD_IDS(info) \ |
_INTEL_BDW_D_IDS(4, info) |
INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ |
INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ |
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#define INTEL_BDW_M_IDS(info) \ |
INTEL_BDW_GT12M_IDS(info), \ |
259,21 → 260,35 |
INTEL_VGA_DEVICE(0x22b2, info), \ |
INTEL_VGA_DEVICE(0x22b3, info) |
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#define INTEL_SKL_IDS(info) \ |
#define INTEL_SKL_GT1_IDS(info) \ |
INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ |
INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ |
INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ |
INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ |
INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ |
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#define INTEL_SKL_GT2_IDS(info) \ |
INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ |
INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ |
INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ |
INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ |
INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ |
INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ |
INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ |
INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ |
INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ |
INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ |
INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ |
INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ |
INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \ |
INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \ |
INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ |
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#define INTEL_SKL_GT3_IDS(info) \ |
INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ |
INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ |
INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */ \ |
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#define INTEL_SKL_IDS(info) \ |
INTEL_SKL_GT1_IDS(info), \ |
INTEL_SKL_GT2_IDS(info), \ |
INTEL_SKL_GT3_IDS(info) |
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#define INTEL_BXT_IDS(info) \ |
INTEL_VGA_DEVICE(0x0A84, info), \ |
INTEL_VGA_DEVICE(0x1A84, info), \ |
INTEL_VGA_DEVICE(0x5A84, info) |
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#endif /* _I915_PCIIDS_H */ |