| /drivers/include/asm/atomic.h |
|---|
| 3,7 → 3,6 |
| #include <linux/compiler.h> |
| #include <linux/types.h> |
| #include <asm/processor.h> |
| #include <asm/alternative.h> |
| #include <asm/cmpxchg.h> |
| #include <asm/rmwcc.h> |
| /drivers/include/asm/barrier.h |
|---|
| 53,24 → 53,24 |
| * model and we should fall back to full barriers. |
| */ |
| #define smp_store_release(p, v) \ |
| #define __smp_store_release(p, v) \ |
| do { \ |
| compiletime_assert_atomic_type(*p); \ |
| smp_mb(); \ |
| __smp_mb(); \ |
| WRITE_ONCE(*p, v); \ |
| } while (0) |
| #define smp_load_acquire(p) \ |
| #define __smp_load_acquire(p) \ |
| ({ \ |
| typeof(*p) ___p1 = READ_ONCE(*p); \ |
| compiletime_assert_atomic_type(*p); \ |
| smp_mb(); \ |
| __smp_mb(); \ |
| ___p1; \ |
| }) |
| #else /* regular x86 TSO memory ordering */ |
| #define smp_store_release(p, v) \ |
| #define __smp_store_release(p, v) \ |
| do { \ |
| compiletime_assert_atomic_type(*p); \ |
| barrier(); \ |
| 77,7 → 77,7 |
| WRITE_ONCE(*p, v); \ |
| } while (0) |
| #define smp_load_acquire(p) \ |
| #define __smp_load_acquire(p) \ |
| ({ \ |
| typeof(*p) ___p1 = READ_ONCE(*p); \ |
| compiletime_assert_atomic_type(*p); \ |
| 88,7 → 88,9 |
| #endif |
| /* Atomic operations are already serializing on x86 */ |
| #define smp_mb__before_atomic() barrier() |
| #define smp_mb__after_atomic() barrier() |
| #define __smp_mb__before_atomic() barrier() |
| #define __smp_mb__after_atomic() barrier() |
| #include <asm-generic/barrier.h> |
| #endif /* _ASM_X86_BARRIER_H */ |
| /drivers/include/asm/bug.h |
|---|
| 0,0 → 1,37 |
| #ifndef _ASM_X86_BUG_H |
| #define _ASM_X86_BUG_H |
| #define HAVE_ARCH_BUG |
| #ifdef CONFIG_DEBUG_BUGVERBOSE |
| #ifdef CONFIG_X86_32 |
| # define __BUG_C0 "2:\t.long 1b, %c0\n" |
| #else |
| # define __BUG_C0 "2:\t.long 1b - 2b, %c0 - 2b\n" |
| #endif |
| #define BUG() \ |
| do { \ |
| asm volatile("1:\tud2\n" \ |
| ".pushsection __bug_table,\"a\"\n" \ |
| __BUG_C0 \ |
| "\t.word %c1, 0\n" \ |
| "\t.org 2b+%c2\n" \ |
| ".popsection" \ |
| : : "i" (__FILE__), "i" (__LINE__), \ |
| "i" (sizeof(struct bug_entry))); \ |
| unreachable(); \ |
| } while (0) |
| #else |
| #define BUG() \ |
| do { \ |
| asm volatile("ud2"); \ |
| unreachable(); \ |
| } while (0) |
| #endif |
| #include <asm-generic/bug.h> |
| #endif /* _ASM_X86_BUG_H */ |
| /drivers/include/asm/cpufeature.h |
|---|
| 12,7 → 12,7 |
| #include <asm/disabled-features.h> |
| #endif |
| #define NCAPINTS 14 /* N 32-bit words worth of info */ |
| #define NCAPINTS 16 /* N 32-bit words worth of info */ |
| #define NBUGINTS 1 /* N 32-bit bug flags */ |
| /* |
| 181,22 → 181,17 |
| /* |
| * Auxiliary flags: Linux defined - For features scattered in various |
| * CPUID levels like 0x6, 0xA etc, word 7 |
| * CPUID levels like 0x6, 0xA etc, word 7. |
| * |
| * Reuse free bits when adding new feature flags! |
| */ |
| #define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */ |
| #define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */ |
| #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
| #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
| #define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */ |
| #define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */ |
| #define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */ |
| #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ |
| #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
| #define X86_FEATURE_HWP ( 7*32+ 10) /* "hwp" Intel HWP */ |
| #define X86_FEATURE_HWP_NOTIFY ( 7*32+ 11) /* Intel HWP_NOTIFY */ |
| #define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */ |
| #define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ |
| #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ |
| #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ |
| /* Virtualization flags: Linux defined, word 8 */ |
| 205,16 → 200,7 |
| #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ |
| #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
| #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
| #define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */ |
| #define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */ |
| #define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ |
| #define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ |
| #define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ |
| #define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ |
| #define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */ |
| #define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */ |
| #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ |
| #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ |
| #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ |
| #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ |
| 259,6 → 245,30 |
| /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ |
| #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ |
| /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ |
| #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ |
| #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ |
| #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ |
| #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ |
| #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ |
| #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ |
| #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ |
| #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ |
| #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ |
| #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ |
| /* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ |
| #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ |
| #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ |
| #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ |
| #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ |
| #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ |
| #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ |
| #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ |
| #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ |
| #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ |
| #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ |
| /* |
| * BUG word(s) |
| */ |
| 279,6 → 289,26 |
| #include <asm/asm.h> |
| #include <linux/bitops.h> |
| enum cpuid_leafs |
| { |
| CPUID_1_EDX = 0, |
| CPUID_8000_0001_EDX, |
| CPUID_8086_0001_EDX, |
| CPUID_LNX_1, |
| CPUID_1_ECX, |
| CPUID_C000_0001_EDX, |
| CPUID_8000_0001_ECX, |
| CPUID_LNX_2, |
| CPUID_LNX_3, |
| CPUID_7_0_EBX, |
| CPUID_D_1_EAX, |
| CPUID_F_0_EDX, |
| CPUID_F_1_EDX, |
| CPUID_8000_0008_EBX, |
| CPUID_6_EAX, |
| CPUID_8000_000A_EDX, |
| }; |
| #ifdef CONFIG_X86_FEATURE_NAMES |
| extern const char * const x86_cap_flags[NCAPINTS*32]; |
| extern const char * const x86_power_flags[32]; |
| 356,60 → 386,31 |
| } while (0) |
| #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
| #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) |
| #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
| #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
| #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
| #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
| #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) |
| #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) |
| #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) |
| #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
| #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
| #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) |
| #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) |
| #define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) |
| #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
| #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
| #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) |
| #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
| #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) |
| #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) |
| #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) |
| #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) |
| #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) |
| #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) |
| #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) |
| #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) |
| #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) |
| #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) |
| #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) |
| #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
| #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) |
| #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) |
| #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) |
| #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
| #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
| #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
| #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) |
| #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
| #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
| #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
| #define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) |
| #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
| #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
| #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
| #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) |
| #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) |
| #define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB) |
| #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) |
| #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) |
| #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) |
| #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) |
| #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) |
| #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) |
| /* |
| * Do not add any more of those clumsy macros - use static_cpu_has_safe() for |
| * fast paths and boot_cpu_has() otherwise! |
| */ |
| #if __GNUC__ >= 4 |
| #if __GNUC__ >= 4 && defined(CONFIG_X86_FAST_FEATURE_TESTS) |
| extern void warn_pre_alternatives(void); |
| extern bool __static_cpu_has_safe(u16 bit); |
| /drivers/include/asm/fixmap.h |
|---|
| 19,7 → 19,6 |
| #include <asm/acpi.h> |
| #include <asm/apicdef.h> |
| #include <asm/page.h> |
| #include <asm/pvclock.h> |
| #ifdef CONFIG_X86_32 |
| #include <linux/threads.h> |
| #include <asm/kmap_types.h> |
| 72,11 → 71,7 |
| #ifdef CONFIG_X86_VSYSCALL_EMULATION |
| VSYSCALL_PAGE = (FIXADDR_TOP - VSYSCALL_ADDR) >> PAGE_SHIFT, |
| #endif |
| #ifdef CONFIG_PARAVIRT_CLOCK |
| PVCLOCK_FIXMAP_BEGIN, |
| PVCLOCK_FIXMAP_END = PVCLOCK_FIXMAP_BEGIN+PVCLOCK_VSYSCALL_NR_PAGES-1, |
| #endif |
| #endif |
| FIX_DBGP_BASE, |
| FIX_EARLYCON_MEM_BASE, |
| #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT |
| /drivers/include/asm/io.h |
|---|
| 0,0 → 1,328 |
| #ifndef _ASM_X86_IO_H |
| #define _ASM_X86_IO_H |
| /* |
| * This file contains the definitions for the x86 IO instructions |
| * inb/inw/inl/outb/outw/outl and the "string versions" of the same |
| * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" |
| * versions of the single-IO instructions (inb_p/inw_p/..). |
| * |
| * This file is not meant to be obfuscating: it's just complicated |
| * to (a) handle it all in a way that makes gcc able to optimize it |
| * as well as possible and (b) trying to avoid writing the same thing |
| * over and over again with slight variations and possibly making a |
| * mistake somewhere. |
| */ |
| /* |
| * Thanks to James van Artsdalen for a better timing-fix than |
| * the two short jumps: using outb's to a nonexistent port seems |
| * to guarantee better timings even on fast machines. |
| * |
| * On the other hand, I'd like to be sure of a non-existent port: |
| * I feel a bit unsafe about using 0x80 (should be safe, though) |
| * |
| * Linus |
| */ |
| /* |
| * Bit simplified and optimized by Jan Hubicka |
| * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. |
| * |
| * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, |
| * isa_read[wl] and isa_write[wl] fixed |
| * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> |
| */ |
| #define ARCH_HAS_IOREMAP_WC |
| #define ARCH_HAS_IOREMAP_WT |
| #include <linux/string.h> |
| #include <linux/compiler.h> |
| #define build_mmio_read(name, size, type, reg, barrier) \ |
| static inline type name(const volatile void __iomem *addr) \ |
| { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ |
| :"m" (*(volatile type __force *)addr) barrier); return ret; } |
| #define build_mmio_write(name, size, type, reg, barrier) \ |
| static inline void name(type val, volatile void __iomem *addr) \ |
| { asm volatile("mov" size " %0,%1": :reg (val), \ |
| "m" (*(volatile type __force *)addr) barrier); } |
| build_mmio_read(readb, "b", unsigned char, "=q", :"memory") |
| build_mmio_read(readw, "w", unsigned short, "=r", :"memory") |
| build_mmio_read(readl, "l", unsigned int, "=r", :"memory") |
| build_mmio_read(__readb, "b", unsigned char, "=q", ) |
| build_mmio_read(__readw, "w", unsigned short, "=r", ) |
| build_mmio_read(__readl, "l", unsigned int, "=r", ) |
| build_mmio_write(writeb, "b", unsigned char, "q", :"memory") |
| build_mmio_write(writew, "w", unsigned short, "r", :"memory") |
| build_mmio_write(writel, "l", unsigned int, "r", :"memory") |
| build_mmio_write(__writeb, "b", unsigned char, "q", ) |
| build_mmio_write(__writew, "w", unsigned short, "r", ) |
| build_mmio_write(__writel, "l", unsigned int, "r", ) |
| #define readb_relaxed(a) __readb(a) |
| #define readw_relaxed(a) __readw(a) |
| #define readl_relaxed(a) __readl(a) |
| #define __raw_readb __readb |
| #define __raw_readw __readw |
| #define __raw_readl __readl |
| #define writeb_relaxed(v, a) __writeb(v, a) |
| #define writew_relaxed(v, a) __writew(v, a) |
| #define writel_relaxed(v, a) __writel(v, a) |
| #define __raw_writeb __writeb |
| #define __raw_writew __writew |
| #define __raw_writel __writel |
| #define mmiowb() barrier() |
| #ifdef CONFIG_X86_64 |
| build_mmio_read(readq, "q", unsigned long, "=r", :"memory") |
| build_mmio_write(writeq, "q", unsigned long, "r", :"memory") |
| #define readq_relaxed(a) readq(a) |
| #define writeq_relaxed(v, a) writeq(v, a) |
| #define __raw_readq(a) readq(a) |
| #define __raw_writeq(val, addr) writeq(val, addr) |
| /* Let people know that we have them */ |
| #define readq readq |
| #define writeq writeq |
| #endif |
| /** |
| * virt_to_phys - map virtual addresses to physical |
| * @address: address to remap |
| * |
| * The returned physical address is the physical (CPU) mapping for |
| * the memory address given. It is only valid to use this function on |
| * addresses directly mapped or allocated via kmalloc. |
| * |
| * This function does not give bus mappings for DMA transfers. In |
| * almost all conceivable cases a device driver should not be using |
| * this function |
| */ |
| /** |
| * phys_to_virt - map physical address to virtual |
| * @address: address to remap |
| * |
| * The returned virtual address is a current CPU mapping for |
| * the memory address given. It is only valid to use this function on |
| * addresses that have a kernel mapping |
| * |
| * This function does not handle bus mappings for DMA transfers. In |
| * almost all conceivable cases a device driver should not be using |
| * this function |
| */ |
| #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) |
| #define isa_bus_to_virt phys_to_virt |
| /* |
| * However PCI ones are not necessarily 1:1 and therefore these interfaces |
| * are forbidden in portable PCI drivers. |
| * |
| * Allow them on x86 for legacy drivers, though. |
| */ |
| #define virt_to_bus virt_to_phys |
| #define bus_to_virt phys_to_virt |
| /** |
| * ioremap - map bus memory into CPU space |
| * @offset: bus address of the memory |
| * @size: size of the resource to map |
| * |
| * ioremap performs a platform specific sequence of operations to |
| * make bus memory CPU accessible via the readb/readw/readl/writeb/ |
| * writew/writel functions and the other mmio helpers. The returned |
| * address is not guaranteed to be usable directly as a virtual |
| * address. |
| * |
| * If the area you are trying to map is a PCI BAR you should have a |
| * look at pci_iomap(). |
| */ |
| //extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); |
| extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); |
| #define ioremap_uc ioremap_uc |
| extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); |
| extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, |
| unsigned long prot_val); |
| /* |
| * The default ioremap() behavior is non-cached: |
| */ |
| //static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) |
| //{ |
| // return ioremap_nocache(offset, size); |
| //} |
| //extern void iounmap(volatile void __iomem *addr); |
| extern void set_iounmap_nonlazy(void); |
| #ifdef __KERNEL__ |
| #include <asm-generic/iomap.h> |
| /* |
| * Convert a virtual cached pointer to an uncached pointer |
| */ |
| #define xlate_dev_kmem_ptr(p) p |
| static inline void |
| memset_io(volatile void __iomem *addr, unsigned char val, size_t count) |
| { |
| memset((void __force *)addr, val, count); |
| } |
| static inline void |
| memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count) |
| { |
| memcpy(dst, (const void __force *)src, count); |
| } |
| static inline void |
| memcpy_toio(volatile void __iomem *dst, const void *src, size_t count) |
| { |
| memcpy((void __force *)dst, src, count); |
| } |
| /* |
| * ISA space is 'always mapped' on a typical x86 system, no need to |
| * explicitly ioremap() it. The fact that the ISA IO space is mapped |
| * to PAGE_OFFSET is pure coincidence - it does not mean ISA values |
| * are physical addresses. The following constant pointer can be |
| * used as the IO-area pointer (it can be iounmapped as well, so the |
| * analogy with PCI is quite large): |
| */ |
| #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) |
| /* |
| * Cache management |
| * |
| * This needed for two cases |
| * 1. Out of order aware processors |
| * 2. Accidentally out of order processors (PPro errata #51) |
| */ |
| static inline void flush_write_buffers(void) |
| { |
| #if defined(CONFIG_X86_PPRO_FENCE) |
| asm volatile("lock; addl $0,0(%%esp)": : :"memory"); |
| #endif |
| } |
| #endif /* __KERNEL__ */ |
| extern void native_io_delay(void); |
| extern int io_delay_type; |
| extern void io_delay_init(void); |
| #if defined(CONFIG_PARAVIRT) |
| #include <asm/paravirt.h> |
| #else |
| static inline void slow_down_io(void) |
| { |
| native_io_delay(); |
| #ifdef REALLY_SLOW_IO |
| native_io_delay(); |
| native_io_delay(); |
| native_io_delay(); |
| #endif |
| } |
| #endif |
| #define BUILDIO(bwl, bw, type) \ |
| static inline void out##bwl(unsigned type value, int port) \ |
| { \ |
| asm volatile("out" #bwl " %" #bw "0, %w1" \ |
| : : "a"(value), "Nd"(port)); \ |
| } \ |
| \ |
| static inline unsigned type in##bwl(int port) \ |
| { \ |
| unsigned type value; \ |
| asm volatile("in" #bwl " %w1, %" #bw "0" \ |
| : "=a"(value) : "Nd"(port)); \ |
| return value; \ |
| } \ |
| \ |
| static inline void out##bwl##_p(unsigned type value, int port) \ |
| { \ |
| out##bwl(value, port); \ |
| slow_down_io(); \ |
| } \ |
| \ |
| static inline unsigned type in##bwl##_p(int port) \ |
| { \ |
| unsigned type value = in##bwl(port); \ |
| slow_down_io(); \ |
| return value; \ |
| } \ |
| \ |
| static inline void outs##bwl(int port, const void *addr, unsigned long count) \ |
| { \ |
| asm volatile("rep; outs" #bwl \ |
| : "+S"(addr), "+c"(count) : "d"(port)); \ |
| } \ |
| \ |
| static inline void ins##bwl(int port, void *addr, unsigned long count) \ |
| { \ |
| asm volatile("rep; ins" #bwl \ |
| : "+D"(addr), "+c"(count) : "d"(port)); \ |
| } |
| BUILDIO(b, b, char) |
| BUILDIO(w, w, short) |
| BUILDIO(l, , int) |
| extern void *xlate_dev_mem_ptr(phys_addr_t phys); |
| extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); |
| extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, |
| enum page_cache_mode pcm); |
| //extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); |
| extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); |
| extern bool is_early_ioremap_ptep(pte_t *ptep); |
| #ifdef CONFIG_XEN |
| #include <xen/xen.h> |
| struct bio_vec; |
| extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, |
| const struct bio_vec *vec2); |
| #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ |
| (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ |
| (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) |
| #endif /* CONFIG_XEN */ |
| #define IO_SPACE_LIMIT 0xffff |
| #ifdef CONFIG_MTRR |
| extern int __must_check arch_phys_wc_index(int handle); |
| #define arch_phys_wc_index arch_phys_wc_index |
| extern int __must_check arch_phys_wc_add(unsigned long base, |
| unsigned long size); |
| extern void arch_phys_wc_del(int handle); |
| #define arch_phys_wc_add arch_phys_wc_add |
| #endif |
| #endif /* _ASM_X86_IO_H */ |
| /drivers/include/asm/msr-index.h |
|---|
| 321,6 → 321,7 |
| #define MSR_F15H_PERF_CTR 0xc0010201 |
| #define MSR_F15H_NB_PERF_CTL 0xc0010240 |
| #define MSR_F15H_NB_PERF_CTR 0xc0010241 |
| #define MSR_F15H_IC_CFG 0xc0011021 |
| /* Fam 10h MSRs */ |
| #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
| /drivers/include/asm/msr.h |
|---|
| 32,6 → 32,16 |
| int err; |
| }; |
| struct saved_msr { |
| bool valid; |
| struct msr_info info; |
| }; |
| struct saved_msrs { |
| unsigned int num; |
| struct saved_msr *array; |
| }; |
| static inline unsigned long long native_read_tscp(unsigned int *aux) |
| { |
| unsigned long low, high; |
| 161,7 → 171,7 |
| static inline void wrmsrl(unsigned msr, u64 val) |
| { |
| native_write_msr(msr, (u32)val, (u32)(val >> 32)); |
| native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32)); |
| } |
| /* wrmsr with exception handling */ |
| /drivers/include/asm/pgtable.h |
|---|
| 69,9 → 69,6 |
| #define pmd_clear(pmd) native_pmd_clear(pmd) |
| #define pte_update(mm, addr, ptep) do { } while (0) |
| #define pte_update_defer(mm, addr, ptep) do { } while (0) |
| #define pmd_update(mm, addr, ptep) do { } while (0) |
| #define pmd_update_defer(mm, addr, ptep) do { } while (0) |
| #define pgd_val(x) native_pgd_val(x) |
| #define __pgd(x) native_make_pgd(x) |
| 165,14 → 162,9 |
| } |
| #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
| static inline int pmd_trans_splitting(pmd_t pmd) |
| { |
| return pmd_val(pmd) & _PAGE_SPLITTING; |
| } |
| static inline int pmd_trans_huge(pmd_t pmd) |
| { |
| return pmd_val(pmd) & _PAGE_PSE; |
| return (pmd_val(pmd) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; |
| } |
| static inline int has_transparent_hugepage(void) |
| 179,6 → 171,13 |
| { |
| return cpu_has_pse; |
| } |
| #ifdef __HAVE_ARCH_PTE_DEVMAP |
| static inline int pmd_devmap(pmd_t pmd) |
| { |
| return !!(pmd_val(pmd) & _PAGE_DEVMAP); |
| } |
| #endif |
| #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
| static inline pte_t pte_set_flags(pte_t pte, pteval_t set) |
| 255,6 → 254,11 |
| return pte_set_flags(pte, _PAGE_SPECIAL); |
| } |
| static inline pte_t pte_mkdevmap(pte_t pte) |
| { |
| return pte_set_flags(pte, _PAGE_SPECIAL|_PAGE_DEVMAP); |
| } |
| static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set) |
| { |
| pmdval_t v = native_pmd_val(pmd); |
| 274,6 → 278,11 |
| return pmd_clear_flags(pmd, _PAGE_ACCESSED); |
| } |
| static inline pmd_t pmd_mkclean(pmd_t pmd) |
| { |
| return pmd_clear_flags(pmd, _PAGE_DIRTY); |
| } |
| static inline pmd_t pmd_wrprotect(pmd_t pmd) |
| { |
| return pmd_clear_flags(pmd, _PAGE_RW); |
| 284,6 → 293,11 |
| return pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); |
| } |
| static inline pmd_t pmd_mkdevmap(pmd_t pmd) |
| { |
| return pmd_set_flags(pmd, _PAGE_DEVMAP); |
| } |
| static inline pmd_t pmd_mkhuge(pmd_t pmd) |
| { |
| return pmd_set_flags(pmd, _PAGE_PSE); |
| 465,6 → 479,13 |
| return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); |
| } |
| #ifdef __HAVE_ARCH_PTE_DEVMAP |
| static inline int pte_devmap(pte_t a) |
| { |
| return (pte_flags(a) & _PAGE_DEVMAP) == _PAGE_DEVMAP; |
| } |
| #endif |
| #define pte_accessible pte_accessible |
| static inline bool pte_accessible(struct mm_struct *mm, pte_t a) |
| { |
| 731,14 → 752,9 |
| * updates should either be sets, clears, or set_pte_atomic for P->P |
| * transitions, which means this hook should only be called for user PTEs. |
| * This hook implies a P->P protection or access change has taken place, which |
| * requires a subsequent TLB flush. The notification can optionally be delayed |
| * until the TLB flush event by using the pte_update_defer form of the |
| * interface, but care must be taken to assure that the flush happens while |
| * still holding the same page table lock so that the shadow and primary pages |
| * do not become out of sync on SMP. |
| * requires a subsequent TLB flush. |
| */ |
| #define pte_update(mm, addr, ptep) do { } while (0) |
| #define pte_update_defer(mm, addr, ptep) do { } while (0) |
| #endif |
| /* |
| 816,10 → 832,6 |
| unsigned long address, pmd_t *pmdp); |
| #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH |
| extern void pmdp_splitting_flush(struct vm_area_struct *vma, |
| unsigned long addr, pmd_t *pmdp); |
| #define __HAVE_ARCH_PMD_WRITE |
| static inline int pmd_write(pmd_t pmd) |
| { |
| 830,9 → 842,7 |
| static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr, |
| pmd_t *pmdp) |
| { |
| pmd_t pmd = native_pmdp_get_and_clear(pmdp); |
| pmd_update(mm, addr, pmdp); |
| return pmd; |
| return native_pmdp_get_and_clear(pmdp); |
| } |
| #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
| 840,7 → 850,6 |
| unsigned long addr, pmd_t *pmdp) |
| { |
| clear_bit(_PAGE_BIT_RW, (unsigned long *)pmdp); |
| pmd_update(mm, addr, pmdp); |
| } |
| /* |
| /drivers/include/asm/pgtable_types.h |
|---|
| 22,9 → 22,10 |
| #define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */ |
| #define _PAGE_BIT_SPECIAL _PAGE_BIT_SOFTW1 |
| #define _PAGE_BIT_CPA_TEST _PAGE_BIT_SOFTW1 |
| #define _PAGE_BIT_SPLITTING _PAGE_BIT_SOFTW2 /* only valid on a PSE pmd */ |
| #define _PAGE_BIT_HIDDEN _PAGE_BIT_SOFTW3 /* hidden by kmemcheck */ |
| #define _PAGE_BIT_SOFT_DIRTY _PAGE_BIT_SOFTW3 /* software dirty tracking */ |
| #define _PAGE_BIT_SOFTW4 58 /* available for programmer */ |
| #define _PAGE_BIT_DEVMAP _PAGE_BIT_SOFTW4 |
| #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */ |
| /* If _PAGE_BIT_PRESENT is clear, we use these: */ |
| 46,7 → 47,6 |
| #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE) |
| #define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL) |
| #define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST) |
| #define _PAGE_SPLITTING (_AT(pteval_t, 1) << _PAGE_BIT_SPLITTING) |
| #define __HAVE_ARCH_PTE_SPECIAL |
| #ifdef CONFIG_KMEMCHECK |
| 85,8 → 85,11 |
| #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) |
| #define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX) |
| #define _PAGE_DEVMAP (_AT(u64, 1) << _PAGE_BIT_DEVMAP) |
| #define __HAVE_ARCH_PTE_DEVMAP |
| #else |
| #define _PAGE_NX (_AT(pteval_t, 0)) |
| #define _PAGE_DEVMAP (_AT(pteval_t, 0)) |
| #endif |
| #define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE) |
| /drivers/include/asm/x86_init.h |
|---|
| 82,13 → 82,11 |
| * struct x86_init_timers - platform specific timer setup |
| * @setup_perpcu_clockev: set up the per cpu clock event device for the |
| * boot cpu |
| * @tsc_pre_init: platform function called before TSC init |
| * @timer_init: initialize the platform timer (default PIT/HPET) |
| * @wallclock_init: init the wallclock device |
| */ |
| struct x86_init_timers { |
| void (*setup_percpu_clockev)(void); |
| void (*tsc_pre_init)(void); |
| void (*timer_init)(void); |
| void (*wallclock_init)(void); |
| }; |