| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/Makefile.am |
|---|
| 0,0 → 1,82 |
| MFC_CORE = \ |
| end_thread.asm \ |
| mfc_batchbuffer_head.asm \ |
| mfc_batchbuffer_tail.asm |
| MFC_CORE_AVC = \ |
| mfc_batchbuffer_avc_intra.asm \ |
| mfc_batchbuffer_avc_inter.asm |
| MFC_CORE_HSW = \ |
| mfc_batchbuffer_hsw.asm |
| INTEL_G6B = mfc_batchbuffer_avc_intra.g6b mfc_batchbuffer_avc_inter.g6b |
| INTEL_G6A = mfc_batchbuffer_avc_intra.g6a mfc_batchbuffer_avc_inter.g6a |
| INTEL_GEN6_INC = mfc_batchbuffer.inc |
| INTEL_GEN6_ASM = $(INTEL_G6A:%.g6a=%.gen6.asm) |
| INTEL_G7B = mfc_batchbuffer_avc_intra.g7b mfc_batchbuffer_avc_inter.g7b |
| INTEL_G7A = mfc_batchbuffer_avc_intra.g7a mfc_batchbuffer_avc_inter.g7a |
| INTEL_GEN7_INC = mfc_batchbuffer.inc |
| INTEL_GEN7_ASM = $(INTEL_G7A:%.g7a=%.gen7.asm) |
| INTEL_G75B = mfc_batchbuffer_hsw.g75b |
| INTEL_G75A = mfc_batchbuffer_hsw.g75a |
| INTEL_GEN75_INC = mfc_batchbuffer_hsw.inc |
| INTEL_GEN75_ASM = $(INTEL_G75A:%.g75a=%.gen75.asm) |
| TARGETS = |
| if HAVE_GEN4ASM |
| TARGETS += $(INTEL_G6B) |
| TARGETS += $(INTEL_G7B) |
| TARGETS += $(INTEL_G75B) |
| endif |
| all-local: $(TARGETS) |
| SUFFIXES = .g6a .g6b .g7a .g7b .gen6.asm .gen7.asm .g75a .g75b .gen75.asm |
| if HAVE_GEN4ASM |
| $(INTEL_GEN6_ASM): $(MFC_CORE) $(MFC_CORE_AVC) $(INTEL_GEN6_INC) |
| .g6a.gen6.asm: |
| $(AM_V_GEN)cpp -P -DDEV_SNB $< > _mfc0.$@ && \ |
| m4 _mfc0.$@ > $@ && \ |
| rm _mfc0.$@ |
| .gen6.asm.g6b: |
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| $(INTEL_GEN7_ASM): $(MFC_CORE) $(MFC_CORE_AVC) $(INTEL_GEN7_INC) |
| .g7a.gen7.asm: |
| $(AM_V_GEN)cpp -P -DDEV_IVB $< > _mfc0.$@ && \ |
| m4 _mfc0.$@ > $@ && \ |
| rm _mfc0.$@ |
| .gen7.asm.g7b: |
| $(AM_V_GEN)$(GEN4ASM) -g 7 -o $@ $< |
| $(INTEL_GEN75_ASM): $(MFC_CORE_HSW) $(INTEL_GEN75_INC) |
| .g75a.gen75.asm: |
| $(AM_V_GEN)cpp -P $< > _mfc0.$@ && \ |
| m4 _mfc0.$@ > $@ && \ |
| rm _mfc0.$@ |
| .gen75.asm.g75b: |
| $(AM_V_GEN)$(GEN4ASM) -g 7.5 -o $@ $< |
| endif |
| CLEANFILES = $(INTEL_GEN6_ASM) $(INTEL_GEN7_ASM) $(INTEL_GEN75_ASM) |
| EXTRA_DIST = \ |
| $(INTEL_G6A) \ |
| $(INTEL_G6B) \ |
| $(INTEL_G7A) \ |
| $(INTEL_G7B) \ |
| $(INTEL_G75A) \ |
| $(INTEL_G75B) \ |
| $(INTEL_GEN6_INC) \ |
| $(INTEL_GEN7_INC) \ |
| $(INTEL_GEN75_INC) \ |
| $(MFC_CORE) \ |
| $(MFC_CORE_AVC) \ |
| $(MFC_CORE_HSW) \ |
| $(NULL) |
| # Extra clean files so that maintainer-clean removes *everything* |
| MAINTAINERCLEANFILES = Makefile.in |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/Makefile.in |
|---|
| 0,0 → 1,523 |
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| maintainer-clean: maintainer-clean-am |
| -rm -f Makefile |
| maintainer-clean-am: distclean-am maintainer-clean-generic |
| mostlyclean: mostlyclean-am |
| mostlyclean-am: mostlyclean-generic mostlyclean-libtool |
| pdf: pdf-am |
| pdf-am: |
| ps: ps-am |
| ps-am: |
| uninstall-am: |
| .MAKE: install-am install-strip |
| .PHONY: all all-am all-local check check-am clean clean-generic \ |
| clean-libtool cscopelist-am ctags-am distclean \ |
| distclean-generic distclean-libtool distdir dvi dvi-am html \ |
| html-am info info-am install install-am install-data \ |
| install-data-am install-dvi install-dvi-am install-exec \ |
| install-exec-am install-html install-html-am install-info \ |
| install-info-am install-man install-pdf install-pdf-am \ |
| install-ps install-ps-am install-strip installcheck \ |
| installcheck-am installdirs maintainer-clean \ |
| maintainer-clean-generic mostlyclean mostlyclean-generic \ |
| mostlyclean-libtool pdf pdf-am ps ps-am tags-am uninstall \ |
| uninstall-am |
| all-local: $(TARGETS) |
| @HAVE_GEN4ASM_TRUE@$(INTEL_GEN6_ASM): $(MFC_CORE) $(MFC_CORE_AVC) $(INTEL_GEN6_INC) |
| @HAVE_GEN4ASM_TRUE@.g6a.gen6.asm: |
| @HAVE_GEN4ASM_TRUE@ $(AM_V_GEN)cpp -P -DDEV_SNB $< > _mfc0.$@ && \ |
| @HAVE_GEN4ASM_TRUE@ m4 _mfc0.$@ > $@ && \ |
| @HAVE_GEN4ASM_TRUE@ rm _mfc0.$@ |
| @HAVE_GEN4ASM_TRUE@.gen6.asm.g6b: |
| @HAVE_GEN4ASM_TRUE@ $(AM_V_GEN)$(GEN4ASM) -g 6 -o $@ $< |
| @HAVE_GEN4ASM_TRUE@$(INTEL_GEN7_ASM): $(MFC_CORE) $(MFC_CORE_AVC) $(INTEL_GEN7_INC) |
| @HAVE_GEN4ASM_TRUE@.g7a.gen7.asm: |
| @HAVE_GEN4ASM_TRUE@ $(AM_V_GEN)cpp -P -DDEV_IVB $< > _mfc0.$@ && \ |
| @HAVE_GEN4ASM_TRUE@ m4 _mfc0.$@ > $@ && \ |
| @HAVE_GEN4ASM_TRUE@ rm _mfc0.$@ |
| @HAVE_GEN4ASM_TRUE@.gen7.asm.g7b: |
| @HAVE_GEN4ASM_TRUE@ $(AM_V_GEN)$(GEN4ASM) -g 7 -o $@ $< |
| @HAVE_GEN4ASM_TRUE@$(INTEL_GEN75_ASM): $(MFC_CORE_HSW) $(INTEL_GEN75_INC) |
| @HAVE_GEN4ASM_TRUE@.g75a.gen75.asm: |
| @HAVE_GEN4ASM_TRUE@ $(AM_V_GEN)cpp -P $< > _mfc0.$@ && \ |
| @HAVE_GEN4ASM_TRUE@ m4 _mfc0.$@ > $@ && \ |
| @HAVE_GEN4ASM_TRUE@ rm _mfc0.$@ |
| @HAVE_GEN4ASM_TRUE@.gen75.asm.g75b: |
| @HAVE_GEN4ASM_TRUE@ $(AM_V_GEN)$(GEN4ASM) -g 7.5 -o $@ $< |
| # Tell versions [3.59,3.63) of GNU make to not export all variables. |
| # Otherwise a system limit (for SysV at least) may be exceeded. |
| .NOEXPORT: |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/end_thread.asm |
|---|
| 0,0 → 1,29 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| __EXIT: |
| mov (8) msg_reg0<1>:ud r0<8,8,1>:ud {align1} ; |
| send (16) msg_ind acc0<1>ud null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT} ; |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer.inc |
|---|
| 0,0 → 1,246 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| define(`BIND_IDX_VME_OUTPUT', `0') |
| define(`BIND_IDX_MFC_SLICE_HEADER', `1') |
| define(`BIND_IDX_MFC_BATCHBUFFER', `2') |
| define(`INTRAMBFLAG_MASK', `0x00002000') |
| #ifdef DEV_SNB |
| define(`OB_CACHE_TYPE', `5') |
| #else |
| define(`OB_CACHE_TYPE', `10') |
| #endif |
| define(`OB_READ', `0') |
| define(`OB_WRITE', `8') |
| define(`OB_CONTROL_0', `0') /* 1 OWord, low 128 bits */ |
| define(`OB_CONTROL_1', `1') /* 1 OWord, high 128 bits */ |
| define(`OB_CONTROL_2', `2') /* 2 OWords */ |
| define(`OB_CONTROL_3', `3') /* 4 OWords */ |
| define(`OB_CONTROL_4', `4') /* 8 OWords */ |
| #ifdef DEV_SNB |
| define(`OB_WRITE_COMMIT_CATEGORY', `1') /* write commit on Sandybrige */ |
| #else |
| define(`OB_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ |
| #endif |
| define(`OB_HEADER_PRESENT', `1') |
| define(`INTER_VME_OUTPUT_IN_BYTES', `160') |
| define(`INTER_VME_OUTPUT_IN_OWS', `10') |
| define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') |
| define(`MFC_AVC_PAK_OBJECT_INTRA_DW0', `0x71490009:UD') |
| define(`MFC_AVC_PAK_OBJECT_INTRA_DW3', `0x000e0000:UD') /* CbpDC (1 << 19 | 1 << 18 | 1 << 17) */ |
| define(`MFC_AVC_PAK_OBJECT_INTRA_DW4', `0xFFFF0000:UD') /* CBP for Y */ |
| define(`MFC_AVC_PAK_OBJECT_INTRA_DW5', `0x000F000F:UD') |
| define(`MFC_AVC_PAK_OBJECT_INTRA_DW6', `0x04000000:UD') /* the flag of the last macroblock */ |
| define(`MFC_AVC_PAK_OBJECT_INTER_DW0', `MFC_AVC_PAK_OBJECT_INTRA_DW0') |
| define(`MFC_AVC_PAK_OBJECT_INTER_DW1', `0x20:UD') /* 32 MVs */ |
| define(`MFC_AVC_PAK_OBJECT_INTER_DW2', `INTER_VME_OUTPUT_IN_BYTES:UD') /* offset, in bytes */ |
| define(`MFC_AVC_PAK_OBJECT_INTER_DW3', `0x014e0000:UD') /* |
| * (1 << 24) | PackedMvNum, Debug |
| * (4 << 20) | 8 MV, SNB don't use it |
| * (1 << 19) | CbpDcY |
| * (1 << 18) | CbpDcU |
| * (1 << 17) | CbpDcV |
| * (0 << 15) | Transform8x8Flag = 0 |
| * (0 << 14) | Frame based |
| * (0 << 13) | Inter MB |
| * (1 << 8) | MbType = P_L0_16x16 |
| * (0 << 7) | MBZ for frame |
| * (0 << 6) | MBZ |
| * (2 << 4) | MBZ for inter |
| * (0 << 3) | MBZ |
| * (0 << 2) | SkipMbFlag |
| * (0 << 0) InterMbMode |
| */ |
| define(`MFC_AVC_PAK_OBJECT_INTER_DW4', `MFC_AVC_PAK_OBJECT_INTRA_DW4') |
| define(`MFC_AVC_PAK_OBJECT_INTER_DW5', `MFC_AVC_PAK_OBJECT_INTRA_DW5') |
| define(`MFC_AVC_PAK_OBJECT_INTER_DW6', `MFC_AVC_PAK_OBJECT_INTRA_DW6') |
| define(`MI_BATCH_BUFFER_END', `0x05000000:UD') |
| /* GRF registers |
| * r0 header |
| * r1~r4 constant buffer (reserved) |
| * r5 inline data |
| * r6~r7 reserved |
| * r8~r15 temporary registers |
| * r16 write back of Oword Block Write |
| */ |
| /* |
| * GRF 0 -- header |
| */ |
| define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ |
| /* |
| * GRF 1~4 -- Constant Buffer (reserved) |
| */ |
| define(`FLAG_MASK_LAST_SLICE', `0x0001:uw') |
| define(`FLAG_MASK_LAST_OBJECT', `0x0002:uw') |
| define(`FLAG_MASK_FIRST_OBJECT', `0x0004:uw') |
| /* |
| * GRF 5 -- inline data |
| */ |
| define(`inline_reg0', `r5') |
| define(`head_offset', `inline_reg0.0') /* :ud, in units of Owords */ |
| define(`batchbuffer_offset', `inline_reg0.4') /* :ud, in units of Owords */ |
| define(`tail_size', `inline_reg0.8') /* :w, in units of Owords */ |
| define(`head_size', `inline_reg0.10') /* :w, in units of Owords */ |
| define(`flags', `inline_reg0.12') /* :uw, |
| * bit0 the flag of the last slice |
| * bit1 the flag of the last object in a slice |
| * bit2 the flag of the first object in a slice |
| */ |
| define(`total_mbs', `inline_reg0.14') /* :w, the number of macroblock commands |
| * being processed by the kernel |
| */ |
| define(`mb_x', `inline_reg0.16') /* :ub, */ |
| define(`mb_y', `inline_reg0.17') /* :ub, */ |
| define(`mb_xy', `inline_reg0.16') /* :uw, */ |
| define(`width_in_mb', `inline_reg0.20') /* :uw, the picture width in macroblocks */ |
| define(`qp', `inline_reg0.22') /* :ub, */ |
| define(`ref_idx0', `inline_reg0.24') /* :ud */ |
| define(`ref_idx1', `inline_reg0.28') /* :ud */ |
| /* |
| * GRF 8~15 -- temporary registers |
| */ |
| define(`tmp_reg0', `r8') |
| define(`tmp_reg1', `r9') |
| define(`tmp_reg2', `r10') |
| define(`tmp_reg3', `r11') |
| define(`tmp_reg4', `r12') |
| define(`tmp_reg5', `r13') |
| define(`tmp_reg6', `r14') |
| define(`tmp_reg7', `r15') |
| define(`tmp_vme_output', `tmp_reg0') |
| define(`tmp_slice_header', `tmp_reg1') |
| define(`tmp_mfc_batchbuffer', `tmp_reg2') |
| define(`tmp_offset', `tmp_reg7') |
| /* |
| * GRF 16~23 write back for Oword Block Read message |
| */ |
| define(`ob_read_wb', `r16<1>:uw') |
| define(`ob_read_wb0', `r16') |
| define(`ob_read_wb1', `r17') |
| define(`ob_read_wb2', `r18') |
| define(`ob_read_wb3', `r19') |
| define(`ob_read_wb4', `r20') |
| define(`ob_read_wb5', `r21') |
| define(`ob_read_wb6', `r22') |
| define(`ob_read_wb7', `r23') |
| define(`ob_read_wb_len_slice_header', `1') |
| define(`ob_read_wb_len_vme_intra', `1') |
| define(`ob_read_wb_len_vme_inter', `1') |
| #ifdef DEV_SNB |
| /* |
| * GRF 24~25 write back for Oword Block Write message |
| */ |
| define(`ob_write_wb', `r24') |
| define(`ob_write_wb_length', `1') |
| #else |
| /* |
| * GRF 24~25 -- reserved |
| */ |
| define(`ob_write_wb', `null<1>:W') |
| define(`ob_write_wb_length', `0') |
| #endif |
| /* |
| * GRF 26~27 |
| */ |
| define(`pak_object_ud', `r26.0') |
| define(`pak_object0_ud', `r26.0') |
| define(`pak_object1_ud', `r26.4') |
| define(`pak_object2_ud', `r26.8') |
| define(`pak_object3_ud', `r26.12') |
| define(`pak_object4_ud', `r26.16') |
| define(`pak_object5_ud', `r26.20') |
| define(`pak_object6_ud', `r26.24') |
| define(`pak_object7_ud', `r26.28') |
| define(`pak_object8_ud', `r27.0') |
| define(`pak_object9_ud', `r27.4') |
| define(`pak_object10_ud', `r27.8') |
| define(`pak_object11_ud', `r27.12') |
| #ifdef DEV_SNB |
| /* |
| * Message Payload registers |
| */ |
| define(`msg_ind', `0') |
| define(`msg_reg0', `m0') |
| define(`msg_reg1', `m1') |
| define(`msg_reg2', `m2') |
| define(`msg_reg3', `m3') |
| define(`msg_reg4', `m4') |
| define(`msg_reg5', `m5') |
| define(`msg_reg6', `m6') |
| define(`msg_reg7', `m7') |
| define(`msg_reg8', `m8') |
| #else |
| /* |
| * Message Payload registers |
| */ |
| define(`msg_ind', `64') |
| define(`msg_reg0', `g64') |
| define(`msg_reg1', `g65') |
| define(`msg_reg2', `g66') |
| define(`msg_reg3', `g67') |
| define(`msg_reg4', `g68') |
| define(`msg_reg5', `g69') |
| define(`msg_reg6', `g70') |
| define(`msg_reg7', `g71') |
| define(`msg_reg8', `g72') |
| #endif |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_inter.asm |
|---|
| 0,0 → 1,178 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| __PAK_OBJECT: |
| mul (1) tmp_offset.0<1>:ud width_in_mb<0,1,0>:uw mb_y<0,1,0>:ub {align1}; |
| add (1) tmp_offset.0<1>:ud tmp_offset.0<0,1,0>:ud mb_x<0,1,0>:ub {align1}; |
| /* |
| * The layout of VME output |
| * ++++++++++++++++++++++++++++++++++++++++++++++ |
| * | MV(128bytes) | other info (32bytes) | |
| * ++++++++++++++++++++++++++++++++++++++++++++++ |
| */ |
| mul (1) tmp_vme_output.8<1>:ud tmp_offset.0<0,1,0>:ud INTER_VME_OUTPUT_IN_OWS:ud {align1} ; /* point to output buffer */ |
| add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud INTER_VME_OUTPUT_MV_IN_OWS:uw {align1}; /* point to other info */ |
| __PAK_OBJECT_LOOP: |
| /* |
| * Read other info |
| */ |
| mov (8) msg_reg0.0<1>:ud tmp_vme_output<8,8,1>:ud {align1} ; |
| send (16) |
| msg_ind |
| ob_read_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_READ, |
| OB_CONTROL_2, |
| BIND_IDX_VME_OUTPUT, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 1 |
| rlen ob_read_wb_len_vme_inter |
| {align1}; |
| /* |
| * Fill the command |
| */ |
| mov (16) pak_object_ud<1>:ud 0x0:ud {align1} ; |
| and.z.f0.1 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_OBJECT {align1}; |
| and.z.f0.0 (1) null<1>:ud ob_read_wb0.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; |
| (-f0.0)jmpi (1) __FILL_INTRA_PAK_COMMAND ; |
| __FILL_INTER_PAK_COMMAND: |
| /* DW0 */ |
| mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_INTER_DW0 ; |
| /* DW2 */ |
| mul (1) pak_object2_ud<1>:ud tmp_offset.0<0,1,0>:ud INTER_VME_OUTPUT_IN_BYTES:ud {align1} ; |
| /* DW5 */ |
| mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW5 ; |
| /* DW1 must be 32 for 8 MVs and 128 for 32 MVs !!! */ |
| mov (1) pak_object1_ud<1>:ud ob_read_wb0.8<0,1,0>:ud {align1} ; |
| /* DW3 */ |
| mov (1) pak_object3_ud<1>:ud ob_read_wb0.0<0,1,0>:ud {align1} ; |
| /* DW4 */ |
| add (1) pak_object4_ud<1>:ud mb_xy<0,1,0>:uw MFC_AVC_PAK_OBJECT_INTER_DW4 {align1} ; |
| add (1) mb_x<1>:ub mb_x<0,1,0>:ub 1:uw {align1}; |
| cmp.e.f0.0 (1) null<1>:uw width_in_mb<0,1,0>:uw mb_x<0,1,0>:ub {align1}; |
| (f0.0)mov (1) mb_x<1>:ub 0:uw {align1} ; |
| (f0.0)add (1) mb_y<1>:ub mb_y<0,1,0>:ub 1:uw {align1} ; |
| /* DW6 */ |
| mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; |
| (-f0.1)mov (1) pak_object6_ud<1>:ud MFC_AVC_PAK_OBJECT_INTER_DW6 {align1} ; |
| cmp.e.f0.0 (1) null<1>:uw total_mbs<0,1,0>:uw 1:uw {align1}; |
| (-f0.0)mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; |
| add (1) pak_object6_ud<1>:ud pak_object6_ud<0,1,0>:ud qp<0,1,0>:ub {align1} ; |
| /* DW7 */ |
| mov (1) pak_object7_ud<1>:ud ob_read_wb0.4<0,1,0>:ud {align1} ; |
| /* DW8 */ |
| mov (1) pak_object8_ud<1>:ud ref_idx0<0,1,0>:ud {align1} ; |
| /* DW9 */ |
| mov (1) pak_object9_ud<1>:ud ref_idx1<0,1,0>:ud {align1} ; |
| jmpi (1) __OUTPUT_PAK_COMMAND ; |
| __FILL_INTRA_PAK_COMMAND: |
| /* DW0 */ |
| mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW0 ; |
| /* DW5 */ |
| mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW5 ; |
| /* DW4 */ |
| add (1) pak_object4_ud<1>:ud mb_xy<0,1,0>:uw MFC_AVC_PAK_OBJECT_INTRA_DW4 {align1} ; |
| add (1) mb_x<1>:ub mb_x<0,1,0>:ub 1:uw {align1}; |
| cmp.e.f0.0 (1) null<1>:uw width_in_mb<0,1,0>:uw mb_x<0,1,0>:ub {align1}; |
| (f0.0)mov (1) mb_x<1>:ub 0:uw {align1} ; |
| (f0.0)add (1) mb_y<1>:ub mb_y<0,1,0>:ub 1:uw {align1} ; |
| /* DW6 */ |
| mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; |
| (-f0.1)mov (1) pak_object6_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW6 {align1} ; |
| cmp.e.f0.0 (1) null<1>:uw total_mbs<0,1,0>:uw 1:uw {align1}; |
| (-f0.0)mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; |
| add (1) pak_object6_ud<1>:ud pak_object6_ud<0,1,0>:ud qp<0,1,0>:ub {align1} ; |
| /* DW3 */ |
| and (1) pak_object3_ud<1>:ud ob_read_wb0.0<0,1,0>:ud 0xFFFF {align1} ; |
| add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_PAK_OBJECT_INTRA_DW3 {align1} ; |
| /* DW7 */ |
| mov (1) pak_object7_ud<1>:ud ob_read_wb0.4<0,1,0>:ud {align1} ; |
| /* DW8 */ |
| mov (1) pak_object8_ud<1>:ud ob_read_wb0.8<0,1,0>:ud {align1} ; |
| /* DW9 */ |
| and (1) pak_object9_ud<1>:ud ob_read_wb0.12<0,1,0>:ud 0xFC:ud {align1} ; |
| __OUTPUT_PAK_COMMAND: |
| mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; |
| mov (8) msg_reg1.0<1>:ud pak_object_ud<8,8,1>:ud {align1} ; |
| mov (8) msg_reg2.0<1>:ud pak_object8_ud<8,8,1>:ud {align1} ; |
| /* point to the next other info block */ |
| add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud INTER_VME_OUTPUT_IN_OWS:ud {align1} ; |
| send (16) |
| msg_ind |
| ob_write_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_WRITE, |
| OB_CONTROL_3, |
| BIND_IDX_MFC_BATCHBUFFER, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 3 |
| rlen ob_write_wb_length |
| {align1}; |
| /* the new offset */ |
| add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 4:ud {align1} ; |
| add (1) tmp_offset.0<1>:ud tmp_offset.0<0,1,0>:ud 1:ud {align1}; |
| add.z.f0.0 (1) total_mbs<1>:w total_mbs<0,1,0>:w -1:w {align1}; |
| (-f0.0)jmpi (1) __PAK_OBJECT_LOOP ; |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_inter.g6a |
|---|
| 0,0 → 1,32 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| #include "mfc_batchbuffer.inc" |
| #include "mfc_batchbuffer_head.asm" |
| #include "mfc_batchbuffer_avc_inter.asm" |
| #include "mfc_batchbuffer_tail.asm" |
| #include "end_thread.asm" |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_inter.g6b |
|---|
| 0,0 → 1,90 |
| { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, |
| { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x21340231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 }, |
| { 0x00000001, 0x21540231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 }, |
| { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, |
| { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 }, |
| { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 }, |
| { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, |
| { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, |
| { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, |
| { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, |
| { 0x00000041, 0x21e04521, 0x000000b4, 0x000000b1 }, |
| { 0x00000040, 0x21e04421, 0x000001e0, 0x000000b0 }, |
| { 0x00000041, 0x21080c21, 0x000001e0, 0x0000000a }, |
| { 0x00000040, 0x21082c21, 0x00000108, 0x00080008 }, |
| { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 }, |
| { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0200 }, |
| { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, |
| { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 }, |
| { 0x01000005, 0x20000c20, 0x00000200, 0x00002000 }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0x00000026 }, |
| { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, |
| { 0x00000041, 0x23480c21, 0x000001e0, 0x000000a0 }, |
| { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, |
| { 0x00000001, 0x23440021, 0x00000208, 0x00000000 }, |
| { 0x00000001, 0x234c0021, 0x00000200, 0x00000000 }, |
| { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, |
| { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, |
| { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, |
| { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, |
| { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, |
| { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, |
| { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, |
| { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, |
| { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, |
| { 0x00000001, 0x23600021, 0x000000b8, 0x00000000 }, |
| { 0x00000001, 0x23640021, 0x000000bc, 0x00000000 }, |
| { 0x00000020, 0x34001c00, 0x00001400, 0x00000022 }, |
| { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, |
| { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, |
| { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, |
| { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, |
| { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, |
| { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, |
| { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, |
| { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, |
| { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, |
| { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, |
| { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff }, |
| { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, |
| { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, |
| { 0x00000001, 0x23600021, 0x00000208, 0x00000000 }, |
| { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc }, |
| { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x20200022, 0x008d0340, 0x00000000 }, |
| { 0x00600001, 0x20400022, 0x008d0360, 0x00000000 }, |
| { 0x00000040, 0x21080c21, 0x00000108, 0x0000000a }, |
| { 0x05800031, 0x23001cdd, 0x00000000, 0x061b0302 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000004 }, |
| { 0x00000040, 0x21e00c21, 0x000001e0, 0x00000001 }, |
| { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffff9a }, |
| { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e }, |
| { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 }, |
| { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 }, |
| { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, |
| { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, |
| { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, |
| { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, |
| { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, |
| { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, |
| { 0x00400001, 0x20200062, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x20240062, 0x00000000, 0x05000000 }, |
| { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, |
| { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, |
| { 0x07800031, 0x24001cc0, 0x00000000, 0x82000010 }, |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_inter.g7a |
|---|
| 0,0 → 1,32 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| #include "mfc_batchbuffer.inc" |
| #include "mfc_batchbuffer_head.asm" |
| #include "mfc_batchbuffer_avc_inter.asm" |
| #include "mfc_batchbuffer_tail.asm" |
| #include "end_thread.asm" |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_inter.g7b |
|---|
| 0,0 → 1,90 |
| { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, |
| { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x21340231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 }, |
| { 0x00000001, 0x21540231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 }, |
| { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, |
| { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 }, |
| { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 }, |
| { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, |
| { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, |
| { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, |
| { 0x00000041, 0x21e04521, 0x000000b4, 0x000000b1 }, |
| { 0x00000040, 0x21e04421, 0x000001e0, 0x000000b0 }, |
| { 0x00000041, 0x21080c21, 0x000001e0, 0x0000000a }, |
| { 0x00000040, 0x21082c21, 0x00000108, 0x00080008 }, |
| { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, |
| { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180200 }, |
| { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, |
| { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 }, |
| { 0x01000005, 0x20000c20, 0x00000200, 0x00002000 }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0x00000026 }, |
| { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, |
| { 0x00000041, 0x23480c21, 0x000001e0, 0x000000a0 }, |
| { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, |
| { 0x00000001, 0x23440021, 0x00000208, 0x00000000 }, |
| { 0x00000001, 0x234c0021, 0x00000200, 0x00000000 }, |
| { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, |
| { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, |
| { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, |
| { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, |
| { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, |
| { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, |
| { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, |
| { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, |
| { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, |
| { 0x00000001, 0x23600021, 0x000000b8, 0x00000000 }, |
| { 0x00000001, 0x23640021, 0x000000bc, 0x00000000 }, |
| { 0x00000020, 0x34001c00, 0x00001400, 0x00000022 }, |
| { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, |
| { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, |
| { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, |
| { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, |
| { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, |
| { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, |
| { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, |
| { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, |
| { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, |
| { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, |
| { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff }, |
| { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, |
| { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, |
| { 0x00000001, 0x23600021, 0x00000208, 0x00000000 }, |
| { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc }, |
| { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x28200021, 0x008d0340, 0x00000000 }, |
| { 0x00600001, 0x28400021, 0x008d0360, 0x00000000 }, |
| { 0x00000040, 0x21080c21, 0x00000108, 0x0000000a }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x060a0302 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000004 }, |
| { 0x00000040, 0x21e00c21, 0x000001e0, 0x00000001 }, |
| { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffff9a }, |
| { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e }, |
| { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 }, |
| { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 }, |
| { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, |
| { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, |
| { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, |
| { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, |
| { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, |
| { 0x00400001, 0x28200061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x28240061, 0x00000000, 0x05000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, |
| { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 }, |
| { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 }, |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_intra.asm |
|---|
| 0,0 → 1,111 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| __PAK_OBJECT: |
| mul (1) tmp_vme_output.8<1>:ud width_in_mb<0,1,0>:uw mb_y<0,1,0>:ub {align1}; |
| add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud mb_x<0,1,0>:ub {align1}; |
| mov (16) pak_object_ud<1>:ud 0x0:ud {align1} ; |
| mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW0 ; |
| mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW5 ; |
| and.z.f0.1 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_OBJECT {align1}; |
| __PAK_OBJECT_LOOP: |
| mov (8) msg_reg0.0<1>:ud tmp_vme_output<8,8,1>:ud {align1} ; |
| send (16) |
| msg_ind |
| ob_read_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_READ, |
| OB_CONTROL_0, |
| BIND_IDX_VME_OUTPUT, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 1 |
| rlen ob_read_wb_len_vme_intra |
| {align1}; |
| /* DW4 */ |
| add (1) pak_object4_ud<1>:ud mb_xy<0,1,0>:uw MFC_AVC_PAK_OBJECT_INTRA_DW4 {align1} ; |
| add (1) mb_x<1>:ub mb_x<0,1,0>:ub 1:uw {align1}; |
| cmp.e.f0.0 (1) null<1>:uw width_in_mb<0,1,0>:uw mb_x<0,1,0>:ub {align1}; |
| (f0.0)mov (1) mb_x<1>:ub 0:uw {align1} ; |
| (f0.0)add (1) mb_y<1>:ub mb_y<0,1,0>:ub 1:uw {align1} ; |
| /* DW6 */ |
| mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; |
| (-f0.1)mov (1) pak_object6_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW6 {align1} ; |
| cmp.e.f0.0 (1) null<1>:uw total_mbs<0,1,0>:uw 1:uw {align1}; |
| (-f0.0)mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; |
| add (1) pak_object6_ud<1>:ud pak_object6_ud<0,1,0>:ud qp<0,1,0>:ub {align1} ; |
| /* DW3 */ |
| and (1) pak_object3_ud<1>:ud ob_read_wb0.0<0,1,0>:ud 0xFFFF {align1} ; |
| add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_PAK_OBJECT_INTRA_DW3 {align1} ; |
| /* DW7 */ |
| mov (1) pak_object7_ud<1>:ud ob_read_wb0.4<0,1,0>:ud {align1} ; |
| /* DW8 */ |
| mov (1) pak_object8_ud<1>:ud ob_read_wb0.8<0,1,0>:ud {align1} ; |
| /* DW9 */ |
| and (1) pak_object9_ud<1>:ud ob_read_wb0.12<0,1,0>:ud 0xFC:ud {align1} ; |
| mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; |
| mov (8) msg_reg1.0<1>:ud pak_object_ud<8,8,1>:ud {align1} ; |
| mov (8) msg_reg2.0<1>:ud pak_object8_ud<8,8,1>:ud {align1} ; |
| /* the new offset */ |
| add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud 1:ud {align1} ; |
| send (16) |
| msg_ind |
| ob_write_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_WRITE, |
| OB_CONTROL_3, |
| BIND_IDX_MFC_BATCHBUFFER, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 3 |
| rlen ob_write_wb_length |
| {align1}; |
| /* the new offset */ |
| add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 4:ud {align1} ; |
| add.z.f0.0 (1) total_mbs<1>:w total_mbs<0,1,0>:w -1:w {align1}; |
| (-f0.0)jmpi (1) __PAK_OBJECT_LOOP ; |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_intra.g6a |
|---|
| 0,0 → 1,32 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| #include "mfc_batchbuffer.inc" |
| #include "mfc_batchbuffer_head.asm" |
| #include "mfc_batchbuffer_avc_intra.asm" |
| #include "mfc_batchbuffer_tail.asm" |
| #include "end_thread.asm" |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_intra.g6b |
|---|
| 0,0 → 1,66 |
| { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, |
| { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x21340231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 }, |
| { 0x00000001, 0x21540231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 }, |
| { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, |
| { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 }, |
| { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 }, |
| { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, |
| { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, |
| { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, |
| { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, |
| { 0x00000041, 0x21084521, 0x000000b4, 0x000000b1 }, |
| { 0x00000040, 0x21084421, 0x00000108, 0x000000b0 }, |
| { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, |
| { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, |
| { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 }, |
| { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 }, |
| { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0000 }, |
| { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, |
| { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, |
| { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, |
| { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, |
| { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, |
| { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, |
| { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, |
| { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, |
| { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff }, |
| { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, |
| { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, |
| { 0x00000001, 0x23600021, 0x00000208, 0x00000000 }, |
| { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc }, |
| { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x20200022, 0x008d0340, 0x00000000 }, |
| { 0x00600001, 0x20400022, 0x008d0360, 0x00000000 }, |
| { 0x00000040, 0x21080c21, 0x00000108, 0x00000001 }, |
| { 0x05800031, 0x23001cdd, 0x00000000, 0x061b0302 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000004 }, |
| { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffce }, |
| { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e }, |
| { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 }, |
| { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 }, |
| { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, |
| { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, |
| { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, |
| { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, |
| { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, |
| { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, |
| { 0x00400001, 0x20200062, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x20240062, 0x00000000, 0x05000000 }, |
| { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, |
| { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, |
| { 0x07800031, 0x24001cc0, 0x00000000, 0x82000010 }, |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_intra.g7a |
|---|
| 0,0 → 1,32 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| #include "mfc_batchbuffer.inc" |
| #include "mfc_batchbuffer_head.asm" |
| #include "mfc_batchbuffer_avc_intra.asm" |
| #include "mfc_batchbuffer_tail.asm" |
| #include "end_thread.asm" |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_avc_intra.g7b |
|---|
| 0,0 → 1,66 |
| { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, |
| { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x21340231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 }, |
| { 0x00000001, 0x21540231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 }, |
| { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, |
| { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 }, |
| { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 }, |
| { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, |
| { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, |
| { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, |
| { 0x00000041, 0x21084521, 0x000000b4, 0x000000b1 }, |
| { 0x00000040, 0x21084421, 0x00000108, 0x000000b0 }, |
| { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, |
| { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, |
| { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 }, |
| { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, |
| { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180000 }, |
| { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, |
| { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, |
| { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, |
| { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, |
| { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, |
| { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, |
| { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, |
| { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, |
| { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, |
| { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff }, |
| { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, |
| { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, |
| { 0x00000001, 0x23600021, 0x00000208, 0x00000000 }, |
| { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc }, |
| { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x28200021, 0x008d0340, 0x00000000 }, |
| { 0x00600001, 0x28400021, 0x008d0360, 0x00000000 }, |
| { 0x00000040, 0x21080c21, 0x00000108, 0x00000001 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x060a0302 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000004 }, |
| { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffce }, |
| { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e }, |
| { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 }, |
| { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 }, |
| { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, |
| { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, |
| { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, |
| { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, |
| { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, |
| { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, |
| { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, |
| { 0x00400001, 0x28200061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x28240061, 0x00000000, 0x05000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, |
| { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 }, |
| { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 }, |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_head.asm |
|---|
| 0,0 → 1,87 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| /* |
| * __START |
| */ |
| __START: |
| mov (16) tmp_reg0<1>:ud 0x0:ud {align1} ; |
| mov (16) tmp_reg2<1>:ud 0x0:ud {align1} ; |
| mov (1) tmp_slice_header.20<1>:ub thread_id_ub {align1}; /* dispatch id */ |
| mov (1) tmp_slice_header.8<1>:ud head_offset<0,1,0>:ud {align1}; |
| mov (1) tmp_mfc_batchbuffer.20<1>:ub thread_id_ub {align1}; /* dispatch id */ |
| mov (1) tmp_mfc_batchbuffer.8<1>:ud batchbuffer_offset<0,1,0>:ud {align1}; |
| __HEAD: |
| and.z.f0.0 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_FIRST_OBJECT {align1}; |
| (f0.0)jmpi (1) __PAK_OBJECT ; |
| __HEAD_LOOP: |
| mov (8) msg_reg0.0<1>:ud tmp_slice_header<8,8,1>:ud {align1} ; |
| send (16) |
| msg_ind |
| ob_read_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_READ, |
| OB_CONTROL_0, |
| BIND_IDX_MFC_SLICE_HEADER, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 1 |
| rlen ob_read_wb_len_slice_header |
| {align1}; |
| mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; |
| mov (8) msg_reg1.0<1>:ud ob_read_wb0<8,8,1>:ud {align1} ; |
| send (16) |
| msg_ind |
| ob_write_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_WRITE, |
| OB_CONTROL_0, |
| BIND_IDX_MFC_BATCHBUFFER, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 2 |
| rlen ob_write_wb_length |
| {align1}; |
| /* the new offset */ |
| add (1) tmp_slice_header.8<1>:ud tmp_slice_header.8<0,1,0>:ud 1:ud {align1} ; |
| add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 1:ud {align1} ; |
| add.z.f0.0 (1) head_size<1>:w head_size<0,1,0>:w -1:w {align1}; |
| (-f0.0)jmpi (1) __HEAD_LOOP ; |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_hsw.asm |
|---|
| 0,0 → 1,296 |
| /* |
| * Copyright © 2010-2013 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Zhao Yakui <yakui.zhao@intel.com> |
| */ |
| START: |
| mov (16) pak_object_reg0.0<1>:ud 0x0:ud {align1}; |
| mov (8) obw_m0.0<1>:ud 0x0:ud {align1}; |
| mov (8) mb_cur_msg.0<1>:ud 0x0:ud {align1}; |
| mov (16) mb_temp.0<1>:ud 0x0:ud {align1}; |
| mov (1) cur_mb_x<1>:uw mb_x<0,1,0>:ub {align1}; |
| mov (1) cur_mb_y<1>:uw mb_y<0,1,0>:ub {align1}; |
| mov (1) end_mb_x<1>:uw slice_end_x<0,1,0>:ub {align1}; |
| mov (1) end_mb_y<1>:uw slice_end_y<0,1,0>:ub {align1}; |
| mov (1) end_loop_count<1>:uw total_mbs<0,1,0>:uw {align1}; |
| mov (1) vme_len<1>:ud 2:ud {align1}; |
| and.z.f0.0 (1) null:uw mb_flag<0,1,0>:ub INTRA_SLICE:uw {align1}; |
| (f0.0) mov (1) vme_len<1>:ud 24:ud {align1}; |
| mov (1) obw_m0.8<1>:UD buffer_offset<0,1,0>:ud {align1}; |
| mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ |
| mul (1) mb_cur_msg.8<1>:UD width_in_mbs<0,1,0>:UW cur_mb_y<0,1,0>:UW {align1}; |
| add (1) mb_cur_msg.8<1>:UD mb_cur_msg.8<0,1,0>:UD cur_mb_x<0,1,0>:uw {align1}; |
| mul (1) mb_cur_msg.8<1>:UD mb_cur_msg.8<0,1,0>:UD vme_len<0,1,0>:UD {align1}; |
| mov (1) mb_cur_msg.20<1>:UB thread_id_ub {align1}; /* dispatch id */ |
| mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_DW0:ud {align1}; |
| mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_DW5:ud {align1}; |
| mov (1) pak_object10_ud<1>:ud MFC_AVC_PAK_OBJECT_DW10:ud {align1}; |
| mov (1) pak_object6_ud<1>:ub qp_flag<0,1,0>:ub {align1}; |
| pak_object_loop: |
| mov (8) mb_msg0.0<1>:ud mb_cur_msg.0<8,8,1>:ud {align1}; |
| mov (1) pak_object4_ud<1>:ud MFC_AVC_PAK_OBJECT_DW4:ud {align1}; |
| mov (1) tmp_reg0.0<1>:ub cur_mb_x<0,1,0>:ub {align1}; |
| mov (1) tmp_reg0.1<1>:ub cur_mb_y<0,1,0>:ub {align1}; |
| mov (1) pak_object4_ud<1>:uw tmp_reg0.0<0,1,0>:uw {align1}; |
| /* pak_object6_ud */ |
| mov (1) pak_object_reg0.26<1>:uw 0x0:uw {align1}; |
| cmp.e.f0.0 (1) null:uw cur_mb_x<0,1,0>:uw end_mb_x<0,1,0>:uw {align1}; |
| (-f0.0) jmpi (1) start_mb_flag; |
| cmp.e.f0.0 (1) null:uw cur_mb_y<0,1,0>:uw end_mb_y<0,1,0>:uw {align1}; |
| (f0.0) mov (1) pak_object_reg0.26<1>:uw MFC_AVC_PAK_LAST_MB:uw {align1}; |
| start_mb_flag: |
| and.z.f0.0 (1) null:uw mb_flag<0,1,0>:ub INTRA_SLICE:uw {align1}; |
| (f0.0) jmpi (1) inter_frame_start; |
| /* bind index 0, read 2 oword (32bytes), msg type: 0(OWord Block Read) */ |
| send (16) |
| mb_ind |
| mb_wb.0<1>:ud |
| null |
| data_port( |
| OBR_CACHE_TYPE, |
| OBR_MESSAGE_TYPE, |
| OBR_CONTROL_2, |
| MV_BIND_IDX, |
| OBR_WRITE_COMMIT_CATEGORY, |
| OBR_HEADER_PRESENT |
| ) |
| mlen 1 |
| rlen 1 |
| {align1}; |
| jmpi (1) intra_pak_command; |
| nop; |
| nop; |
| inter_frame_start: |
| /* bind index 0, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ |
| send (16) |
| mb_ind |
| mb_wb.0<1>:ud |
| null |
| data_port( |
| OBR_CACHE_TYPE, |
| OBR_MESSAGE_TYPE, |
| OBR_CONTROL_4, |
| MV_BIND_IDX, |
| OBR_WRITE_COMMIT_CATEGORY, |
| OBR_HEADER_PRESENT |
| ) |
| mlen 1 |
| rlen 2 |
| {align1}; |
| /* TODO: RefID is required after multi-references are added */ |
| cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; |
| (f0.0) jmpi (1) intra_pak_command; |
| /* MV len and MV mode */ |
| and (1) pak_object3_ud<1>:ud mb_inter_wb.0<0,1,0>:ud MFC_AVC_INTER_MASK_DW3:ud {align1}; |
| add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_PAK_CBP:ud {align1}; |
| and (1) tmp_reg0.0<1>:uw mb_inter_wb.0<0,1,0>:uw INTER_MASK:uw {align1}; |
| mov (1) pak_object1_ud<1>:ud 32:ud {align1}; |
| cmp.e.f0.0 (1) null:uw tmp_reg0.0<0,1,0>:uw INTER_8X8MODE:uw {align1}; |
| (-f0.0) add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud INTER_MV8:ud {align1}; |
| (-f0.0) jmpi (1) inter_mv_check; |
| and.nz.f0.0 (1) null:ud mb_inter_wb.4<0,1,0>:uw SUBSHAPE_MASK:uw {align1}; |
| (f0.0) mov (1) pak_object1_ud<1>:ud 128:ud {align1}; |
| (f0.0) add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud INTER_MV32:ud {align1}; |
| (f0.0) jmpi (1) mv_check_end; |
| add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud INTER_MV8:ud {align1}; |
| inter_mv_check: |
| and (1) tmp_reg0.0<1>:uw mb_inter_wb.0<0,1,0>:uw INTER_MASK:uw {align1}; |
| cmp.e.f0.0 (1) null:uw tmp_reg0.0<0,1,0>:uw INTER_16X16MODE:uw {align1}; |
| (f0.0) jmpi (1) mv_check_end; |
| add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; |
| /* Read MV for MB A */ |
| /* bind index 0, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ |
| send (16) |
| mb_ind |
| mb_mv0.0<1>:ud |
| null |
| data_port( |
| OBR_CACHE_TYPE, |
| OBR_MESSAGE_TYPE, |
| OBR_CONTROL_8, |
| MV_BIND_IDX, |
| OBR_WRITE_COMMIT_CATEGORY, |
| OBR_HEADER_PRESENT |
| ) |
| mlen 1 |
| rlen 4 |
| {align1}; |
| /* TODO: RefID is required after multi-references are added */ |
| mov (2) mb_mv0.8<1>:ud mb_mv1.0<2,2,1>:ud {align1}; |
| mov (2) mb_mv0.16<1>:ud mb_mv2.0<2,2,1>:ud {align1}; |
| mov (2) mb_mv0.24<1>:ud mb_mv3.0<2,2,1>:ud {align1}; |
| mov (8) msg_reg0.0<1>:ud mb_msg0.0<8,8,1>:ud {align1} ; |
| mov (8) msg_reg1.0<1>:ud mb_mv0.0<8,8,1>:ud {align1} ; |
| /* Write MV for MB A */ |
| /* bind index 0, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ |
| send (16) |
| msg_ind |
| obw_wb |
| null |
| data_port( |
| OBW_CACHE_TYPE, |
| OBW_MESSAGE_TYPE, |
| OBW_CONTROL_2, |
| MV_BIND_IDX, |
| OBW_WRITE_COMMIT_CATEGORY, |
| OBW_HEADER_PRESENT |
| ) |
| mlen 2 |
| rlen obw_wb_length |
| {align1}; |
| mv_check_end: |
| /* ref list */ |
| mov (1) pak_object8_ud<1>:ud fwd_ref<0,1,0>:ud {align1}; |
| mov (1) pak_object9_ud<1>:ud bwd_ref<0,1,0>:ud {align1}; |
| /* inter_mode. pak_object7_ud */ |
| mov (1) pak_object7_ud<1>:ud 0x0:ud {align1}; |
| mov (1) pak_object_reg0.28<1>:ub mb_inter_wb.5<0,1,0>:ub {align1}; |
| mov (1) pak_object_reg0.29<1>:ub mb_inter_wb.6<0,1,0>:ub {align1}; |
| /* mv start address */ |
| add (1) tmp_reg0.4<1>:ud mb_cur_msg.8<0,1,0>:ud 3:ud {align1}; |
| mul (1) pak_object2_ud<1>:ud tmp_reg0.4<0,1,0>:ud 16:ud {align1}; |
| jmpi (1) write_pak_command; |
| intra_pak_command: |
| /* object 1/2 is set to zero */ |
| mov (2) pak_object1_ud<1>:ud 0x0:ud {align1}; |
| /* object 7/8 intra mode */ |
| mov (1) pak_object7_ud<1>:ud mb_intra_wb.4<0,1,0>:ud {align1}; |
| mov (1) pak_object8_ud<1>:ud mb_intra_wb.8<0,1,0>:ud {align1}; |
| /* object 9 Intra structure */ |
| mov (1) pak_object9_ud<1>:ud 0x0:ud {align1}; |
| mov (1) pak_object9_ud<1>:ub mb_intra_wb.12<0,1,0>:ub {align1}; |
| and (1) pak_object3_ud<1>:ud mb_intra_wb.0<0,1,0>:ud MFC_AVC_INTRA_MASK_DW3:ud {align1}; |
| add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_INTRA_FLAG + MFC_AVC_PAK_CBP:ud {align1}; |
| mov (1) tmp_reg0.0<1>:ud 0:ud {align1}; |
| mov (1) tmp_reg0.1<1>:ub mb_intra_wb.2<0,1,0>:ub {align1}; |
| and (1) tmp_reg0.0<1>:uw tmp_reg0.0<0,1,0>:uw AVC_INTRA_MASK:uw {align1}; |
| add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud tmp_reg0.0<0,1,0>:ud {align1}; |
| /* Write the pak command into the batchbuffer */ |
| write_pak_command: |
| mov (8) msg_reg0.0<1>:ud obw_m0.0<8,8,1>:ud {align1} ; |
| mov (8) msg_reg1.0<1>:ud pak_object_reg0.0<8,8,1>:ud {align1} ; |
| /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ |
| send (16) |
| msg_ind |
| obw_wb |
| null |
| data_port( |
| OBW_CACHE_TYPE, |
| OBW_MESSAGE_TYPE, |
| OBW_CONTROL_2, |
| MFC_BIND_IDX, |
| OBW_WRITE_COMMIT_CATEGORY, |
| OBW_HEADER_PRESENT |
| ) |
| mlen 2 |
| rlen obw_wb_length |
| {align1}; |
| add (1) msg_reg0.8<1>:ud msg_reg0.8<0,1,0>:ud 2:ud {align1}; |
| mov (8) msg_reg1.0<1>:ud pak_object_reg1.0<8,8,1>:ud {align1}; |
| /* bind index 3, write 1 oword (16bytes), msg type: 8(OWord Block Write) */ |
| send (16) |
| msg_ind |
| obw_wb |
| null |
| data_port( |
| OBW_CACHE_TYPE, |
| OBW_MESSAGE_TYPE, |
| OBW_CONTROL_0, |
| MFC_BIND_IDX, |
| OBW_WRITE_COMMIT_CATEGORY, |
| OBW_HEADER_PRESENT |
| ) |
| mlen 2 |
| rlen obw_wb_length |
| {align1}; |
| /* Check the next mb */ |
| add (1) cur_loop_count<1>:uw cur_loop_count<0,1,0>:uw 1:uw {align1}; |
| cmp.e.f0.0 (1) null:uw cur_loop_count<0,1,0>:uw end_loop_count<0,1,0>:uw {align1}; |
| (f0.0) jmpi (1) pak_loop_end; |
| /* the buffer offset for next block */ |
| add (1) obw_m0.8<1>:ud obw_m0.8<0,1,0>:ud 3:uw {align1}; |
| add (1) mb_cur_msg.8<1>:ud mb_cur_msg.8<0,1,0>:ud vme_len<0,1,0>:ud {align1}; |
| add (1) cur_mb_x<1>:uw cur_mb_x<0,1,0>:uw 1:uw {align1}; |
| /* Check whether it is already equal to width in mbs */ |
| cmp.e.f0.0 (1) null:uw cur_mb_x<0,1,0>:uw width_in_mbs<0,1,0>:uw {align1}; |
| (f0.0) add (1) cur_mb_y<1>:uw cur_mb_y<0,1,0>:uw 1:uw {align1}; |
| (f0.0) mov (1) cur_mb_x<1>:uw 0:uw {align1}; |
| /* continue the pak command for next mb */ |
| jmpi (1) pak_object_loop; |
| nop; |
| nop; |
| pak_loop_end: |
| /* Issue message fence so that the previous write message is committed */ |
| send (16) |
| msg_ind |
| mb_wb.0<1>:ud |
| null |
| data_port( |
| OBR_CACHE_TYPE, |
| OBR_MESSAGE_FENCE, |
| OBR_MF_COMMIT, |
| MFC_BIND_IDX, |
| OBR_WRITE_COMMIT_CATEGORY, |
| OBR_HEADER_PRESENT |
| ) |
| mlen 1 |
| rlen 1 |
| {align1}; |
| __EXIT: |
| /* |
| * kill thread |
| */ |
| mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; |
| send (1) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |
| nop; |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_hsw.g75a |
|---|
| 0,0 → 1,29 |
| /* |
| * Copyright © 2010-2013 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Zhao Yakui <yakui.zhao@intel.com> |
| */ |
| #include "mfc_batchbuffer_hsw.inc" |
| #include "mfc_batchbuffer_hsw.asm" |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_hsw.g75b |
|---|
| 0,0 → 1,105 |
| { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, |
| { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, |
| { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 }, |
| { 0x00800001, 0x2ac00061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x2ac00229, 0x000000a8, 0x00000000 }, |
| { 0x00000001, 0x2ac20229, 0x000000a9, 0x00000000 }, |
| { 0x00000001, 0x2ae00229, 0x000000b0, 0x00000000 }, |
| { 0x00000001, 0x2ae20229, 0x000000b1, 0x00000000 }, |
| { 0x00000001, 0x2ae40129, 0x000000ac, 0x00000000 }, |
| { 0x00000001, 0x2ae80061, 0x00000000, 0x00000002 }, |
| { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, |
| { 0x00010001, 0x2ae80061, 0x00000000, 0x00000018 }, |
| { 0x00000001, 0x21e80021, 0x000000a0, 0x00000000 }, |
| { 0x00000001, 0x21f40231, 0x00000014, 0x00000000 }, |
| { 0x00000041, 0x2b082521, 0x000000aa, 0x00000ac2 }, |
| { 0x00000040, 0x2b082421, 0x00000b08, 0x00000ac0 }, |
| { 0x00000041, 0x2b080421, 0x00000b08, 0x00000ae8 }, |
| { 0x00000001, 0x2b140231, 0x00000014, 0x00000000 }, |
| { 0x00000001, 0x23400061, 0x00000000, 0x7149000a }, |
| { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, |
| { 0x00000001, 0x23680061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x23580231, 0x000000a6, 0x00000000 }, |
| { 0x00600001, 0x2b400021, 0x008d0b00, 0x00000000 }, |
| { 0x00000001, 0x23500061, 0x00000000, 0xffff0000 }, |
| { 0x00000001, 0x21000231, 0x00000ac0, 0x00000000 }, |
| { 0x00000001, 0x21010231, 0x00000ac2, 0x00000000 }, |
| { 0x00000001, 0x23500129, 0x00000100, 0x00000000 }, |
| { 0x00000001, 0x235a0169, 0x00000000, 0x00000000 }, |
| { 0x01000010, 0x20002528, 0x00000ac0, 0x00000ae0 }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0x00000020 }, |
| { 0x01000010, 0x20002528, 0x00000ac2, 0x00000ae2 }, |
| { 0x00010001, 0x235a0169, 0x00000000, 0x04000400 }, |
| { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, |
| { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02180200 }, |
| { 0x00000020, 0x34001c00, 0x00001400, 0x00000240 }, |
| { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
| { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
| { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280300 }, |
| { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x000001f0 }, |
| { 0x00000005, 0x234c0c21, 0x00000b80, 0x1f00ffff }, |
| { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, |
| { 0x00000005, 0x21002d29, 0x00000b80, 0x00030003 }, |
| { 0x00000001, 0x23440061, 0x00000000, 0x00000020 }, |
| { 0x01000010, 0x20002d28, 0x00000100, 0x00030003 }, |
| { 0x00110040, 0x234c0c21, 0x0000034c, 0x00400000 }, |
| { 0x00110020, 0x34001c00, 0x00001400, 0x00000050 }, |
| { 0x02000005, 0x20002d20, 0x00000b84, 0xff00ff00 }, |
| { 0x00010001, 0x23440061, 0x00000000, 0x00000080 }, |
| { 0x00010040, 0x234c0c21, 0x0000034c, 0x00600000 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x000000c0 }, |
| { 0x00000040, 0x234c0c21, 0x0000034c, 0x00400000 }, |
| { 0x00000005, 0x21002d29, 0x00000b80, 0x00030003 }, |
| { 0x01000010, 0x20002d28, 0x00000100, 0x00000000 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000080 }, |
| { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, |
| { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480400 }, |
| { 0x00200001, 0x2ba80021, 0x00450bc0, 0x00000000 }, |
| { 0x00200001, 0x2bb00021, 0x00450be0, 0x00000000 }, |
| { 0x00200001, 0x2bb80021, 0x00450c00, 0x00000000 }, |
| { 0x00600001, 0x28000021, 0x008d0b40, 0x00000000 }, |
| { 0x00600001, 0x28200021, 0x008d0ba0, 0x00000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0200 }, |
| { 0x00000001, 0x23600021, 0x000000b4, 0x00000000 }, |
| { 0x00000001, 0x23640021, 0x000000b8, 0x00000000 }, |
| { 0x00000001, 0x235c0061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x235c0231, 0x00000b85, 0x00000000 }, |
| { 0x00000001, 0x235d0231, 0x00000b86, 0x00000000 }, |
| { 0x00000040, 0x21040c21, 0x00000b08, 0x00000003 }, |
| { 0x00000041, 0x23480c21, 0x00000104, 0x00000010 }, |
| { 0x00000020, 0x34001c00, 0x00001400, 0x000000b0 }, |
| { 0x00200001, 0x23440061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x235c0021, 0x00000b64, 0x00000000 }, |
| { 0x00000001, 0x23600021, 0x00000b68, 0x00000000 }, |
| { 0x00000001, 0x23640061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x23640231, 0x00000b6c, 0x00000000 }, |
| { 0x00000005, 0x234c0c21, 0x00000b60, 0x0000c0ff }, |
| { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e2000 }, |
| { 0x00000001, 0x21000061, 0x00000000, 0x00000000 }, |
| { 0x00000001, 0x21010231, 0x00000b62, 0x00000000 }, |
| { 0x00000005, 0x21002d29, 0x00000100, 0x1f001f00 }, |
| { 0x00000040, 0x234c0421, 0x0000034c, 0x00000100 }, |
| { 0x00600001, 0x28000021, 0x008d01e0, 0x00000000 }, |
| { 0x00600001, 0x28200021, 0x008d0340, 0x00000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0202 }, |
| { 0x00000040, 0x28080c21, 0x00000808, 0x00000002 }, |
| { 0x00600001, 0x28200021, 0x008d0360, 0x00000000 }, |
| { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, |
| { 0x00000040, 0x2ac42d29, 0x00000ac4, 0x00010001 }, |
| { 0x01000010, 0x20002528, 0x00000ac4, 0x00000ae4 }, |
| { 0x00010020, 0x34001c00, 0x00001400, 0x00000090 }, |
| { 0x00000040, 0x21e82c21, 0x000001e8, 0x00030003 }, |
| { 0x00000040, 0x2b080421, 0x00000b08, 0x00000ae8 }, |
| { 0x00000040, 0x2ac02d29, 0x00000ac0, 0x00010001 }, |
| { 0x01000010, 0x20002528, 0x00000ac0, 0x000000aa }, |
| { 0x00010040, 0x2ac22d29, 0x00000ac2, 0x00010001 }, |
| { 0x00010001, 0x2ac00169, 0x00000000, 0x00000000 }, |
| { 0x00000020, 0x34001c00, 0x00001400, 0xfffffb30 }, |
| { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
| { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
| { 0x0a800031, 0x2b601ca1, 0x00000800, 0x0219e002 }, |
| { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, |
| { 0x07000031, 0x24001ca8, 0x00000e00, 0x82000010 }, |
| { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_hsw.inc |
|---|
| 0,0 → 1,195 |
| /* |
| * Copyright © 2010-2013 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Zhao Yakui <yakui.zhao@intel.com> |
| */ |
| /* GRF registers |
| * r0 header |
| * r1~r4 constant buffer (reserved) |
| * r5 inline data |
| * r6~r7 reserved |
| * r8~r15 temporary registers |
| * r16 write back of Oword Block Write |
| */ |
| /* |
| * GRF 0 -- header |
| */ |
| define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ |
| define(`inline_reg0', `r5') |
| define(`buffer_offset', `inline_reg0.0') /* :ud, in units of Owords */ |
| /* :ub, |
| * bit0 indicates the frame type. 1 is the I-frame. 0 is P-B frame |
| */ |
| define(`mb_flag', `inline_reg0.4') |
| define(`qp_flag', `inline_reg0.6') /* :ub */ |
| define(`mb_x', `inline_reg0.8') /* :ub, */ |
| define(`mb_y', `inline_reg0.9') /* :ub, */ |
| define(`mb_xy', `inline_reg0.8') /* :uw, */ |
| /* :uw, the picture width in macroblocks */ |
| define(`width_in_mbs', `inline_reg0.10') |
| /* :w, the number of macroblock commands being processed by the kernel */ |
| define(`total_mbs', `inline_reg0.12') |
| /* ub, the mb x/y of the last mb in slice */ |
| define(`slice_end_x', `inline_reg0.16') |
| define(`slice_end_y', `inline_reg0.17') |
| /* :ud the forward reference picture list */ |
| define(`fwd_ref', `inline_reg0.20') |
| /* :ud the backward reference picture list */ |
| define(`bwd_ref', `inline_reg0.24') |
| /* |
| * GRF 8~15 -- temporary registers |
| */ |
| define(`tmp_reg0', `r8') |
| define(`tmp_reg1', `r9') |
| define(`tmp_reg2', `r10') |
| define(`tmp_reg3', `r11') |
| define(`tmp_reg4', `r12') |
| define(`tmp_reg5', `r13') |
| define(`tmp_reg6', `r14') |
| define(`tmp_reg7', `r15') |
| define(`obw_m0', `tmp_reg7') |
| define(`obw_wb', `null<1>:W') |
| define(`obw_wb_length', `0') |
| /* |
| * GRF 26~27 |
| */ |
| define(`pak_object_reg0', `r26') |
| define(`pak_object0_ud', `r26.0') |
| define(`pak_object1_ud', `r26.4') |
| define(`pak_object2_ud', `r26.8') |
| define(`pak_object3_ud', `r26.12') |
| define(`pak_object4_ud', `r26.16') |
| define(`pak_object5_ud', `r26.20') |
| define(`pak_object6_ud', `r26.24') |
| define(`pak_object7_ud', `r26.28') |
| define(`pak_object_reg1', `r27') |
| define(`pak_object8_ud', `r27.0') |
| define(`pak_object9_ud', `r27.4') |
| define(`pak_object10_ud', `r27.8') |
| define(`pak_object11_ud', `r27.12') |
| /* |
| * Message Payload registers |
| */ |
| define(`msg_ind', `64') |
| define(`msg_reg0', `g64') |
| define(`msg_reg1', `g65') |
| define(`msg_reg2', `g66') |
| define(`msg_reg3', `g67') |
| define(`msg_reg4', `g68') |
| define(`msg_reg5', `g69') |
| define(`msg_reg6', `g70') |
| define(`msg_reg7', `g71') |
| define(`msg_reg8', `g72') |
| define(`MV_BIND_IDX', `0') |
| define(`MFC_BIND_IDX', `2') |
| define(`ts_msg_ind', `112') |
| define(`ts_msg_reg0', `r112') |
| define(`MFC_AVC_PAK_OBJECT_DW0', `0x7149000a') |
| define(`MFC_AVC_PAK_OBJECT_DW4', `0xFFFF0000') /* CBP for Y */ |
| define(`MFC_AVC_PAK_OBJECT_DW5', `0x000F000F') |
| define(`MFC_AVC_PAK_OBJECT_DW10', `0x0000000') |
| define(`OBR_MESSAGE_TYPE', `0') |
| define(`OBR_CACHE_TYPE', `10') |
| define(`OBR_MESSAGE_FENCE', `7') |
| define(`OBR_MF_NOCOMMIT', `0') |
| define(`OBR_MF_COMMIT', `0x20') |
| define(`OBR_CONTROL_0', `0') /* 1 OWord, low 128 bits */ |
| define(`OBR_CONTROL_1', `1') /* 1 OWord, high 128 bits */ |
| define(`OBR_CONTROL_2', `2') /* 2 OWords */ |
| define(`OBR_CONTROL_4', `3') /* 4 OWords */ |
| define(`OBR_CONTROL_8', `4') /* 8 OWords */ |
| define(`OBR_HEADER_PRESENT', `1') |
| define(`OBR_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ |
| define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ |
| define(`OBW_CACHE_TYPE', `10') |
| define(`OBW_MESSAGE_TYPE', `8') |
| define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ |
| define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ |
| define(`OBW_CONTROL_2', `2') /* 2 OWords */ |
| define(`OBW_CONTROL_4', `3') /* 4 OWords */ |
| define(`OBW_CONTROL_8', `4') /* 8 OWords */ |
| define(`OBW_HEADER_PRESENT', `1') |
| define(`INTER_MASK', `0x03') |
| define(`INTER_16X16MODE', `0x0') |
| define(`INTER_16X8MODE', `0x01') |
| define(`INTER_8X16MODE', `0x02') |
| define(`INTER_8X8MODE', `0x03') |
| define(`SUBSHAPE_MASK', `0xFF00') |
| define(`mb_ind', `90') |
| define(`mb_msg0', `r90') |
| define(`mb_wb', `r91') |
| define(`mb_intra_wb', `r91') |
| define(`mb_inter_wb', `r92') |
| define(`mb_mv0', `r93') |
| define(`mb_mv1', `r94') |
| define(`mb_mv2', `r95') |
| define(`mb_mv3', `r96') |
| define(`mb_temp', `r86') |
| define(`cur_mb_x', `mb_temp.0') /* :uw, */ |
| define(`cur_mb_y', `mb_temp.2') /* :uw, */ |
| define(`cur_loop_count', `mb_temp.4') /* :uw, */ |
| define(`mb_end', `r87') |
| define(`end_mb_x', `mb_end.0') /* :uw, */ |
| define(`end_mb_y', `mb_end.2') /* :uw, */ |
| define(`end_loop_count', `mb_end.4') /* :uw, */ |
| /* :ud the length of VME predict result for every mb. Units in owords */ |
| define(`vme_len', `mb_end.8') |
| define(`mb_cur_msg', `r88') |
| define(`INTRA_SLICE', `0x0001') |
| define(`MFC_AVC_PAK_LAST_MB', `0x0400') |
| define(`MFC_AVC_INTER_MASK_DW3', `0x1F00FFFF') |
| define(`MFC_AVC_INTRA_MASK_DW3', `0x0000C0FF') |
| define(`INTER_MV8', `0x00400000') |
| define(`INTER_MV32', `0x00600000') |
| define(`MFC_AVC_PAK_CBP', `0x000E0000') |
| define(`MFC_AVC_INTRA_FLAG', `0x00002000') |
| define(`AVC_INTRA_MASK', `0x1F00') |
| /contrib/sdk/sources/vaapi/intel-driver-1.4.1/src/shaders/utils/mfc_batchbuffer_tail.asm |
|---|
| 0,0 → 1,100 |
| /* |
| * Copyright © 2012 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| * |
| * Authors: |
| * Xiang Haihao <haihao.xiang@intel.com> |
| */ |
| __TAIL: |
| (f0.1)jmpi (1) __EXIT ; |
| __TAIL_LOOP: |
| mov (8) msg_reg0.0<1>:ud tmp_slice_header<8,8,1>:ud {align1} ; |
| send (16) |
| msg_ind |
| ob_read_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_READ, |
| OB_CONTROL_0, |
| BIND_IDX_MFC_SLICE_HEADER, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 1 |
| rlen ob_read_wb_len_slice_header |
| {align1}; |
| mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; |
| mov (8) msg_reg1.0<1>:ud ob_read_wb0<8,8,1>:ud {align1} ; |
| send (16) |
| msg_ind |
| ob_write_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_WRITE, |
| OB_CONTROL_0, |
| BIND_IDX_MFC_BATCHBUFFER, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 2 |
| rlen ob_write_wb_length |
| {align1}; |
| /* the new offset */ |
| add (1) tmp_slice_header.8<1>:ud tmp_slice_header.8<0,1,0>:ud 1:ud {align1} ; |
| add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 1:ud {align1} ; |
| add.z.f0.0 (1) tail_size<1>:w tail_size<0,1,0>:w -1:w {align1}; |
| (-f0.0)jmpi (1) __TAIL_LOOP ; |
| __DONE: |
| and.z.f0.0 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_SLICE {align1}; |
| (f0.0)jmpi (1) __EXIT ; |
| /* bind index 5, write 1 oword, msg type: 8(OWord Block Write) */ |
| mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; |
| mov (4) msg_reg1.0<1>:ud 0x0:ud {align1} ; |
| mov (1) msg_reg1.4<1>:ud MI_BATCH_BUFFER_END {align1} ; |
| send (16) |
| msg_ind |
| ob_write_wb |
| null |
| data_port( |
| OB_CACHE_TYPE, |
| OB_WRITE, |
| OB_CONTROL_0, |
| BIND_IDX_MFC_BATCHBUFFER, |
| OB_WRITE_COMMIT_CATEGORY, |
| OB_HEADER_PRESENT |
| ) |
| mlen 2 |
| rlen ob_write_wb_length |
| {align1}; |