/contrib/sdk/sources/libdrm/include/drm/drm.h |
---|
38,6 → 38,7 |
#include <stdint.h> |
#include <sys/types.h> |
typedef int8_t __s8; |
typedef uint8_t __u8; |
typedef int16_t __s16; |
627,6 → 628,13 |
*/ |
#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 |
/** |
* DRM_CLIENT_CAP_ATOMIC |
* |
* If set to 1, the DRM core will allow atomic modesetting requests. |
*/ |
#define DRM_CLIENT_CAP_ATOMIC 3 |
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ |
struct drm_set_client_cap { |
__u64 capability; |
673,8 → 681,9 |
#define SRV_MASK_UPDATE 45 |
#define SRV_MASK_UPDATE_EX 46 |
#define SRV_I915_GEM_PREAD 47 |
#define SRV_I915_GEM_EXECBUFFER 48 |
#include "drm_mode.h" |
#define DRM_IOCTL_BASE 'd' |
829,6 → 838,7 |
#define DRM_CAP_PRIME 0x5 |
#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 |
#define DRM_CAP_ASYNC_PAGE_FLIP 0x7 |
#define DRM_CAP_ADDFB2_MODIFIERS 0x10 |
#define DRM_PRIME_CAP_IMPORT 0x1 |
#define DRM_PRIME_CAP_EXPORT 0x2 |
/contrib/sdk/sources/libdrm/include/drm/drm_fourcc.h |
---|
127,4 → 127,97 |
#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ |
#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ |
/* |
* Format Modifiers: |
* |
* Format modifiers describe, typically, a re-ordering or modification |
* of the data in a plane of an FB. This can be used to express tiled/ |
* swizzled formats, or compression, or a combination of the two. |
* |
* The upper 8 bits of the format modifier are a vendor-id as assigned |
* below. The lower 56 bits are assigned as vendor sees fit. |
*/ |
/* Vendor Ids: */ |
#define DRM_FORMAT_MOD_NONE 0 |
#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 |
#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 |
#define DRM_FORMAT_MOD_VENDOR_NV 0x03 |
#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 |
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 |
/* add more to the end as needed */ |
#define fourcc_mod_code(vendor, val) \ |
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) |
/* |
* Format Modifier tokens: |
* |
* When adding a new token please document the layout with a code comment, |
* similar to the fourcc codes above. drm_fourcc.h is considered the |
* authoritative source for all of these. |
*/ |
/* Intel framebuffer modifiers */ |
/* |
* Intel X-tiling layout |
* |
* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) |
* in row-major layout. Within the tile bytes are laid out row-major, with |
* a platform-dependent stride. On top of that the memory can apply |
* platform-depending swizzling of some higher address bits into bit6. |
* |
* This format is highly platforms specific and not useful for cross-driver |
* sharing. It exists since on a given platform it does uniquely identify the |
* layout in a simple way for i915-specific userspace. |
*/ |
#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) |
/* |
* Intel Y-tiling layout |
* |
* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) |
* in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) |
* chunks column-major, with a platform-dependent height. On top of that the |
* memory can apply platform-depending swizzling of some higher address bits |
* into bit6. |
* |
* This format is highly platforms specific and not useful for cross-driver |
* sharing. It exists since on a given platform it does uniquely identify the |
* layout in a simple way for i915-specific userspace. |
*/ |
#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) |
/* |
* Intel Yf-tiling layout |
* |
* This is a tiled layout using 4Kb tiles in row-major layout. |
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which |
* are arranged in four groups (two wide, two high) with column-major layout. |
* Each group therefore consits out of four 256 byte units, which are also laid |
* out as 2x2 column-major. |
* 256 byte units are made out of four 64 byte blocks of pixels, producing |
* either a square block or a 2:1 unit. |
* 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width |
* in pixel depends on the pixel depth. |
*/ |
#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) |
/* |
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
* |
* Macroblocks are laid in a Z-shape, and each pixel data is following the |
* standard NV12 style. |
* As for NV12, an image is the result of two frame buffers: one for Y, |
* one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). |
* Alignment requirements are (for each buffer): |
* - multiple of 128 pixels for the width |
* - multiple of 32 pixels for the height |
* |
* For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html |
*/ |
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) |
#endif /* DRM_FOURCC_H */ |
/contrib/sdk/sources/libdrm/include/drm/drm_mode.h |
---|
173,6 → 173,9 |
#define DRM_MODE_ENCODER_TMDS 2 |
#define DRM_MODE_ENCODER_LVDS 3 |
#define DRM_MODE_ENCODER_TVDAC 4 |
#define DRM_MODE_ENCODER_VIRTUAL 5 |
#define DRM_MODE_ENCODER_DSI 6 |
#define DRM_MODE_ENCODER_DPMST 7 |
struct drm_mode_get_encoder { |
__u32 encoder_id; |
210,6 → 213,8 |
#define DRM_MODE_CONNECTOR_HDMIB 12 |
#define DRM_MODE_CONNECTOR_TV 13 |
#define DRM_MODE_CONNECTOR_eDP 14 |
#define DRM_MODE_CONNECTOR_VIRTUAL 15 |
#define DRM_MODE_CONNECTOR_DSI 16 |
struct drm_mode_get_connector { |
239,6 → 244,21 |
#define DRM_MODE_PROP_BLOB (1<<4) |
#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ |
/* non-extended types: legacy bitmask, one bit per type: */ |
#define DRM_MODE_PROP_LEGACY_TYPE ( \ |
DRM_MODE_PROP_RANGE | \ |
DRM_MODE_PROP_ENUM | \ |
DRM_MODE_PROP_BLOB | \ |
DRM_MODE_PROP_BITMASK) |
/* extended-types: rather than continue to consume a bit per type, |
* grab a chunk of the bits to use as integer type id. |
*/ |
#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0 |
#define DRM_MODE_PROP_TYPE(n) ((n) << 6) |
#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1) |
#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2) |
struct drm_mode_property_enum { |
__u64 value; |
char name[DRM_PROP_NAME_LEN]; |
303,6 → 323,7 |
}; |
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ |
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ |
struct drm_mode_fb_cmd2 { |
__u32 fb_id; |
323,10 → 344,18 |
* So it would consist of Y as offset[0] and UV as |
* offset[1]. Note that offset[0] will generally |
* be 0. |
* |
* To accommodate tiled, compressed, etc formats, a per-plane |
* modifier can be specified. The default value of zero |
* indicates "native" format as specified by the fourcc. |
* Vendor specific modifier token. This allows, for example, |
* different tiling/swizzling pattern on different planes. |
* See discussion above of DRM_FORMAT_MOD_xxx. |
*/ |
__u32 handles[4]; |
__u32 pitches[4]; /* pitch for each plane */ |
__u32 offsets[4]; /* offset of each plane */ |
__u64 modifier[4]; /* ie, tiling, compressed (per plane) */ |
}; |
#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 |
487,4 → 516,41 |
__u32 handle; |
}; |
/* page-flip flags are valid, plus: */ |
#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100 |
#define DRM_MODE_ATOMIC_NONBLOCK 0x0200 |
#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400 |
struct drm_mode_atomic { |
__u32 flags; |
__u32 count_objs; |
__u64 objs_ptr; |
__u64 count_props_ptr; |
__u64 props_ptr; |
__u64 prop_values_ptr; |
__u64 reserved; |
__u64 user_data; |
}; |
/** |
* Create a new 'blob' data property, copying length bytes from data pointer, |
* and returning new blob ID. |
*/ |
struct drm_mode_create_blob { |
/** Pointer to data to copy. */ |
__u64 data; |
/** Length of data to copy. */ |
__u32 length; |
/** Return: new property ID. */ |
__u32 blob_id; |
}; |
/** |
* Destroy a user-created blob property. |
*/ |
struct drm_mode_destroy_blob { |
__u32 blob_id; |
}; |
#endif |
/contrib/sdk/sources/libdrm/include/drm/i915_drm.h |
---|
171,8 → 171,12 |
#define I915_BOX_TEXTURE_LOAD 0x8 |
#define I915_BOX_LOST_CONTEXT 0x10 |
/* I915 specific ioctls |
* The device specific ioctl range is 0x40 to 0x79. |
/* |
* i915 specific ioctls. |
* |
* The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie |
* [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset |
* against DRM_COMMAND_BASE and should be between [0x0, 0x60). |
*/ |
#define DRM_I915_INIT 0x00 |
#define DRM_I915_FLUSH 0x01 |
243,7 → 247,7 |
#define DRM_IOCTL_I915_VBLANK_SWAP |
#define DRM_IOCTL_I915_HWS_ADDR |
#define DRM_IOCTL_I915_GEM_INIT |
#define DRM_IOCTL_I915_GEM_EXECBUFFER |
#define DRM_IOCTL_I915_GEM_EXECBUFFER SRV_I915_GEM_EXECBUFFER |
#define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2 |
#define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN |
#define DRM_IOCTL_I915_GEM_UNPIN SRV_I915_GEM_UNPIN |
254,7 → 258,7 |
#define DRM_IOCTL_I915_GEM_ENTERVT |
#define DRM_IOCTL_I915_GEM_LEAVEVT |
#define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE |
#define DRM_IOCTL_I915_GEM_PREAD |
#define DRM_IOCTL_I915_GEM_PREAD SRV_I915_GEM_PREAD |
#define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE |
#define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP |
#define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT |
340,9 → 344,21 |
#define I915_PARAM_HAS_WT 27 |
#define I915_PARAM_CMD_PARSER_VERSION 28 |
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
#define I915_PARAM_MMAP_VERSION 30 |
#define I915_PARAM_HAS_BSD2 31 |
#define I915_PARAM_REVISION 32 |
#define I915_PARAM_SUBSLICE_TOTAL 33 |
#define I915_PARAM_EU_TOTAL 34 |
#define I915_PARAM_HAS_GPU_RESET 35 |
#define I915_PARAM_HAS_RESOURCE_STREAMER 36 |
#define I915_PARAM_HAS_EXEC_SOFTPIN 37 |
typedef struct drm_i915_getparam { |
int param; |
/* |
* WARNING: Using pointers instead of fixed-size u64 means we need to write |
* compat32 code. Don't repeat this mistake. |
*/ |
int *value; |
} drm_i915_getparam_t; |
487,6 → 503,14 |
* This is a fixed-size type for 32/64 compatibility. |
*/ |
__u64 addr_ptr; |
/** |
* Flags for extended behaviour. |
* |
* Added in version 2. |
*/ |
__u64 flags; |
#define I915_MMAP_WC 0x1 |
}; |
struct drm_i915_gem_mmap_gtt { |
654,8 → 678,12 |
__u64 alignment; |
/** |
* Returned value of the updated offset of the object, for future |
* presumed_offset writes. |
* When the EXEC_OBJECT_PINNED flag is specified this is populated by |
* the user with the GTT offset at which this object will be pinned. |
* When the I915_EXEC_NO_RELOC flag is specified this must contain the |
* presumed_offset of the object. |
* During execbuffer2 the kernel populates it with the value of the |
* current GTT offset of the object, for future presumed_offset writes. |
*/ |
__u64 offset; |
662,7 → 690,9 |
#define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
#define EXEC_OBJECT_NEEDS_GTT (1<<1) |
#define EXEC_OBJECT_WRITE (1<<2) |
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) |
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) |
#define EXEC_OBJECT_PINNED (1<<4) |
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1) |
__u64 flags; |
__u64 rsvd1; |
736,8 → 766,19 |
*/ |
#define I915_EXEC_HANDLE_LUT (1<<12) |
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) |
/** Used for switching BSD rings on the platforms with two BSD rings */ |
#define I915_EXEC_BSD_MASK (3<<13) |
#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ |
#define I915_EXEC_BSD_RING1 (1<<13) |
#define I915_EXEC_BSD_RING2 (2<<13) |
/** Tell the kernel that the batchbuffer is processed by |
* the resource streamer. |
*/ |
#define I915_EXEC_RESOURCE_STREAMER (1<<15) |
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) |
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
#define i915_execbuffer2_set_context_id(eb2, context) \ |
(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
972,6 → 1013,7 |
/* flags */ |
#define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
#define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) |
struct drm_intel_overlay_attrs { |
__u32 flags; |
__u32 color_key; |
1038,9 → 1080,23 |
}; |
struct drm_i915_reg_read { |
/* |
* Register offset. |
* For 64bit wide registers where the upper 32bits don't immediately |
* follow the lower 32bits, the offset of the lower 32bits must |
* be specified |
*/ |
__u64 offset; |
__u64 val; /* Return value */ |
}; |
/* Known registers: |
* |
* Render engine timestamp - 0x2358 + 64bit - gen7+ |
* - Note this register returns an invalid value if using the default |
* single instruction 8byte read, in order to workaround that use |
* offset (0x2538 | 1) instead. |
* |
*/ |
struct drm_i915_reset_stats { |
__u32 ctx_id; |
1072,6 → 1128,16 |
__u32 handle; |
}; |
struct drm_i915_gem_context_param { |
__u32 ctx_id; |
__u32 size; |
__u64 param; |
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 |
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 |
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 |
__u64 value; |
}; |
struct drm_i915_mask { |
__u32 handle; |
__u32 width; |