WebSVN – Kolibri OS – Path Comparison – / – /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/ Rev 5563 and /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/ Rev 5564

Regard whitespace Rev 5563 → Rev 5564

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
 ,0 → 1,2828
+#ifndef A3XX_XML
+#define A3XX_XML
+/* Autogenerated file, DO NOT EDIT manually!
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://github.com/freedreno/envytools/
+git clone https://github.com/freedreno/envytools.git
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  59314 bytes, from 2015-04-19 16:21:40)
+Copyright (C) 2013-2015 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+enum a3xx_tile_mode {
+        LINEAR = 0,
+        TILE_32X32 = 2,
+};
+enum a3xx_state_block_id {
+        HLSQ_BLOCK_ID_TP_TEX = 2,
+        HLSQ_BLOCK_ID_TP_MIPMAP = 3,
+        HLSQ_BLOCK_ID_SP_VS = 4,
+        HLSQ_BLOCK_ID_SP_FS = 6,
+};
+enum a3xx_cache_opcode {
+        INVALIDATE = 1,
+};
+enum a3xx_vtx_fmt {
+        VFMT_32_FLOAT = 0,
+        VFMT_32_32_FLOAT = 1,
+        VFMT_32_32_32_FLOAT = 2,
+        VFMT_32_32_32_32_FLOAT = 3,
+        VFMT_16_FLOAT = 4,
+        VFMT_16_16_FLOAT = 5,
+        VFMT_16_16_16_FLOAT = 6,
+        VFMT_16_16_16_16_FLOAT = 7,
+        VFMT_32_FIXED = 8,
+        VFMT_32_32_FIXED = 9,
+        VFMT_32_32_32_FIXED = 10,
+        VFMT_32_32_32_32_FIXED = 11,
+        VFMT_16_SINT = 16,
+        VFMT_16_16_SINT = 17,
+        VFMT_16_16_16_SINT = 18,
+        VFMT_16_16_16_16_SINT = 19,
+        VFMT_16_UINT = 20,
+        VFMT_16_16_UINT = 21,
+        VFMT_16_16_16_UINT = 22,
+        VFMT_16_16_16_16_UINT = 23,
+        VFMT_16_SNORM = 24,
+        VFMT_16_16_SNORM = 25,
+        VFMT_16_16_16_SNORM = 26,
+        VFMT_16_16_16_16_SNORM = 27,
+        VFMT_16_UNORM = 28,
+        VFMT_16_16_UNORM = 29,
+        VFMT_16_16_16_UNORM = 30,
+        VFMT_16_16_16_16_UNORM = 31,
+        VFMT_32_UINT = 32,
+        VFMT_32_32_UINT = 33,
+        VFMT_32_32_32_UINT = 34,
+        VFMT_32_32_32_32_UINT = 35,
+        VFMT_32_SINT = 36,
+        VFMT_32_32_SINT = 37,
+        VFMT_32_32_32_SINT = 38,
+        VFMT_32_32_32_32_SINT = 39,
+        VFMT_8_UINT = 40,
+        VFMT_8_8_UINT = 41,
+        VFMT_8_8_8_UINT = 42,
+        VFMT_8_8_8_8_UINT = 43,
+        VFMT_8_UNORM = 44,
+        VFMT_8_8_UNORM = 45,
+        VFMT_8_8_8_UNORM = 46,
+        VFMT_8_8_8_8_UNORM = 47,
+        VFMT_8_SINT = 48,
+        VFMT_8_8_SINT = 49,
+        VFMT_8_8_8_SINT = 50,
+        VFMT_8_8_8_8_SINT = 51,
+        VFMT_8_SNORM = 52,
+        VFMT_8_8_SNORM = 53,
+        VFMT_8_8_8_SNORM = 54,
+        VFMT_8_8_8_8_SNORM = 55,
+        VFMT_10_10_10_2_UINT = 60,
+        VFMT_10_10_10_2_UNORM = 61,
+        VFMT_10_10_10_2_SINT = 62,
+        VFMT_10_10_10_2_SNORM = 63,
+};
+enum a3xx_tex_fmt {
+        TFMT_5_6_5_UNORM = 4,
+        TFMT_5_5_5_1_UNORM = 5,
+        TFMT_4_4_4_4_UNORM = 7,
+        TFMT_Z16_UNORM = 9,
+        TFMT_X8Z24_UNORM = 10,
+        TFMT_Z32_FLOAT = 11,
+        TFMT_NV12_UV_TILED = 17,
+        TFMT_NV12_Y_TILED = 19,
+        TFMT_NV12_UV = 21,
+        TFMT_NV12_Y = 23,
+        TFMT_I420_Y = 24,
+        TFMT_I420_U = 26,
+        TFMT_I420_V = 27,
+        TFMT_ATC_RGB = 32,
+        TFMT_ATC_RGBA_EXPLICIT = 33,
+        TFMT_ETC1 = 34,
+        TFMT_ATC_RGBA_INTERPOLATED = 35,
+        TFMT_DXT1 = 36,
+        TFMT_DXT3 = 37,
+        TFMT_DXT5 = 38,
+        TFMT_10_10_10_2_UNORM = 41,
+        TFMT_9_9_9_E5_FLOAT = 42,
+        TFMT_11_11_10_FLOAT = 43,
+        TFMT_A8_UNORM = 44,
+        TFMT_L8_A8_UNORM = 47,
+        TFMT_8_UNORM = 48,
+        TFMT_8_8_UNORM = 49,
+        TFMT_8_8_8_UNORM = 50,
+        TFMT_8_8_8_8_UNORM = 51,
+        TFMT_8_SNORM = 52,
+        TFMT_8_8_SNORM = 53,
+        TFMT_8_8_8_SNORM = 54,
+        TFMT_8_8_8_8_SNORM = 55,
+        TFMT_8_UINT = 56,
+        TFMT_8_8_UINT = 57,
+        TFMT_8_8_8_UINT = 58,
+        TFMT_8_8_8_8_UINT = 59,
+        TFMT_8_SINT = 60,
+        TFMT_8_8_SINT = 61,
+        TFMT_8_8_8_SINT = 62,
+        TFMT_8_8_8_8_SINT = 63,
+        TFMT_16_FLOAT = 64,
+        TFMT_16_16_FLOAT = 65,
+        TFMT_16_16_16_16_FLOAT = 67,
+        TFMT_16_UINT = 68,
+        TFMT_16_16_UINT = 69,
+        TFMT_16_16_16_16_UINT = 71,
+        TFMT_16_SINT = 72,
+        TFMT_16_16_SINT = 73,
+        TFMT_16_16_16_16_SINT = 75,
+        TFMT_16_UNORM = 76,
+        TFMT_16_16_UNORM = 77,
+        TFMT_16_16_16_16_UNORM = 79,
+        TFMT_16_SNORM = 80,
+        TFMT_16_16_SNORM = 81,
+        TFMT_16_16_16_16_SNORM = 83,
+        TFMT_32_FLOAT = 84,
+        TFMT_32_32_FLOAT = 85,
+        TFMT_32_32_32_32_FLOAT = 87,
+        TFMT_32_UINT = 88,
+        TFMT_32_32_UINT = 89,
+        TFMT_32_32_32_32_UINT = 91,
+        TFMT_32_SINT = 92,
+        TFMT_32_32_SINT = 93,
+        TFMT_32_32_32_32_SINT = 95,
+        TFMT_ETC2_RG11_SNORM = 112,
+        TFMT_ETC2_RG11_UNORM = 113,
+        TFMT_ETC2_R11_SNORM = 114,
+        TFMT_ETC2_R11_UNORM = 115,
+        TFMT_ETC2_RGBA8 = 116,
+        TFMT_ETC2_RGB8A1 = 117,
+        TFMT_ETC2_RGB8 = 118,
+};
+enum a3xx_tex_fetchsize {
+        TFETCH_DISABLE = 0,
+        TFETCH_1_BYTE = 1,
+        TFETCH_2_BYTE = 2,
+        TFETCH_4_BYTE = 3,
+        TFETCH_8_BYTE = 4,
+        TFETCH_16_BYTE = 5,
+};
+enum a3xx_color_fmt {
+        RB_R5G6B5_UNORM = 0,
+        RB_R5G5B5A1_UNORM = 1,
+        RB_R4G4B4A4_UNORM = 3,
+        RB_R8G8B8_UNORM = 4,
+        RB_R8G8B8A8_UNORM = 8,
+        RB_R8G8B8A8_SNORM = 9,
+        RB_R8G8B8A8_UINT = 10,
+        RB_R8G8B8A8_SINT = 11,
+        RB_R8G8_UNORM = 12,
+        RB_R8G8_SNORM = 13,
+        RB_R8_UINT = 14,
+        RB_R8_SINT = 15,
+        RB_R10G10B10A2_UNORM = 16,
+        RB_A8_UNORM = 20,
+        RB_R8_UNORM = 21,
+        RB_R16_FLOAT = 24,
+        RB_R16G16_FLOAT = 25,
+        RB_R16G16B16A16_FLOAT = 27,
+        RB_R11G11B10_FLOAT = 28,
+        RB_R16_SNORM = 32,
+        RB_R16G16_SNORM = 33,
+        RB_R16G16B16A16_SNORM = 35,
+        RB_R16_UNORM = 36,
+        RB_R16G16_UNORM = 37,
+        RB_R16G16B16A16_UNORM = 39,
+        RB_R16_SINT = 40,
+        RB_R16G16_SINT = 41,
+        RB_R16G16B16A16_SINT = 43,
+        RB_R16_UINT = 44,
+        RB_R16G16_UINT = 45,
+        RB_R16G16B16A16_UINT = 47,
+        RB_R32_FLOAT = 48,
+        RB_R32G32_FLOAT = 49,
+        RB_R32G32B32A32_FLOAT = 51,
+        RB_R32_SINT = 52,
+        RB_R32G32_SINT = 53,
+        RB_R32G32B32A32_SINT = 55,
+        RB_R32_UINT = 56,
+        RB_R32G32_UINT = 57,
+        RB_R32G32B32A32_UINT = 59,
+};
+enum a3xx_sp_perfcounter_select {
+        SP_FS_CFLOW_INSTRUCTIONS = 12,
+        SP_FS_FULL_ALU_INSTRUCTIONS = 14,
+        SP0_ICL1_MISSES = 26,
+        SP_ALU_ACTIVE_CYCLES = 29,
+};
+enum a3xx_rop_code {
+        ROP_CLEAR = 0,
+        ROP_NOR = 1,
+        ROP_AND_INVERTED = 2,
+        ROP_COPY_INVERTED = 3,
+        ROP_AND_REVERSE = 4,
+        ROP_INVERT = 5,
+        ROP_XOR = 6,
+        ROP_NAND = 7,
+        ROP_AND = 8,
+        ROP_EQUIV = 9,
+        ROP_NOOP = 10,
+        ROP_OR_INVERTED = 11,
+        ROP_COPY = 12,
+        ROP_OR_REVERSE = 13,
+        ROP_OR = 14,
+        ROP_SET = 15,
+};
+enum a3xx_rb_blend_opcode {
+        BLEND_DST_PLUS_SRC = 0,
+        BLEND_SRC_MINUS_DST = 1,
+        BLEND_DST_MINUS_SRC = 2,
+        BLEND_MIN_DST_SRC = 3,
+        BLEND_MAX_DST_SRC = 4,
+};
+enum a3xx_intp_mode {
+        SMOOTH = 0,
+        FLAT = 1,
+};
+enum a3xx_repl_mode {
+        S = 1,
+        T = 2,
+        ONE_T = 3,
+};
+enum a3xx_tex_filter {
+        A3XX_TEX_NEAREST = 0,
+        A3XX_TEX_LINEAR = 1,
+        A3XX_TEX_ANISO = 2,
+};
+enum a3xx_tex_clamp {
+        A3XX_TEX_REPEAT = 0,
+        A3XX_TEX_CLAMP_TO_EDGE = 1,
+        A3XX_TEX_MIRROR_REPEAT = 2,
+        A3XX_TEX_CLAMP_TO_BORDER = 3,
+        A3XX_TEX_MIRROR_CLAMP = 4,
+};
+enum a3xx_tex_aniso {
+        A3XX_TEX_ANISO_1 = 0,
+        A3XX_TEX_ANISO_2 = 1,
+        A3XX_TEX_ANISO_4 = 2,
+        A3XX_TEX_ANISO_8 = 3,
+        A3XX_TEX_ANISO_16 = 4,
+};
+enum a3xx_tex_swiz {
+        A3XX_TEX_X = 0,
+        A3XX_TEX_Y = 1,
+        A3XX_TEX_Z = 2,
+        A3XX_TEX_W = 3,
+        A3XX_TEX_ZERO = 4,
+        A3XX_TEX_ONE = 5,
+};
+enum a3xx_tex_type {
+        A3XX_TEX_1D = 0,
+        A3XX_TEX_2D = 1,
+        A3XX_TEX_CUBE = 2,
+        A3XX_TEX_3D = 3,
+};
+#define A3XX_INT0_RBBM_GPU_IDLE                                 0x00000001
+#define A3XX_INT0_RBBM_AHB_ERROR                                0x00000002
+#define A3XX_INT0_RBBM_REG_TIMEOUT                              0x00000004
+#define A3XX_INT0_RBBM_ME_MS_TIMEOUT                            0x00000008
+#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT                           0x00000010
+#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW                         0x00000020
+#define A3XX_INT0_VFD_ERROR                                     0x00000040
+#define A3XX_INT0_CP_SW_INT                                     0x00000080
+#define A3XX_INT0_CP_T0_PACKET_IN_IB                            0x00000100
+#define A3XX_INT0_CP_OPCODE_ERROR                               0x00000200
+#define A3XX_INT0_CP_RESERVED_BIT_ERROR                         0x00000400
+#define A3XX_INT0_CP_HW_FAULT                                   0x00000800
+#define A3XX_INT0_CP_DMA                                        0x00001000
+#define A3XX_INT0_CP_IB2_INT                                    0x00002000
+#define A3XX_INT0_CP_IB1_INT                                    0x00004000
+#define A3XX_INT0_CP_RB_INT                                     0x00008000
+#define A3XX_INT0_CP_REG_PROTECT_FAULT                          0x00010000
+#define A3XX_INT0_CP_RB_DONE_TS                                 0x00020000
+#define A3XX_INT0_CP_VS_DONE_TS                                 0x00040000
+#define A3XX_INT0_CP_PS_DONE_TS                                 0x00080000
+#define A3XX_INT0_CACHE_FLUSH_TS                                0x00100000
+#define A3XX_INT0_CP_AHB_ERROR_HALT                             0x00200000
+#define A3XX_INT0_MISC_HANG_DETECT                              0x01000000
+#define A3XX_INT0_UCHE_OOB_ACCESS                               0x02000000
+#define REG_A3XX_RBBM_HW_VERSION                                0x00000000
+#define REG_A3XX_RBBM_HW_RELEASE                                0x00000001
+#define REG_A3XX_RBBM_HW_CONFIGURATION                          0x00000002
+#define REG_A3XX_RBBM_CLOCK_CTL                                 0x00000010
+#define REG_A3XX_RBBM_SP_HYST_CNT                               0x00000012
+#define REG_A3XX_RBBM_SW_RESET_CMD                              0x00000018
+#define REG_A3XX_RBBM_AHB_CTL0                                  0x00000020
+#define REG_A3XX_RBBM_AHB_CTL1                                  0x00000021
+#define REG_A3XX_RBBM_AHB_CMD                                   0x00000022
+#define REG_A3XX_RBBM_AHB_ERROR_STATUS                          0x00000027
+#define REG_A3XX_RBBM_GPR0_CTL                                  0x0000002e
+#define REG_A3XX_RBBM_STATUS                                    0x00000030
+#define A3XX_RBBM_STATUS_HI_BUSY                                0x00000001
+#define A3XX_RBBM_STATUS_CP_ME_BUSY                             0x00000002
+#define A3XX_RBBM_STATUS_CP_PFP_BUSY                            0x00000004
+#define A3XX_RBBM_STATUS_CP_NRT_BUSY                            0x00004000
+#define A3XX_RBBM_STATUS_VBIF_BUSY                              0x00008000
+#define A3XX_RBBM_STATUS_TSE_BUSY                               0x00010000
+#define A3XX_RBBM_STATUS_RAS_BUSY                               0x00020000
+#define A3XX_RBBM_STATUS_RB_BUSY                                0x00040000
+#define A3XX_RBBM_STATUS_PC_DCALL_BUSY                          0x00080000
+#define A3XX_RBBM_STATUS_PC_VSD_BUSY                            0x00100000
+#define A3XX_RBBM_STATUS_VFD_BUSY                               0x00200000
+#define A3XX_RBBM_STATUS_VPC_BUSY                               0x00400000
+#define A3XX_RBBM_STATUS_UCHE_BUSY                              0x00800000
+#define A3XX_RBBM_STATUS_SP_BUSY                                0x01000000
+#define A3XX_RBBM_STATUS_TPL1_BUSY                              0x02000000
+#define A3XX_RBBM_STATUS_MARB_BUSY                              0x04000000
+#define A3XX_RBBM_STATUS_VSC_BUSY                               0x08000000
+#define A3XX_RBBM_STATUS_ARB_BUSY                               0x10000000
+#define A3XX_RBBM_STATUS_HLSQ_BUSY                              0x20000000
+#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC                          0x40000000
+#define A3XX_RBBM_STATUS_GPU_BUSY                               0x80000000
+#define REG_A3XX_RBBM_NQWAIT_UNTIL                              0x00000040
+#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL                      0x00000033
+#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL                    0x00000050
+#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0                  0x00000051
+#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1                  0x00000054
+#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2                  0x00000057
+#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3                  0x0000005a
+#define REG_A3XX_RBBM_INT_SET_CMD                               0x00000060
+#define REG_A3XX_RBBM_INT_CLEAR_CMD                             0x00000061
+#define REG_A3XX_RBBM_INT_0_MASK                                0x00000063
+#define REG_A3XX_RBBM_INT_0_STATUS                              0x00000064
+#define REG_A3XX_RBBM_PERFCTR_CTL                               0x00000080
+#define A3XX_RBBM_PERFCTR_CTL_ENABLE                            0x00000001
+#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0                         0x00000081
+#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1                         0x00000082
+#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO                     0x00000084
+#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI                     0x00000085
+#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT                       0x00000086
+#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT                       0x00000087
+#define REG_A3XX_RBBM_GPU_BUSY_MASKED                           0x00000088
+#define REG_A3XX_RBBM_PERFCTR_CP_0_LO                           0x00000090
+#define REG_A3XX_RBBM_PERFCTR_CP_0_HI                           0x00000091
+#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO                         0x00000092
+#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI                         0x00000093
+#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO                         0x00000094
+#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI                         0x00000095
+#define REG_A3XX_RBBM_PERFCTR_PC_0_LO                           0x00000096
+#define REG_A3XX_RBBM_PERFCTR_PC_0_HI                           0x00000097
+#define REG_A3XX_RBBM_PERFCTR_PC_1_LO                           0x00000098
+#define REG_A3XX_RBBM_PERFCTR_PC_1_HI                           0x00000099
+#define REG_A3XX_RBBM_PERFCTR_PC_2_LO                           0x0000009a
+#define REG_A3XX_RBBM_PERFCTR_PC_2_HI                           0x0000009b
+#define REG_A3XX_RBBM_PERFCTR_PC_3_LO                           0x0000009c
+#define REG_A3XX_RBBM_PERFCTR_PC_3_HI                           0x0000009d
+#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO                          0x0000009e
+#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI                          0x0000009f
+#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO                          0x000000a0
+#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI                          0x000000a1
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO                         0x000000a2
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI                         0x000000a3
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO                         0x000000a4
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI                         0x000000a5
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO                         0x000000a6
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI                         0x000000a7
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO                         0x000000a8
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI                         0x000000a9
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO                         0x000000aa
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI                         0x000000ab
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO                         0x000000ac
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI                         0x000000ad
+#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO                          0x000000ae
+#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI                          0x000000af
+#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO                          0x000000b0
+#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI                          0x000000b1
+#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO                          0x000000b2
+#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI                          0x000000b3
+#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO                          0x000000b4
+#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI                          0x000000b5
+#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO                          0x000000b6
+#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI                          0x000000b7
+#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO                          0x000000b8
+#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI                          0x000000b9
+#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO                         0x000000ba
+#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI                         0x000000bb
+#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO                         0x000000bc
+#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI                         0x000000bd
+#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO                         0x000000be
+#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI                         0x000000bf
+#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO                         0x000000c0
+#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI                         0x000000c1
+#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO                         0x000000c2
+#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI                         0x000000c3
+#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO                         0x000000c4
+#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI                         0x000000c5
+#define REG_A3XX_RBBM_PERFCTR_TP_0_LO                           0x000000c6
+#define REG_A3XX_RBBM_PERFCTR_TP_0_HI                           0x000000c7
+#define REG_A3XX_RBBM_PERFCTR_TP_1_LO                           0x000000c8
+#define REG_A3XX_RBBM_PERFCTR_TP_1_HI                           0x000000c9
+#define REG_A3XX_RBBM_PERFCTR_TP_2_LO                           0x000000ca
+#define REG_A3XX_RBBM_PERFCTR_TP_2_HI                           0x000000cb
+#define REG_A3XX_RBBM_PERFCTR_TP_3_LO                           0x000000cc
+#define REG_A3XX_RBBM_PERFCTR_TP_3_HI                           0x000000cd
+#define REG_A3XX_RBBM_PERFCTR_TP_4_LO                           0x000000ce
+#define REG_A3XX_RBBM_PERFCTR_TP_4_HI                           0x000000cf
+#define REG_A3XX_RBBM_PERFCTR_TP_5_LO                           0x000000d0
+#define REG_A3XX_RBBM_PERFCTR_TP_5_HI                           0x000000d1
+#define REG_A3XX_RBBM_PERFCTR_SP_0_LO                           0x000000d2
+#define REG_A3XX_RBBM_PERFCTR_SP_0_HI                           0x000000d3
+#define REG_A3XX_RBBM_PERFCTR_SP_1_LO                           0x000000d4
+#define REG_A3XX_RBBM_PERFCTR_SP_1_HI                           0x000000d5
+#define REG_A3XX_RBBM_PERFCTR_SP_2_LO                           0x000000d6
+#define REG_A3XX_RBBM_PERFCTR_SP_2_HI                           0x000000d7
+#define REG_A3XX_RBBM_PERFCTR_SP_3_LO                           0x000000d8
+#define REG_A3XX_RBBM_PERFCTR_SP_3_HI                           0x000000d9
+#define REG_A3XX_RBBM_PERFCTR_SP_4_LO                           0x000000da
+#define REG_A3XX_RBBM_PERFCTR_SP_4_HI                           0x000000db
+#define REG_A3XX_RBBM_PERFCTR_SP_5_LO                           0x000000dc
+#define REG_A3XX_RBBM_PERFCTR_SP_5_HI                           0x000000dd
+#define REG_A3XX_RBBM_PERFCTR_SP_6_LO                           0x000000de
+#define REG_A3XX_RBBM_PERFCTR_SP_6_HI                           0x000000df
+#define REG_A3XX_RBBM_PERFCTR_SP_7_LO                           0x000000e0
+#define REG_A3XX_RBBM_PERFCTR_SP_7_HI                           0x000000e1
+#define REG_A3XX_RBBM_PERFCTR_RB_0_LO                           0x000000e2
+#define REG_A3XX_RBBM_PERFCTR_RB_0_HI                           0x000000e3
+#define REG_A3XX_RBBM_PERFCTR_RB_1_LO                           0x000000e4
+#define REG_A3XX_RBBM_PERFCTR_RB_1_HI                           0x000000e5
+#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO                          0x000000ea
+#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI                          0x000000eb
+#define REG_A3XX_RBBM_PERFCTR_PWR_1_LO                          0x000000ec
+#define REG_A3XX_RBBM_PERFCTR_PWR_1_HI                          0x000000ed
+#define REG_A3XX_RBBM_RBBM_CTL                                  0x00000100
+#define REG_A3XX_RBBM_DEBUG_BUS_CTL                             0x00000111
+#define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS                     0x00000112
+#define REG_A3XX_CP_PFP_UCODE_ADDR                              0x000001c9
+#define REG_A3XX_CP_PFP_UCODE_DATA                              0x000001ca
+#define REG_A3XX_CP_ROQ_ADDR                                    0x000001cc
+#define REG_A3XX_CP_ROQ_DATA                                    0x000001cd
+#define REG_A3XX_CP_MERCIU_ADDR                                 0x000001d1
+#define REG_A3XX_CP_MERCIU_DATA                                 0x000001d2
+#define REG_A3XX_CP_MERCIU_DATA2                                0x000001d3
+#define REG_A3XX_CP_MEQ_ADDR                                    0x000001da
+#define REG_A3XX_CP_MEQ_DATA                                    0x000001db
+#define REG_A3XX_CP_WFI_PEND_CTR                                0x000001f5
+#define REG_A3XX_RBBM_PM_OVERRIDE2                              0x0000039d
+#define REG_A3XX_CP_PERFCOUNTER_SELECT                          0x00000445
+#define REG_A3XX_CP_HW_FAULT                                    0x0000045c
+#define REG_A3XX_CP_PROTECT_CTRL                                0x0000045e
+#define REG_A3XX_CP_PROTECT_STATUS                              0x0000045f
+static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
+static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
+#define REG_A3XX_CP_AHB_FAULT                                   0x0000054d
+#define REG_A3XX_SQ_GPR_MANAGEMENT                              0x00000d00
+#define REG_A3XX_SQ_INST_STORE_MANAGMENT                        0x00000d02
+#define REG_A3XX_TP0_CHICKEN                                    0x00000e1e
+#define REG_A3XX_SP_GLOBAL_MEM_SIZE                             0x00000e22
+#define REG_A3XX_SP_GLOBAL_MEM_ADDR                             0x00000e23
+#define REG_A3XX_GRAS_CL_CLIP_CNTL                              0x00002040
+#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER                  0x00001000
+#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE                     0x00010000
+#define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE                0x00020000
+#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE              0x00080000
+#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE                 0x00100000
+#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE           0x00200000
+#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD                           0x00800000
+#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD                           0x01000000
+#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE                    0x02000000
+#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ                            0x00002044
+#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK                     0x000003ff
+#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT                    0
+static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
+}
+#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK                     0x000ffc00
+#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT                    10
+static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
+}
+#define REG_A3XX_GRAS_CL_VPORT_XOFFSET                          0x00002048
+#define A3XX_GRAS_CL_VPORT_XOFFSET__MASK                        0xffffffff
+#define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT                       0
+static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK;
+}
+#define REG_A3XX_GRAS_CL_VPORT_XSCALE                           0x00002049
+#define A3XX_GRAS_CL_VPORT_XSCALE__MASK                         0xffffffff
+#define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT                        0
+static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK;
+}
+#define REG_A3XX_GRAS_CL_VPORT_YOFFSET                          0x0000204a
+#define A3XX_GRAS_CL_VPORT_YOFFSET__MASK                        0xffffffff
+#define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT                       0
+static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK;
+}
+#define REG_A3XX_GRAS_CL_VPORT_YSCALE                           0x0000204b
+#define A3XX_GRAS_CL_VPORT_YSCALE__MASK                         0xffffffff
+#define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT                        0
+static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK;
+}
+#define REG_A3XX_GRAS_CL_VPORT_ZOFFSET                          0x0000204c
+#define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK                        0xffffffff
+#define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT                       0
+static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK;
+}
+#define REG_A3XX_GRAS_CL_VPORT_ZSCALE                           0x0000204d
+#define A3XX_GRAS_CL_VPORT_ZSCALE__MASK                         0xffffffff
+#define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT                        0
+static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK;
+}
+#define REG_A3XX_GRAS_SU_POINT_MINMAX                           0x00002068
+#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK                     0x0000ffff
+#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT                    0
+static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
+{
+        return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
+}
+#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK                     0xffff0000
+#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT                    16
+static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
+{
+        return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
+}
+#define REG_A3XX_GRAS_SU_POINT_SIZE                             0x00002069
+#define A3XX_GRAS_SU_POINT_SIZE__MASK                           0xffffffff
+#define A3XX_GRAS_SU_POINT_SIZE__SHIFT                          0
+static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
+{
+        return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
+}
+#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE                      0x0000206c
+#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK                0x00ffffff
+#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT               0
+static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
+{
+        return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;
+}
+#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET                     0x0000206d
+#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK                   0xffffffff
+#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                  0
+static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
+{
+        return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
+}
+#define REG_A3XX_GRAS_SU_MODE_CONTROL                           0x00002070
+#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT                    0x00000001
+#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK                     0x00000002
+#define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW                      0x00000004
+#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK           0x000007f8
+#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT          3
+static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
+{
+        return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
+}
+#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET                   0x00000800
+#define REG_A3XX_GRAS_SC_CONTROL                                0x00002072
+#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK                  0x000000f0
+#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT                 4
+static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
+{
+        return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
+}
+#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK                 0x00000f00
+#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT                8
+static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val)
+{
+        return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
+}
+#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK                  0x0000f000
+#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT                 12
+static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
+}
+#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL                      0x00002074
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK                  0x00007fff
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT                 0
+static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
+}
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK                  0x7fff0000
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT                 16
+static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
+}
+#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR                      0x00002075
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK                  0x00007fff
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT                 0
+static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
+}
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK                  0x7fff0000
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT                 16
+static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
+}
+#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL                      0x00002079
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK                  0x00007fff
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT                 0
+static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
+}
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK                  0x7fff0000
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT                 16
+static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
+}
+#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR                      0x0000207a
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK                  0x00007fff
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT                 0
+static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
+}
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK                  0x7fff0000
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT                 16
+static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
+}
+#define REG_A3XX_RB_MODE_CONTROL                                0x000020c0
+#define A3XX_RB_MODE_CONTROL_GMEM_BYPASS                        0x00000080
+#define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK                  0x00000700
+#define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT                 8
+static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
+{
+        return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
+}
+#define A3XX_RB_MODE_CONTROL_MRT__MASK                          0x00003000
+#define A3XX_RB_MODE_CONTROL_MRT__SHIFT                         12
+static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
+{
+        return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
+}
+#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE              0x00008000
+#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE                0x00010000
+#define REG_A3XX_RB_RENDER_CONTROL                              0x000020c1
+#define A3XX_RB_RENDER_CONTROL_FACENESS                         0x00000008
+#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK                  0x00000ff0
+#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT                 4
+static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
+}
+#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE               0x00001000
+#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM                      0x00002000
+#define A3XX_RB_RENDER_CONTROL_XCOORD                           0x00004000
+#define A3XX_RB_RENDER_CONTROL_YCOORD                           0x00008000
+#define A3XX_RB_RENDER_CONTROL_ZCOORD                           0x00010000
+#define A3XX_RB_RENDER_CONTROL_WCOORD                           0x00020000
+#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST                       0x00400000
+#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK            0x07000000
+#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT           24
+static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK;
+}
+#define REG_A3XX_RB_MSAA_CONTROL                                0x000020c2
+#define A3XX_RB_MSAA_CONTROL_DISABLE                            0x00000400
+#define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK                      0x0000f000
+#define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT                     12
+static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val)
+{
+        return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK;
+}
+#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK                  0xffff0000
+#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT                 16
+static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
+}
+#define REG_A3XX_RB_ALPHA_REF                                   0x000020c3
+#define A3XX_RB_ALPHA_REF_UINT__MASK                            0x0000ff00
+#define A3XX_RB_ALPHA_REF_UINT__SHIFT                           8
+static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK;
+}
+#define A3XX_RB_ALPHA_REF_FLOAT__MASK                           0xffff0000
+#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT                          16
+static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
+}
+static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
+static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
+#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE                    0x00000008
+#define A3XX_RB_MRT_CONTROL_BLEND                               0x00000010
+#define A3XX_RB_MRT_CONTROL_BLEND2                              0x00000020
+#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK                      0x00000f00
+#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT                     8
+static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
+{
+        return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK;
+}
+#define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK                   0x00003000
+#define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT                  12
+static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
+{
+        return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK;
+}
+#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK              0x0f000000
+#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT             24
+static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
+{
+        return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
+}
+static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
+#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK                 0x0000003f
+#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT                0
+static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
+{
+        return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
+}
+#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK              0x000000c0
+#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT             6
+static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val)
+{
+        return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
+}
+#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK                   0x00000c00
+#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT                  10
+static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
+{
+        return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
+}
+#define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB                         0x00004000
+#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK              0xfffe0000
+#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT             17
+static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
+}
+static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
+#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK               0xfffffff0
+#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT              4
+static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
+}
+static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK          0x0000001f
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT         0
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK        0x000000e0
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT       5
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK         0x00001f00
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT        8
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK        0x001f0000
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT       16
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK      0x00e00000
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT     21
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK       0x1f000000
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT      24
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE                  0x20000000
+#define REG_A3XX_RB_BLEND_RED                                   0x000020e4
+#define A3XX_RB_BLEND_RED_UINT__MASK                            0x000000ff
+#define A3XX_RB_BLEND_RED_UINT__SHIFT                           0
+static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
+}
+#define A3XX_RB_BLEND_RED_FLOAT__MASK                           0xffff0000
+#define A3XX_RB_BLEND_RED_FLOAT__SHIFT                          16
+static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
+}
+#define REG_A3XX_RB_BLEND_GREEN                                 0x000020e5
+#define A3XX_RB_BLEND_GREEN_UINT__MASK                          0x000000ff
+#define A3XX_RB_BLEND_GREEN_UINT__SHIFT                         0
+static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
+}
+#define A3XX_RB_BLEND_GREEN_FLOAT__MASK                         0xffff0000
+#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT                        16
+static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
+}
+#define REG_A3XX_RB_BLEND_BLUE                                  0x000020e6
+#define A3XX_RB_BLEND_BLUE_UINT__MASK                           0x000000ff
+#define A3XX_RB_BLEND_BLUE_UINT__SHIFT                          0
+static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
+}
+#define A3XX_RB_BLEND_BLUE_FLOAT__MASK                          0xffff0000
+#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT                         16
+static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
+}
+#define REG_A3XX_RB_BLEND_ALPHA                                 0x000020e7
+#define A3XX_RB_BLEND_ALPHA_UINT__MASK                          0x000000ff
+#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT                         0
+static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
+}
+#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK                         0xffff0000
+#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT                        16
+static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
+}
+#define REG_A3XX_RB_CLEAR_COLOR_DW0                             0x000020e8
+#define REG_A3XX_RB_CLEAR_COLOR_DW1                             0x000020e9
+#define REG_A3XX_RB_CLEAR_COLOR_DW2                             0x000020ea
+#define REG_A3XX_RB_CLEAR_COLOR_DW3                             0x000020eb
+#define REG_A3XX_RB_COPY_CONTROL                                0x000020ec
+#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK                 0x00000003
+#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT                0
+static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
+{
+        return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
+}
+#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR                         0x00000008
+#define A3XX_RB_COPY_CONTROL_MODE__MASK                         0x00000070
+#define A3XX_RB_COPY_CONTROL_MODE__SHIFT                        4
+static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
+{
+        return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
+}
+#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK                    0x00000f00
+#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT                   8
+static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
+{
+        return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
+}
+#define A3XX_RB_COPY_CONTROL_UNK12                              0x00001000
+#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK                    0xffffc000
+#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT                   14
+static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
+{
+        return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
+}
+#define REG_A3XX_RB_COPY_DEST_BASE                              0x000020ed
+#define A3XX_RB_COPY_DEST_BASE_BASE__MASK                       0xfffffff0
+#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT                      4
+static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
+}
+#define REG_A3XX_RB_COPY_DEST_PITCH                             0x000020ee
+#define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK                     0xffffffff
+#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT                    0
+static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
+}
+#define REG_A3XX_RB_COPY_DEST_INFO                              0x000020ef
+#define A3XX_RB_COPY_DEST_INFO_TILE__MASK                       0x00000003
+#define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT                      0
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK                     0x000000fc
+#define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                    2
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_SWAP__MASK                       0x00000300
+#define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT                      8
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK                0x00000c00
+#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT               10
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK           0x0003c000
+#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT          14
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK                     0x001c0000
+#define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT                    18
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
+}
+#define REG_A3XX_RB_DEPTH_CONTROL                               0x00002100
+#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z                     0x00000001
+#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE                          0x00000002
+#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE                    0x00000004
+#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE                   0x00000008
+#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK                       0x00000070
+#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT                      4
+static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
+}
+#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE                         0x00000080
+#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE                     0x80000000
+#define REG_A3XX_RB_DEPTH_CLEAR                                 0x00002101
+#define REG_A3XX_RB_DEPTH_INFO                                  0x00002102
+#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000003
+#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                  0
+static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
+{
+        return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
+}
+#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                     0xfffff800
+#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                    11
+static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
+{
+        return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+}
+#define REG_A3XX_RB_DEPTH_PITCH                                 0x00002103
+#define A3XX_RB_DEPTH_PITCH__MASK                               0xffffffff
+#define A3XX_RB_DEPTH_PITCH__SHIFT                              0
+static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
+{
+        return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
+}
+#define REG_A3XX_RB_STENCIL_CONTROL                             0x00002104
+#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE                  0x00000001
+#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF               0x00000002
+#define A3XX_RB_STENCIL_CONTROL_STENCIL_READ                    0x00000004
+#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK                      0x00000700
+#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT                     8
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_FAIL__MASK                      0x00003800
+#define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT                     11
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK                     0x0001c000
+#define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT                    14
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK                     0x000e0000
+#define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT                    17
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK                   0x00700000
+#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT                  20
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK                   0x03800000
+#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT                  23
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK                  0x1c000000
+#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT                 26
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK                  0xe0000000
+#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT                 29
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
+}
+#define REG_A3XX_RB_STENCIL_CLEAR                               0x00002105
+#define REG_A3XX_RB_STENCIL_INFO                                0x00002106
+#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK                 0xfffff800
+#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT                11
+static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
+{
+        return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
+}
+#define REG_A3XX_RB_STENCIL_PITCH                               0x00002107
+#define A3XX_RB_STENCIL_PITCH__MASK                             0xffffffff
+#define A3XX_RB_STENCIL_PITCH__SHIFT                            0
+static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
+{
+        return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
+}
+#define REG_A3XX_RB_STENCILREFMASK                              0x00002108
+#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
+#define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
+static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK;
+}
+#define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
+#define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
+static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK;
+}
+#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
+#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
+static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
+}
+#define REG_A3XX_RB_STENCILREFMASK_BF                           0x00002109
+#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
+#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
+static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
+}
+#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
+#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
+static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
+}
+#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
+#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
+static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
+}
+#define REG_A3XX_RB_LRZ_VSC_CONTROL                             0x0000210c
+#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE                  0x00000002
+#define REG_A3XX_RB_WINDOW_OFFSET                               0x0000210e
+#define A3XX_RB_WINDOW_OFFSET_X__MASK                           0x0000ffff
+#define A3XX_RB_WINDOW_OFFSET_X__SHIFT                          0
+static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
+{
+        return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
+}
+#define A3XX_RB_WINDOW_OFFSET_Y__MASK                           0xffff0000
+#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT                          16
+static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
+{
+        return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
+}
+#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL                        0x00002110
+#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET                      0x00000001
+#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY                       0x00000002
+#define REG_A3XX_RB_SAMPLE_COUNT_ADDR                           0x00002111
+#define REG_A3XX_RB_Z_CLAMP_MIN                                 0x00002114
+#define REG_A3XX_RB_Z_CLAMP_MAX                                 0x00002115
+#define REG_A3XX_VGT_BIN_BASE                                   0x000021e1
+#define REG_A3XX_VGT_BIN_SIZE                                   0x000021e2
+#define REG_A3XX_PC_VSTREAM_CONTROL                             0x000021e4
+#define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK                      0x003f0000
+#define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT                     16
+static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
+{
+        return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK;
+}
+#define A3XX_PC_VSTREAM_CONTROL_N__MASK                         0x07c00000
+#define A3XX_PC_VSTREAM_CONTROL_N__SHIFT                        22
+static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val)
+{
+        return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK;
+}
+#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL                     0x000021ea
+#define REG_A3XX_PC_PRIM_VTX_CNTL                               0x000021ec
+#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK               0x0000001f
+#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT              0
+static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val)
+{
+        return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK;
+}
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK        0x000000e0
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT       5
+static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
+{
+        return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK;
+}
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK         0x00000700
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT        8
+static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
+{
+        return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
+}
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE                   0x00001000
+#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART                 0x00100000
+#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST                0x02000000
+#define A3XX_PC_PRIM_VTX_CNTL_PSIZE                             0x04000000
+#define REG_A3XX_PC_RESTART_INDEX                               0x000021ed
+#define REG_A3XX_HLSQ_CONTROL_0_REG                             0x00002200
+#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK              0x00000010
+#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT             4
+static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
+{
+        return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
+}
+#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE             0x00000040
+#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART                 0x00000200
+#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2                       0x00000400
+#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE                    0x04000000
+#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK                 0x08000000
+#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT                27
+static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
+}
+#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE               0x10000000
+#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE               0x20000000
+#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE                    0x40000000
+#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT                   0x80000000
+#define REG_A3XX_HLSQ_CONTROL_1_REG                             0x00002201
+#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK              0x00000040
+#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT             6
+static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
+{
+        return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
+}
+#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE             0x00000100
+#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1                       0x00000200
+#define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD                         0x02000000
+#define REG_A3XX_HLSQ_CONTROL_2_REG                             0x00002202
+#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK        0xfc000000
+#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT       26
+static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
+}
+#define REG_A3XX_HLSQ_CONTROL_3_REG                             0x00002203
+#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK                     0x000000ff
+#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT                    0
+static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
+}
+#define REG_A3XX_HLSQ_VS_CONTROL_REG                            0x00002204
+#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK              0x00000fff
+#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT             0
+static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
+}
+#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK         0x00fff000
+#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT        12
+static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
+}
+#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
+#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT             24
+static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
+}
+#define REG_A3XX_HLSQ_FS_CONTROL_REG                            0x00002205
+#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK              0x00000fff
+#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT             0
+static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
+}
+#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK         0x00fff000
+#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT        12
+static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
+}
+#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
+#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT             24
+static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
+}
+#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG                   0x00002206
+#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK      0x0000ffff
+#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT     0
+static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
+}
+#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK        0xffff0000
+#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT       16
+static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
+}
+#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG                   0x00002207
+#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK      0x0000ffff
+#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT     0
+static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
+}
+#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK        0xffff0000
+#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT       16
+static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
+}
+#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG                          0x0000220a
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK                0x00000003
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT               0
+static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
+}
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK             0x00000ffc
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT            2
+static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
+}
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK             0x003ff000
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT            12
+static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
+}
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK             0xffc00000
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT            22
+static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
+}
+static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
+static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
+static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
+#define REG_A3XX_HLSQ_CL_CONTROL_0_REG                          0x00002211
+#define REG_A3XX_HLSQ_CL_CONTROL_1_REG                          0x00002212
+#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG                       0x00002214
+static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
+static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
+#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG                     0x00002216
+#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG                     0x00002217
+#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG                          0x0000221a
+#define REG_A3XX_VFD_CONTROL_0                                  0x00002240
+#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK                  0x0003ffff
+#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT                 0
+static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
+}
+#define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK                     0x003c0000
+#define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT                    18
+static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK;
+}
+#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK                0x07c00000
+#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT               22
+static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
+}
+#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK              0xf8000000
+#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT             27
+static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
+}
+#define REG_A3XX_VFD_CONTROL_1                                  0x00002241
+#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK                     0x0000ffff
+#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT                    0
+static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
+}
+#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK                      0x00ff0000
+#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT                     16
+static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
+}
+#define A3XX_VFD_CONTROL_1_REGID4INST__MASK                     0xff000000
+#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT                    24
+static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK;
+}
+#define REG_A3XX_VFD_INDEX_MIN                                  0x00002242
+#define REG_A3XX_VFD_INDEX_MAX                                  0x00002243
+#define REG_A3XX_VFD_INSTANCEID_OFFSET                          0x00002244
+#define REG_A3XX_VFD_INDEX_OFFSET                               0x00002245
+#define REG_A3XX_VFD_INDEX_OFFSET                               0x00002245
+static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
+static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
+#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK                  0x0000007f
+#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT                 0
+static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
+}
+#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK                  0x0000ff80
+#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT                 7
+static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
+}
+#define A3XX_VFD_FETCH_INSTR_0_INSTANCED                        0x00010000
+#define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT                       0x00020000
+#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK                  0x00fc0000
+#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT                 18
+static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK;
+}
+#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK                   0xff000000
+#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT                  24
+static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
+}
+static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
+static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
+static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
+#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK                   0x0000000f
+#define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT                  0
+static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_CONSTFILL                         0x00000010
+#define A3XX_VFD_DECODE_INSTR_FORMAT__MASK                      0x00000fc0
+#define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT                     6
+static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_REGID__MASK                       0x000ff000
+#define A3XX_VFD_DECODE_INSTR_REGID__SHIFT                      12
+static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_INT                               0x00100000
+#define A3XX_VFD_DECODE_INSTR_SWAP__MASK                        0x00c00000
+#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT                       22
+static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK                    0x1f000000
+#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT                   24
+static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID                     0x20000000
+#define A3XX_VFD_DECODE_INSTR_SWITCHNEXT                        0x40000000
+#define REG_A3XX_VFD_VS_THREADING_THRESHOLD                     0x0000227e
+#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK   0x0000000f
+#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT  0
+static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val)
+{
+        return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK;
+}
+#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK      0x0000ff00
+#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT     8
+static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val)
+{
+        return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK;
+}
+#define REG_A3XX_VPC_ATTR                                       0x00002280
+#define A3XX_VPC_ATTR_TOTALATTR__MASK                           0x000001ff
+#define A3XX_VPC_ATTR_TOTALATTR__SHIFT                          0
+static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
+{
+        return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK;
+}
+#define A3XX_VPC_ATTR_PSIZE                                     0x00000200
+#define A3XX_VPC_ATTR_THRDASSIGN__MASK                          0x0ffff000
+#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT                         12
+static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
+{
+        return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK;
+}
+#define A3XX_VPC_ATTR_LMSIZE__MASK                              0xf0000000
+#define A3XX_VPC_ATTR_LMSIZE__SHIFT                             28
+static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val)
+{
+        return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK;
+}
+#define REG_A3XX_VPC_PACK                                       0x00002281
+#define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK                      0x0000ff00
+#define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT                     8
+static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
+{
+        return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
+}
+#define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK                      0x00ff0000
+#define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT                     16
+static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
+{
+        return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
+}
+static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
+static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
+#define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK                   0x00000003
+#define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT                  0
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK                   0x0000000c
+#define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT                  2
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK                   0x00000030
+#define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT                  4
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK                   0x000000c0
+#define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT                  6
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK                   0x00000300
+#define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT                  8
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK                   0x00000c00
+#define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT                  10
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK                   0x00003000
+#define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT                  12
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK                   0x0000c000
+#define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT                  14
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK                   0x00030000
+#define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT                  16
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK                   0x000c0000
+#define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT                  18
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK                   0x00300000
+#define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT                  20
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK                   0x00c00000
+#define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT                  22
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK                   0x03000000
+#define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT                  24
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK                   0x0c000000
+#define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT                  26
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK                   0x30000000
+#define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT                  28
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK;
+}
+#define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK                   0xc0000000
+#define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT                  30
+static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK;
+}
+static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
+static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK                  0x00000003
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT                 0
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK                  0x0000000c
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT                 2
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK                  0x00000030
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT                 4
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK                  0x000000c0
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT                 6
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK                  0x00000300
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT                 8
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK                  0x00000c00
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT                 10
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK                  0x00003000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT                 12
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK                  0x0000c000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT                 14
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK                  0x00030000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT                 16
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK                  0x000c0000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT                 18
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK                  0x00300000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT                 20
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK                  0x00c00000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT                 22
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK                  0x03000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT                 24
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK                  0x0c000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT                 26
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK                  0x30000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT                 28
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK                  0xc0000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT                 30
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
+{
+        return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
+}
+#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0                      0x0000228a
+#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1                      0x0000228b
+#define REG_A3XX_SP_SP_CTRL_REG                                 0x000022c0
+#define A3XX_SP_SP_CTRL_REG_RESOLVE                             0x00010000
+#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK                     0x00040000
+#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT                    18
+static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
+{
+        return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
+}
+#define A3XX_SP_SP_CTRL_REG_BINNING                             0x00080000
+#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK                     0x00300000
+#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT                    20
+static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
+{
+        return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
+}
+#define A3XX_SP_SP_CTRL_REG_L0MODE__MASK                        0x00c00000
+#define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT                       22
+static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
+{
+        return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK;
+}
+#define REG_A3XX_SP_VS_CTRL_REG0                                0x000022c4
+#define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK                   0x00000001
+#define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT                  0
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK              0x00000002
+#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT             1
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID                       0x00000004
+#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
+#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0003fc00
+#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK              0x000c0000
+#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT             18
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
+#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT                  20
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
+#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE                       0x00400000
+#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE                        0x00800000
+#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK                       0xff000000
+#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT                      24
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
+}
+#define REG_A3XX_SP_VS_CTRL_REG1                                0x000022c5
+#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK                  0x000003ff
+#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
+static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK               0x000ffc00
+#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT              10
+static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK           0x7f000000
+#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT          24
+static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
+}
+#define REG_A3XX_SP_VS_PARAM_REG                                0x000022c6
+#define A3XX_SP_VS_PARAM_REG_POSREGID__MASK                     0x000000ff
+#define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT                    0
+static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
+}
+#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK                   0x0000ff00
+#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT                  8
+static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
+}
+#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK                0xfff00000
+#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT               20
+static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
+}
+static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
+static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
+#define A3XX_SP_VS_OUT_REG_A_REGID__MASK                        0x000001ff
+#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT                       0
+static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
+}
+#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK                     0x00001e00
+#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT                    9
+static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
+}
+#define A3XX_SP_VS_OUT_REG_B_REGID__MASK                        0x01ff0000
+#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT                       16
+static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
+}
+#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK                     0x1e000000
+#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT                    25
+static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
+}
+static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
+static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT                   0
+static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
+}
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT                   8
+static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
+}
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT                   16
+static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
+}
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT                   24
+static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
+}
+#define REG_A3XX_SP_VS_OBJ_OFFSET_REG                           0x000022d4
+#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
+#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
+static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
+}
+#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
+#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
+static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
+}
+#define REG_A3XX_SP_VS_OBJ_START_REG                            0x000022d5
+#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG                        0x000022d6
+#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG                         0x000022d7
+#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG                         0x000022d8
+#define REG_A3XX_SP_VS_LENGTH_REG                               0x000022df
+#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK                0xffffffff
+#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT               0
+static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK;
+}
+#define REG_A3XX_SP_FS_CTRL_REG0                                0x000022e0
+#define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK                   0x00000001
+#define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT                  0
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK              0x00000002
+#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT             1
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID                       0x00000004
+#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
+#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0003fc00
+#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK              0x000c0000
+#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT             18
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
+#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT                  20
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
+#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE                       0x00400000
+#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE                        0x00800000
+#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK                       0xff000000
+#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT                      24
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK;
+}
+#define REG_A3XX_SP_FS_CTRL_REG1                                0x000022e1
+#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK                  0x000003ff
+#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
+static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK               0x000ffc00
+#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT              10
+static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK           0x00f00000
+#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT          20
+static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK            0x3f000000
+#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT           24
+static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
+}
+#define REG_A3XX_SP_FS_OBJ_OFFSET_REG                           0x000022e2
+#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
+#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
+static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
+}
+#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
+#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
+static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
+}
+#define REG_A3XX_SP_FS_OBJ_START_REG                            0x000022e3
+#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG                        0x000022e4
+#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG                         0x000022e5
+#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG                         0x000022e6
+#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0                     0x000022e8
+#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1                     0x000022e9
+#define REG_A3XX_SP_FS_OUTPUT_REG                               0x000022ec
+#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK                         0x00000003
+#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT                        0
+static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
+}
+#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE                      0x00000080
+#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK                 0x0000ff00
+#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT                8
+static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
+}
+static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
+static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
+#define A3XX_SP_FS_MRT_REG_REGID__MASK                          0x000000ff
+#define A3XX_SP_FS_MRT_REG_REGID__SHIFT                         0
+static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK;
+}
+#define A3XX_SP_FS_MRT_REG_HALF_PRECISION                       0x00000100
+#define A3XX_SP_FS_MRT_REG_SINT                                 0x00000400
+#define A3XX_SP_FS_MRT_REG_UINT                                 0x00000800
+static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
+static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
+#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK             0x0000003f
+#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT            0
+static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
+{
+        return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK;
+}
+#define REG_A3XX_SP_FS_LENGTH_REG                               0x000022ff
+#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK                0xffffffff
+#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT               0
+static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK;
+}
+#define REG_A3XX_PA_SC_AA_CONFIG                                0x00002301
+#define REG_A3XX_TPL1_TP_VS_TEX_OFFSET                          0x00002340
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK          0x000000ff
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT         0
+static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK;
+}
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK           0x0000ff00
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT          8
+static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK;
+}
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK           0xffff0000
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT          16
+static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK;
+}
+#define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR              0x00002341
+#define REG_A3XX_TPL1_TP_FS_TEX_OFFSET                          0x00002342
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK          0x000000ff
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT         0
+static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK;
+}
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK           0x0000ff00
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT          8
+static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK;
+}
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK           0xffff0000
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT          16
+static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK;
+}
+#define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR              0x00002343
+#define REG_A3XX_VBIF_CLKON                                     0x00003001
+#define REG_A3XX_VBIF_FIXED_SORT_EN                             0x0000300c
+#define REG_A3XX_VBIF_FIXED_SORT_SEL0                           0x0000300d
+#define REG_A3XX_VBIF_FIXED_SORT_SEL1                           0x0000300e
+#define REG_A3XX_VBIF_ABIT_SORT                                 0x0000301c
+#define REG_A3XX_VBIF_ABIT_SORT_CONF                            0x0000301d
+#define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN                         0x0000302a
+#define REG_A3XX_VBIF_IN_RD_LIM_CONF0                           0x0000302c
+#define REG_A3XX_VBIF_IN_RD_LIM_CONF1                           0x0000302d
+#define REG_A3XX_VBIF_IN_WR_LIM_CONF0                           0x00003030
+#define REG_A3XX_VBIF_IN_WR_LIM_CONF1                           0x00003031
+#define REG_A3XX_VBIF_OUT_RD_LIM_CONF0                          0x00003034
+#define REG_A3XX_VBIF_OUT_WR_LIM_CONF0                          0x00003035
+#define REG_A3XX_VBIF_DDR_OUT_MAX_BURST                         0x00003036
+#define REG_A3XX_VBIF_ARB_CTL                                   0x0000303c
+#define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB                       0x00003049
+#define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0                    0x00003058
+#define REG_A3XX_VBIF_OUT_AXI_AOOO_EN                           0x0000305e
+#define REG_A3XX_VBIF_OUT_AXI_AOOO                              0x0000305f
+#define REG_A3XX_VBIF_PERF_CNT_EN                               0x00003070
+#define A3XX_VBIF_PERF_CNT_EN_CNT0                              0x00000001
+#define A3XX_VBIF_PERF_CNT_EN_CNT1                              0x00000002
+#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0                           0x00000004
+#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1                           0x00000008
+#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2                           0x00000010
+#define REG_A3XX_VBIF_PERF_CNT_CLR                              0x00003071
+#define A3XX_VBIF_PERF_CNT_CLR_CNT0                             0x00000001
+#define A3XX_VBIF_PERF_CNT_CLR_CNT1                             0x00000002
+#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0                          0x00000004
+#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1                          0x00000008
+#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2                          0x00000010
+#define REG_A3XX_VBIF_PERF_CNT_SEL                              0x00003072
+#define REG_A3XX_VBIF_PERF_CNT0_LO                              0x00003073
+#define REG_A3XX_VBIF_PERF_CNT0_HI                              0x00003074
+#define REG_A3XX_VBIF_PERF_CNT1_LO                              0x00003075
+#define REG_A3XX_VBIF_PERF_CNT1_HI                              0x00003076
+#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO                          0x00003077
+#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI                          0x00003078
+#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO                          0x00003079
+#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI                          0x0000307a
+#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO                          0x0000307b
+#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI                          0x0000307c
+#define REG_A3XX_VSC_BIN_SIZE                                   0x00000c01
+#define A3XX_VSC_BIN_SIZE_WIDTH__MASK                           0x0000001f
+#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT                          0
+static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
+{
+        return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
+}
+#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK                          0x000003e0
+#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT                         5
+static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
+}
+#define REG_A3XX_VSC_SIZE_ADDRESS                               0x00000c02
+static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
+static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
+#define A3XX_VSC_PIPE_CONFIG_X__MASK                            0x000003ff
+#define A3XX_VSC_PIPE_CONFIG_X__SHIFT                           0
+static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
+{
+        return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK;
+}
+#define A3XX_VSC_PIPE_CONFIG_Y__MASK                            0x000ffc00
+#define A3XX_VSC_PIPE_CONFIG_Y__SHIFT                           10
+static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val)
+{
+        return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK;
+}
+#define A3XX_VSC_PIPE_CONFIG_W__MASK                            0x00f00000
+#define A3XX_VSC_PIPE_CONFIG_W__SHIFT                           20
+static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val)
+{
+        return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK;
+}
+#define A3XX_VSC_PIPE_CONFIG_H__MASK                            0x0f000000
+#define A3XX_VSC_PIPE_CONFIG_H__SHIFT                           24
+static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
+{
+        return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
+}
+static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
+static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
+#define REG_A3XX_VSC_BIN_CONTROL                                0x00000c3c
+#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE                     0x00000001
+#define REG_A3XX_UNKNOWN_0C3D                                   0x00000c3d
+#define REG_A3XX_PC_PERFCOUNTER0_SELECT                         0x00000c48
+#define REG_A3XX_PC_PERFCOUNTER1_SELECT                         0x00000c49
+#define REG_A3XX_PC_PERFCOUNTER2_SELECT                         0x00000c4a
+#define REG_A3XX_PC_PERFCOUNTER3_SELECT                         0x00000c4b
+#define REG_A3XX_GRAS_TSE_DEBUG_ECO                             0x00000c81
+#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT                       0x00000c88
+#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT                       0x00000c89
+#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT                       0x00000c8a
+#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT                       0x00000c8b
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
+#define REG_A3XX_RB_GMEM_BASE_ADDR                              0x00000cc0
+#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR                     0x00000cc1
+#define REG_A3XX_RB_PERFCOUNTER0_SELECT                         0x00000cc6
+#define REG_A3XX_RB_PERFCOUNTER1_SELECT                         0x00000cc7
+#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION                      0x00000ce0
+#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK              0x00003fff
+#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT             0
+static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
+{
+        return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
+}
+#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK             0x0fffc000
+#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT            14
+static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
+{
+        return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
+}
+#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT                       0x00000e00
+#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT                       0x00000e01
+#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT                       0x00000e02
+#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT                       0x00000e03
+#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT                       0x00000e04
+#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT                       0x00000e05
+#define REG_A3XX_UNKNOWN_0E43                                   0x00000e43
+#define REG_A3XX_VFD_PERFCOUNTER0_SELECT                        0x00000e44
+#define REG_A3XX_VFD_PERFCOUNTER1_SELECT                        0x00000e45
+#define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL                          0x00000e61
+#define REG_A3XX_VPC_VPC_DEBUG_RAM_READ                         0x00000e62
+#define REG_A3XX_VPC_PERFCOUNTER0_SELECT                        0x00000e64
+#define REG_A3XX_VPC_PERFCOUNTER1_SELECT                        0x00000e65
+#define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG                    0x00000e82
+#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT                       0x00000e84
+#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT                       0x00000e85
+#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT                       0x00000e86
+#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT                       0x00000e87
+#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT                       0x00000e88
+#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT                       0x00000e89
+#define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG                     0x00000ea0
+#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK              0x0fffffff
+#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT             0
+static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val)
+{
+        return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK;
+}
+#define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG                     0x00000ea1
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK              0x0fffffff
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT             0
+static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val)
+{
+        return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK;
+}
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK            0x30000000
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT           28
+static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val)
+{
+        return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK;
+}
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE            0x80000000
+#define REG_A3XX_UNKNOWN_0EA6                                   0x00000ea6
+#define REG_A3XX_SP_PERFCOUNTER0_SELECT                         0x00000ec4
+#define REG_A3XX_SP_PERFCOUNTER1_SELECT                         0x00000ec5
+#define REG_A3XX_SP_PERFCOUNTER2_SELECT                         0x00000ec6
+#define REG_A3XX_SP_PERFCOUNTER3_SELECT                         0x00000ec7
+#define REG_A3XX_SP_PERFCOUNTER4_SELECT                         0x00000ec8
+#define REG_A3XX_SP_PERFCOUNTER5_SELECT                         0x00000ec9
+#define REG_A3XX_SP_PERFCOUNTER6_SELECT                         0x00000eca
+#define REG_A3XX_SP_PERFCOUNTER7_SELECT                         0x00000ecb
+#define REG_A3XX_UNKNOWN_0EE0                                   0x00000ee0
+#define REG_A3XX_UNKNOWN_0F03                                   0x00000f03
+#define REG_A3XX_TP_PERFCOUNTER0_SELECT                         0x00000f04
+#define REG_A3XX_TP_PERFCOUNTER1_SELECT                         0x00000f05
+#define REG_A3XX_TP_PERFCOUNTER2_SELECT                         0x00000f06
+#define REG_A3XX_TP_PERFCOUNTER3_SELECT                         0x00000f07
+#define REG_A3XX_TP_PERFCOUNTER4_SELECT                         0x00000f08
+#define REG_A3XX_TP_PERFCOUNTER5_SELECT                         0x00000f09
+#define REG_A3XX_VGT_CL_INITIATOR                               0x000021f0
+#define REG_A3XX_VGT_EVENT_INITIATOR                            0x000021f9
+#define REG_A3XX_VGT_DRAW_INITIATOR                             0x000021fc
+#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK                 0x0000003f
+#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT                0
+static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
+{
+        return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
+}
+#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK             0x000000c0
+#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT            6
+static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
+{
+        return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
+}
+#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK                  0x00000600
+#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT                 9
+static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
+{
+        return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
+}
+#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK                0x00000800
+#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT               11
+static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
+{
+        return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
+}
+#define A3XX_VGT_DRAW_INITIATOR_NOT_EOP                         0x00001000
+#define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX                     0x00002000
+#define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE       0x00004000
+#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK             0xff000000
+#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT            24
+static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
+{
+        return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
+}
+#define REG_A3XX_VGT_IMMED_DATA                                 0x000021fd
+#define REG_A3XX_TEX_SAMP_0                                     0x00000000
+#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR                        0x00000002
+#define A3XX_TEX_SAMP_0_XY_MAG__MASK                            0x0000000c
+#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT                           2
+static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK;
+}
+#define A3XX_TEX_SAMP_0_XY_MIN__MASK                            0x00000030
+#define A3XX_TEX_SAMP_0_XY_MIN__SHIFT                           4
+static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK;
+}
+#define A3XX_TEX_SAMP_0_WRAP_S__MASK                            0x000001c0
+#define A3XX_TEX_SAMP_0_WRAP_S__SHIFT                           6
+static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK;
+}
+#define A3XX_TEX_SAMP_0_WRAP_T__MASK                            0x00000e00
+#define A3XX_TEX_SAMP_0_WRAP_T__SHIFT                           9
+static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK;
+}
+#define A3XX_TEX_SAMP_0_WRAP_R__MASK                            0x00007000
+#define A3XX_TEX_SAMP_0_WRAP_R__SHIFT                           12
+static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
+}
+#define A3XX_TEX_SAMP_0_ANISO__MASK                             0x00038000
+#define A3XX_TEX_SAMP_0_ANISO__SHIFT                            15
+static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK;
+}
+#define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK                      0x00700000
+#define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT                     20
+static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
+}
+#define A3XX_TEX_SAMP_0_UNNORM_COORDS                           0x80000000
+#define REG_A3XX_TEX_SAMP_1                                     0x00000001
+#define A3XX_TEX_SAMP_1_LOD_BIAS__MASK                          0x000007ff
+#define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT                         0
+static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val)
+{
+        return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK;
+}
+#define A3XX_TEX_SAMP_1_MAX_LOD__MASK                           0x003ff000
+#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT                          12
+static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
+{
+        return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
+}
+#define A3XX_TEX_SAMP_1_MIN_LOD__MASK                           0xffc00000
+#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT                          22
+static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
+{
+        return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
+}
+#define REG_A3XX_TEX_CONST_0                                    0x00000000
+#define A3XX_TEX_CONST_0_TILED                                  0x00000001
+#define A3XX_TEX_CONST_0_SRGB                                   0x00000004
+#define A3XX_TEX_CONST_0_SWIZ_X__MASK                           0x00000070
+#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT                          4
+static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
+{
+        return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK;
+}
+#define A3XX_TEX_CONST_0_SWIZ_Y__MASK                           0x00000380
+#define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT                          7
+static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val)
+{
+        return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK;
+}
+#define A3XX_TEX_CONST_0_SWIZ_Z__MASK                           0x00001c00
+#define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT                          10
+static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val)
+{
+        return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK;
+}
+#define A3XX_TEX_CONST_0_SWIZ_W__MASK                           0x0000e000
+#define A3XX_TEX_CONST_0_SWIZ_W__SHIFT                          13
+static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
+{
+        return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
+}
+#define A3XX_TEX_CONST_0_MIPLVLS__MASK                          0x000f0000
+#define A3XX_TEX_CONST_0_MIPLVLS__SHIFT                         16
+static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
+}
+#define A3XX_TEX_CONST_0_FMT__MASK                              0x1fc00000
+#define A3XX_TEX_CONST_0_FMT__SHIFT                             22
+static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
+{
+        return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
+}
+#define A3XX_TEX_CONST_0_NOCONVERT                              0x20000000
+#define A3XX_TEX_CONST_0_TYPE__MASK                             0xc0000000
+#define A3XX_TEX_CONST_0_TYPE__SHIFT                            30
+static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
+{
+        return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
+}
+#define REG_A3XX_TEX_CONST_1                                    0x00000001
+#define A3XX_TEX_CONST_1_HEIGHT__MASK                           0x00003fff
+#define A3XX_TEX_CONST_1_HEIGHT__SHIFT                          0
+static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK;
+}
+#define A3XX_TEX_CONST_1_WIDTH__MASK                            0x0fffc000
+#define A3XX_TEX_CONST_1_WIDTH__SHIFT                           14
+static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
+}
+#define A3XX_TEX_CONST_1_FETCHSIZE__MASK                        0xf0000000
+#define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT                       28
+static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
+{
+        return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK;
+}
+#define REG_A3XX_TEX_CONST_2                                    0x00000002
+#define A3XX_TEX_CONST_2_INDX__MASK                             0x000000ff
+#define A3XX_TEX_CONST_2_INDX__SHIFT                            0
+static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK;
+}
+#define A3XX_TEX_CONST_2_PITCH__MASK                            0x3ffff000
+#define A3XX_TEX_CONST_2_PITCH__SHIFT                           12
+static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK;
+}
+#define A3XX_TEX_CONST_2_SWAP__MASK                             0xc0000000
+#define A3XX_TEX_CONST_2_SWAP__SHIFT                            30
+static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
+{
+        return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK;
+}
+#define REG_A3XX_TEX_CONST_3                                    0x00000003
+#define A3XX_TEX_CONST_3_LAYERSZ1__MASK                         0x00007fff
+#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT                        0
+static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
+{
+        return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;
+}
+#define A3XX_TEX_CONST_3_DEPTH__MASK                            0x0ffe0000
+#define A3XX_TEX_CONST_3_DEPTH__SHIFT                           17
+static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK;
+}
+#define A3XX_TEX_CONST_3_LAYERSZ2__MASK                         0xf0000000
+#define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT                        28
+static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)
+{
+        return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;
+}
+#endif /* A3XX_XML */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_blend.c
 ,0 → 1,135
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_state.h"
+#include "util/u_blend.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "fd3_blend.h"
+#include "fd3_context.h"
+#include "fd3_format.h"
+static enum a3xx_rb_blend_opcode
+blend_func(unsigned func)
+{
+        switch (func) {
+        case PIPE_BLEND_ADD:
+                return BLEND_DST_PLUS_SRC;
+        case PIPE_BLEND_MIN:
+                return BLEND_MIN_DST_SRC;
+        case PIPE_BLEND_MAX:
+                return BLEND_MAX_DST_SRC;
+        case PIPE_BLEND_SUBTRACT:
+                return BLEND_SRC_MINUS_DST;
+        case PIPE_BLEND_REVERSE_SUBTRACT:
+                return BLEND_DST_MINUS_SRC;
+        default:
+                DBG("invalid blend func: %x", func);
+                return 0;
+        }
+}
+void *
+fd3_blend_state_create(struct pipe_context *pctx,
+                const struct pipe_blend_state *cso)
+{
+        struct fd3_blend_stateobj *so;
+        enum a3xx_rop_code rop = ROP_COPY;
+        bool reads_dest = false;
+        int i;
+        if (cso->logicop_enable) {
+                rop = cso->logicop_func;  /* maps 1:1 */
+                switch (cso->logicop_func) {
+                case PIPE_LOGICOP_NOR:
+                case PIPE_LOGICOP_AND_INVERTED:
+                case PIPE_LOGICOP_AND_REVERSE:
+                case PIPE_LOGICOP_INVERT:
+                case PIPE_LOGICOP_XOR:
+                case PIPE_LOGICOP_NAND:
+                case PIPE_LOGICOP_AND:
+                case PIPE_LOGICOP_EQUIV:
+                case PIPE_LOGICOP_NOOP:
+                case PIPE_LOGICOP_OR_INVERTED:
+                case PIPE_LOGICOP_OR_REVERSE:
+                case PIPE_LOGICOP_OR:
+                        reads_dest = true;
+                        break;
+                }
+        }
+        so = CALLOC_STRUCT(fd3_blend_stateobj);
+        if (!so)
+                return NULL;
+        so->base = *cso;
+        for (i = 0; i < ARRAY_SIZE(so->rb_mrt); i++) {
+                const struct pipe_rt_blend_state *rt;
+                if (cso->independent_blend_enable)
+                        rt = &cso->rt[i];
+                else
+                        rt = &cso->rt[0];
+                so->rb_mrt[i].blend_control_rgb =
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(fd_blend_factor(rt->rgb_src_factor)) |
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(blend_func(rt->rgb_func)) |
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(fd_blend_factor(rt->rgb_dst_factor));
+                so->rb_mrt[i].blend_control_alpha =
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(fd_blend_factor(rt->alpha_src_factor)) |
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(blend_func(rt->alpha_func)) |
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(fd_blend_factor(rt->alpha_dst_factor));
+                so->rb_mrt[i].blend_control_no_alpha_rgb =
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(fd_blend_factor(util_blend_dst_alpha_to_one(rt->rgb_src_factor))) |
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(blend_func(rt->rgb_func)) |
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(fd_blend_factor(util_blend_dst_alpha_to_one(rt->rgb_dst_factor)));
+                so->rb_mrt[i].control =
+                                A3XX_RB_MRT_CONTROL_ROP_CODE(rop) |
+                                A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(rt->colormask);
+                if (rt->blend_enable)
+                        so->rb_mrt[i].control |=
+                                        A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE |
+                                        A3XX_RB_MRT_CONTROL_BLEND |
+                                        A3XX_RB_MRT_CONTROL_BLEND2;
+                if (reads_dest)
+                        so->rb_mrt[i].control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
+                if (cso->dither)
+                        so->rb_mrt[i].control |= A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS);
+        }
+        return so;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_blend.h
 ,0 → 1,57
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_BLEND_H_
+#define FD3_BLEND_H_
+#include "pipe/p_state.h"
+#include "pipe/p_context.h"
+struct fd3_blend_stateobj {
+        struct pipe_blend_state base;
+        struct {
+                /* Blend control bits for color if there is an alpha channel */
+                uint32_t blend_control_rgb;
+                /* Blend control bits for color if there is no alpha channel */
+                uint32_t blend_control_no_alpha_rgb;
+                /* Blend control bits for alpha channel */
+                uint32_t blend_control_alpha;
+                uint32_t control;
+        } rb_mrt[4];
+};
+static INLINE struct fd3_blend_stateobj *
+fd3_blend_stateobj(struct pipe_blend_state *blend)
+{
+        return (struct fd3_blend_stateobj *)blend;
+}
+void * fd3_blend_state_create(struct pipe_context *pctx,
+                const struct pipe_blend_state *cso);
+#endif /* FD3_BLEND_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_context.c
 ,0 → 1,177
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "fd3_context.h"
+#include "fd3_blend.h"
+#include "fd3_draw.h"
+#include "fd3_emit.h"
+#include "fd3_gmem.h"
+#include "fd3_program.h"
+#include "fd3_query.h"
+#include "fd3_rasterizer.h"
+#include "fd3_texture.h"
+#include "fd3_zsa.h"
+static void
+fd3_context_destroy(struct pipe_context *pctx)
+{
+        struct fd3_context *fd3_ctx = fd3_context(fd_context(pctx));
+        util_dynarray_fini(&fd3_ctx->rbrc_patches);
+        fd_bo_del(fd3_ctx->vs_pvt_mem);
+        fd_bo_del(fd3_ctx->fs_pvt_mem);
+        fd_bo_del(fd3_ctx->vsc_size_mem);
+        pctx->delete_vertex_elements_state(pctx, fd3_ctx->solid_vbuf_state.vtx);
+        pctx->delete_vertex_elements_state(pctx, fd3_ctx->blit_vbuf_state.vtx);
+        pipe_resource_reference(&fd3_ctx->solid_vbuf, NULL);
+        pipe_resource_reference(&fd3_ctx->blit_texcoord_vbuf, NULL);
+        u_upload_destroy(fd3_ctx->border_color_uploader);
+        fd_context_destroy(pctx);
+}
+/* TODO we could combine a few of these small buffers (solid_vbuf,
+ * blit_texcoord_vbuf, and vsc_size_mem, into a single buffer and
+ * save a tiny bit of memory
+ */
+static struct pipe_resource *
+create_solid_vertexbuf(struct pipe_context *pctx)
+{
+        static const float init_shader_const[] = {
+                        -1.000000, +1.000000, +1.000000,
+                        +1.000000, -1.000000, +1.000000,
+        };
+        struct pipe_resource *prsc = pipe_buffer_create(pctx->screen,
+                        PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, sizeof(init_shader_const));
+        pipe_buffer_write(pctx, prsc, 0,
+                        sizeof(init_shader_const), init_shader_const);
+        return prsc;
+}
+static struct pipe_resource *
+create_blit_texcoord_vertexbuf(struct pipe_context *pctx)
+{
+        struct pipe_resource *prsc = pipe_buffer_create(pctx->screen,
+                        PIPE_BIND_CUSTOM, PIPE_USAGE_DYNAMIC, 16);
+        return prsc;
+}
+static const uint8_t primtypes[PIPE_PRIM_MAX] = {
+                [PIPE_PRIM_POINTS]         = DI_PT_POINTLIST_A3XX,
+                [PIPE_PRIM_LINES]          = DI_PT_LINELIST,
+                [PIPE_PRIM_LINE_STRIP]     = DI_PT_LINESTRIP,
+                [PIPE_PRIM_LINE_LOOP]      = DI_PT_LINELOOP,
+                [PIPE_PRIM_TRIANGLES]      = DI_PT_TRILIST,
+                [PIPE_PRIM_TRIANGLE_STRIP] = DI_PT_TRISTRIP,
+                [PIPE_PRIM_TRIANGLE_FAN]   = DI_PT_TRIFAN,
+};
+struct pipe_context *
+fd3_context_create(struct pipe_screen *pscreen, void *priv)
+{
+        struct fd_screen *screen = fd_screen(pscreen);
+        struct fd3_context *fd3_ctx = CALLOC_STRUCT(fd3_context);
+        struct pipe_context *pctx;
+        if (!fd3_ctx)
+                return NULL;
+        pctx = &fd3_ctx->base.base;
+        fd3_ctx->base.dev = fd_device_ref(screen->dev);
+        fd3_ctx->base.screen = fd_screen(pscreen);
+        pctx->destroy = fd3_context_destroy;
+        pctx->create_blend_state = fd3_blend_state_create;
+        pctx->create_rasterizer_state = fd3_rasterizer_state_create;
+        pctx->create_depth_stencil_alpha_state = fd3_zsa_state_create;
+        fd3_draw_init(pctx);
+        fd3_gmem_init(pctx);
+        fd3_texture_init(pctx);
+        fd3_prog_init(pctx);
+        pctx = fd_context_init(&fd3_ctx->base, pscreen, primtypes, priv);
+        if (!pctx)
+                return NULL;
+        util_dynarray_init(&fd3_ctx->rbrc_patches);
+        fd3_ctx->vs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
+                        DRM_FREEDRENO_GEM_TYPE_KMEM);
+        fd3_ctx->fs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
+                        DRM_FREEDRENO_GEM_TYPE_KMEM);
+        fd3_ctx->vsc_size_mem = fd_bo_new(screen->dev, 0x1000,
+                        DRM_FREEDRENO_GEM_TYPE_KMEM);
+        fd3_ctx->solid_vbuf = create_solid_vertexbuf(pctx);
+        fd3_ctx->blit_texcoord_vbuf = create_blit_texcoord_vertexbuf(pctx);
+        /* setup solid_vbuf_state: */
+        fd3_ctx->solid_vbuf_state.vtx = pctx->create_vertex_elements_state(
+                        pctx, 1, (struct pipe_vertex_element[]){{
+                                .vertex_buffer_index = 0,
+                                .src_offset = 0,
+                                .src_format = PIPE_FORMAT_R32G32B32_FLOAT,
+                        }});
+        fd3_ctx->solid_vbuf_state.vertexbuf.count = 1;
+        fd3_ctx->solid_vbuf_state.vertexbuf.vb[0].stride = 12;
+        fd3_ctx->solid_vbuf_state.vertexbuf.vb[0].buffer = fd3_ctx->solid_vbuf;
+        /* setup blit_vbuf_state: */
+        fd3_ctx->blit_vbuf_state.vtx = pctx->create_vertex_elements_state(
+                        pctx, 2, (struct pipe_vertex_element[]){{
+                                .vertex_buffer_index = 0,
+                                .src_offset = 0,
+                                .src_format = PIPE_FORMAT_R32G32_FLOAT,
+                        }, {
+                                .vertex_buffer_index = 1,
+                                .src_offset = 0,
+                                .src_format = PIPE_FORMAT_R32G32B32_FLOAT,
+                        }});
+        fd3_ctx->blit_vbuf_state.vertexbuf.count = 2;
+        fd3_ctx->blit_vbuf_state.vertexbuf.vb[0].stride = 8;
+        fd3_ctx->blit_vbuf_state.vertexbuf.vb[0].buffer = fd3_ctx->blit_texcoord_vbuf;
+        fd3_ctx->blit_vbuf_state.vertexbuf.vb[1].stride = 12;
+        fd3_ctx->blit_vbuf_state.vertexbuf.vb[1].buffer = fd3_ctx->solid_vbuf;
+        fd3_query_context_init(pctx);
+        fd3_ctx->border_color_uploader = u_upload_create(pctx, 4096,
+* PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, 0);
+        return pctx;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_context.h
 ,0 → 1,127
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_CONTEXT_H_
+#define FD3_CONTEXT_H_
+#include "util/u_upload_mgr.h"
+#include "freedreno_drmif.h"
+#include "freedreno_context.h"
+#include "ir3_shader.h"
+struct fd3_context {
+        struct fd_context base;
+        /* Keep track of writes to RB_RENDER_CONTROL which need to be patched
+         * once we know whether or not to use GMEM, and GMEM tile pitch.
+         */
+        struct util_dynarray rbrc_patches;
+        struct fd_bo *vs_pvt_mem, *fs_pvt_mem;
+        /* This only needs to be 4 * num_of_pipes bytes (ie. 32 bytes).  We
+         * could combine it with another allocation.
+         */
+        struct fd_bo *vsc_size_mem;
+        /* vertex buf used for clear/gmem->mem vertices, and mem->gmem
+         * vertices:
+         */
+        struct pipe_resource *solid_vbuf;
+        /* vertex buf used for mem->gmem tex coords:
+         */
+        struct pipe_resource *blit_texcoord_vbuf;
+        /* vertex state for solid_vbuf:
+         *    - solid_vbuf / 12 / R32G32B32_FLOAT
+         */
+        struct fd_vertex_state solid_vbuf_state;
+        /* vertex state for blit_prog:
+         *    - blit_texcoord_vbuf / 8 / R32G32_FLOAT
+         *    - solid_vbuf / 12 / R32G32B32_FLOAT
+         */
+        struct fd_vertex_state blit_vbuf_state;
+        /*
+         * Border color layout *appears* to be as arrays of 0x40 byte
+         * elements, with frag shader elements starting at (16 x 0x40).
+         * But at some point I should probably experiment more with
+         * samplers in vertex shaders to be sure.  Unclear about why
+         * there is this offset when there are separate VS and FS base
+         * addr regs.
+         *
+         * The first 8 bytes of each entry are the requested border
+         * color in fp16.  Unclear about the rest.. could be used for
+         * other formats, or could simply be for aligning the pitch
+         * to 32 pixels.
+         */
+#define BORDERCOLOR_SIZE 0x40
+        struct u_upload_mgr *border_color_uploader;
+        struct pipe_resource *border_color_buf;
+        /* if *any* of bits are set in {v,f}saturate_{s,t,r} */
+        bool vsaturate, fsaturate;
+        /* bitmask of sampler which needs coords clamped for vertex
+         * shader:
+         */
+        unsigned vsaturate_s, vsaturate_t, vsaturate_r;
+        /* bitmask of sampler which needs coords clamped for frag
+         * shader:
+         */
+        unsigned fsaturate_s, fsaturate_t, fsaturate_r;
+        /* bitmask of integer texture samplers */
+        uint16_t vinteger_s, finteger_s;
+        /* some state changes require a different shader variant.  Keep
+         * track of this so we know when we need to re-emit shader state
+         * due to variant change.  See fixup_shader_state()
+         */
+        struct ir3_shader_key last_key;
+};
+static INLINE struct fd3_context *
+fd3_context(struct fd_context *ctx)
+{
+        return (struct fd3_context *)ctx;
+}
+struct pipe_context *
+fd3_context_create(struct pipe_screen *pscreen, void *priv);
+#endif /* FD3_CONTEXT_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
 ,0 → 1,377
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_state.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "util/u_prim.h"
+#include "util/u_format.h"
+#include "freedreno_state.h"
+#include "freedreno_resource.h"
+#include "fd3_draw.h"
+#include "fd3_context.h"
+#include "fd3_emit.h"
+#include "fd3_program.h"
+#include "fd3_format.h"
+#include "fd3_zsa.h"
+static inline uint32_t
+add_sat(uint32_t a, int32_t b)
+{
+        int64_t ret = (uint64_t)a + (int64_t)b;
+        if (ret > ~0U)
+                return ~0U;
+        if (ret < 0)
+                return 0;
+        return (uint32_t)ret;
+}
+static void
+draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
+                struct fd3_emit *emit)
+{
+        const struct pipe_draw_info *info = emit->info;
+        enum pc_di_primtype primtype = ctx->primtypes[info->mode];
+        fd3_emit_state(ctx, ring, emit);
+        if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
+                fd3_emit_vertex_bufs(ring, emit);
+        OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
+        OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
+        OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
+        OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
+        OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
+        OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
+        OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
+        OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
+        OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
+                        info->restart_index : 0xffffffff);
+        if (ctx->rasterizer && ctx->rasterizer->point_size_per_vertex &&
+                info->mode == PIPE_PRIM_POINTS)
+                primtype = DI_PT_POINTLIST_A2XX;
+        fd_draw_emit(ctx, ring,
+                        primtype,
+                        emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
+                        info);
+}
+/* fixup dirty shader state in case some "unrelated" (from the state-
+ * tracker's perspective) state change causes us to switch to a
+ * different variant.
+ */
+static void
+fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct ir3_shader_key *last_key = &fd3_ctx->last_key;
+        if (!ir3_shader_key_equal(last_key, key)) {
+                ctx->dirty |= FD_DIRTY_PROG;
+                if (last_key->has_per_samp || key->has_per_samp) {
+                        if ((last_key->vsaturate_s != key->vsaturate_s) ||
+                                        (last_key->vsaturate_t != key->vsaturate_t) ||
+                                        (last_key->vsaturate_r != key->vsaturate_r) ||
+                                        (last_key->vinteger_s != key->vinteger_s))
+                                ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
+                        if ((last_key->fsaturate_s != key->fsaturate_s) ||
+                                        (last_key->fsaturate_t != key->fsaturate_t) ||
+                                        (last_key->fsaturate_r != key->fsaturate_r) ||
+                                        (last_key->finteger_s != key->finteger_s))
+                                ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
+                }
+                if (last_key->color_two_side != key->color_two_side)
+                        ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
+                if (last_key->half_precision != key->half_precision)
+                        ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
+                fd3_ctx->last_key = *key;
+        }
+}
+static void
+fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd3_emit emit = {
+                .vtx  = &ctx->vtx,
+                .prog = &ctx->prog,
+                .info = info,
+                .key = {
+                        /* do binning pass first: */
+                        .binning_pass = true,
+                        .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
+                        // TODO set .half_precision based on render target format,
+                        // ie. float16 and smaller use half, float32 use full..
+                        .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
+                        .has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate ||
+                                                         fd3_ctx->vinteger_s || fd3_ctx->finteger_s),
+                        .vsaturate_s = fd3_ctx->vsaturate_s,
+                        .vsaturate_t = fd3_ctx->vsaturate_t,
+                        .vsaturate_r = fd3_ctx->vsaturate_r,
+                        .fsaturate_s = fd3_ctx->fsaturate_s,
+                        .fsaturate_t = fd3_ctx->fsaturate_t,
+                        .fsaturate_r = fd3_ctx->fsaturate_r,
+                        .vinteger_s = fd3_ctx->vinteger_s,
+                        .finteger_s = fd3_ctx->finteger_s,
+                },
+                .rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
+                .sprite_coord_enable = ctx->rasterizer ? ctx->rasterizer->sprite_coord_enable : 0,
+                .sprite_coord_mode = ctx->rasterizer ? ctx->rasterizer->sprite_coord_mode : false,
+        };
+        unsigned dirty;
+        fixup_shader_state(ctx, &emit.key);
+        dirty = ctx->dirty;
+        emit.dirty = dirty & ~(FD_DIRTY_BLEND);
+        draw_impl(ctx, ctx->binning_ring, &emit);
+        /* and now regular (non-binning) pass: */
+        emit.key.binning_pass = false;
+        emit.dirty = dirty;
+        emit.vp = NULL;   /* we changed key so need to refetch vp */
+        draw_impl(ctx, ctx->ring, &emit);
+}
+/* clear operations ignore viewport state, so we need to reset it
+ * based on framebuffer state:
+ */
+static void
+reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
+{
+        float half_width = pfb->width * 0.5f;
+        float half_height = pfb->height * 0.5f;
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
+}
+/* binning pass cmds for a clear:
+ * NOTE: newer blob drivers don't use binning for clear, which is probably
+ * preferable since it is low vtx count.  However that doesn't seem to
+ * actually work for me.  Not sure if it is depending on support for
+ * clear pass (rather than using solid-fill shader), or something else
+ * that newer blob is doing differently.  Once that is figured out, we
+ * can remove fd3_clear_binning().
+ */
+static void
+fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd_ringbuffer *ring = ctx->binning_ring;
+        struct fd3_emit emit = {
+                .vtx  = &fd3_ctx->solid_vbuf_state,
+                .prog = &ctx->solid_prog,
+                .key = {
+                        .binning_pass = true,
+                        .half_precision = true,
+                },
+                .dirty = dirty,
+        };
+        fd3_emit_state(ctx, ring, &emit);
+        fd3_emit_vertex_bufs(ring, &emit);
+        reset_viewport(ring, &ctx->framebuffer);
+        OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
+        OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
+        OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
+        OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
+        OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
+        OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
+        OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
+        OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
+        OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
+        fd_event_write(ctx, ring, PERFCOUNTER_STOP);
+        fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+                        DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
+}
+static void
+fd3_clear(struct fd_context *ctx, unsigned buffers,
+                const union pipe_color_union *color, double depth, unsigned stencil)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+        struct fd_ringbuffer *ring = ctx->ring;
+        unsigned dirty = ctx->dirty;
+        unsigned i;
+        struct fd3_emit emit = {
+                .vtx  = &fd3_ctx->solid_vbuf_state,
+                .prog = &ctx->solid_prog,
+                .key = {
+                        .half_precision = (fd3_half_precision(pfb->cbufs[0]) &&
+                                                           fd3_half_precision(pfb->cbufs[1]) &&
+                                                           fd3_half_precision(pfb->cbufs[2]) &&
+                                                           fd3_half_precision(pfb->cbufs[3])),
+                },
+        };
+        dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
+        dirty |= FD_DIRTY_PROG;
+        emit.dirty = dirty;
+        fd3_clear_binning(ctx, dirty);
+        /* emit generic state now: */
+        fd3_emit_state(ctx, ring, &emit);
+        reset_viewport(ring, &ctx->framebuffer);
+        OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
+        OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
+                        A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
+        OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
+        OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
+                        &fd3_ctx->rbrc_patches);
+        if (buffers & PIPE_CLEAR_DEPTH) {
+                OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
+                OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
+                                A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
+                                A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
+                fd_wfi(ctx, ring);
+                OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
+                OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
+                OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
+                ctx->dirty |= FD_DIRTY_VIEWPORT;
+        } else {
+                OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
+                OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
+        }
+        if (buffers & PIPE_CLEAR_STENCIL) {
+                OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
+                OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
+                                A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
+                                A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
+                OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
+                                A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
+xff000000 | // XXX ???
+                                A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
+                OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
+                OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
+                                A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
+                                A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
+                                A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
+                                A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
+        } else {
+                OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
+                OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
+                                A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
+                                A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
+                OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
+                                A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
+                                A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
+                OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
+                OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
+                                A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
+                                A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
+                                A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
+        }
+        for (i = 0; i < 4; i++) {
+                OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
+                OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
+                                A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
+                                COND(buffers & (PIPE_CLEAR_COLOR0 << i),
+                                         A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf)));
+                OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
+                OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
+        }
+        OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
+        fd3_emit_vertex_bufs(ring, &emit);
+        fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
+        OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
+        OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
+        OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
+        OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
+        OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
+        OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
+        OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
+        OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
+        OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
+        fd_event_write(ctx, ring, PERFCOUNTER_STOP);
+        fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
+                        DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
+}
+void
+fd3_draw_init(struct pipe_context *pctx)
+{
+        struct fd_context *ctx = fd_context(pctx);
+        ctx->draw_vbo = fd3_draw_vbo;
+        ctx->clear = fd3_clear;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_draw.h
 ,0 → 1,38
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_DRAW_H_
+#define FD3_DRAW_H_
+#include "pipe/p_context.h"
+#include "freedreno_draw.h"
+void fd3_draw_init(struct pipe_context *pctx);
+#endif /* FD3_DRAW_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
 ,0 → 1,932
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_state.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "util/u_helpers.h"
+#include "util/u_format.h"
+#include "freedreno_resource.h"
+#include "fd3_emit.h"
+#include "fd3_blend.h"
+#include "fd3_context.h"
+#include "fd3_program.h"
+#include "fd3_rasterizer.h"
+#include "fd3_texture.h"
+#include "fd3_format.h"
+#include "fd3_zsa.h"
+/* regid:          base const register
+ * prsc or dwords: buffer containing constant values
+ * sizedwords:     size of const value buffer
+ */
+void
+fd3_emit_constant(struct fd_ringbuffer *ring,
+                enum adreno_state_block sb,
+                uint32_t regid, uint32_t offset, uint32_t sizedwords,
+                const uint32_t *dwords, struct pipe_resource *prsc)
+{
+        uint32_t i, sz;
+        enum adreno_state_src src;
+        if (prsc) {
+                sz = 0;
+                src = SS_INDIRECT;
+        } else {
+                sz = sizedwords;
+                src = SS_DIRECT;
+        }
+        OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
+        OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
+                        CP_LOAD_STATE_0_STATE_SRC(src) |
+                        CP_LOAD_STATE_0_STATE_BLOCK(sb) |
+                        CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
+        if (prsc) {
+                struct fd_bo *bo = fd_resource(prsc)->bo;
+                OUT_RELOC(ring, bo, offset,
+                                CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
+        } else {
+                OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
+                                CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
+                dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
+        }
+        for (i = 0; i < sz; i++) {
+                OUT_RING(ring, dwords[i]);
+        }
+}
+static void
+emit_constants(struct fd_ringbuffer *ring,
+                enum adreno_state_block sb,
+                struct fd_constbuf_stateobj *constbuf,
+                struct ir3_shader_variant *shader,
+                bool emit_immediates)
+{
+        uint32_t enabled_mask = constbuf->enabled_mask;
+        uint32_t max_const;
+        int i;
+        // XXX TODO only emit dirty consts.. but we need to keep track if
+        // they are clobbered by a clear, gmem2mem, or mem2gmem..
+        constbuf->dirty_mask = enabled_mask;
+        /* in particular, with binning shader we may end up with unused
+         * consts, ie. we could end up w/ constlen that is smaller
+         * than first_immediate.  In that case truncate the user consts
+         * early to avoid HLSQ lockup caused by writing too many consts
+         */
+        max_const = MIN2(shader->first_driver_param, shader->constlen);
+        /* emit user constants: */
+        if (enabled_mask & 1) {
+                const unsigned index = 0;
+                struct pipe_constant_buffer *cb = &constbuf->cb[index];
+                unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
+                // I expect that size should be a multiple of vec4's:
+                assert(size == align(size, 4));
+                /* and even if the start of the const buffer is before
+                 * first_immediate, the end may not be:
+                 */
+                size = MIN2(size, 4 * max_const);
+                if (size && constbuf->dirty_mask & (1 << index)) {
+                        fd3_emit_constant(ring, sb, 0,
+                                                          cb->buffer_offset, size,
+                                                          cb->user_buffer, cb->buffer);
+                        constbuf->dirty_mask &= ~(1 << index);
+                }
+                enabled_mask &= ~(1 << index);
+        }
+        if (shader->constlen > shader->first_driver_param) {
+                uint32_t params = MIN2(4, shader->constlen - shader->first_driver_param);
+                /* emit ubos: */
+                OUT_PKT3(ring, CP_LOAD_STATE, 2 + params * 4);
+                OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(shader->first_driver_param * 2) |
+                                 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
+                                 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
+                                 CP_LOAD_STATE_0_NUM_UNIT(params * 2));
+                OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
+                                 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
+                for (i = 1; i <= params * 4; i++) {
+                        struct pipe_constant_buffer *cb = &constbuf->cb[i];
+                        assert(!cb->user_buffer);
+                        if ((enabled_mask & (1 << i)) && cb->buffer)
+                                OUT_RELOC(ring, fd_resource(cb->buffer)->bo, cb->buffer_offset, 0, 0);
+                        else
+                                OUT_RING(ring, 0xbad00000 | ((i - 1) << 16));
+                }
+        }
+        /* emit shader immediates: */
+        if (shader && emit_immediates) {
+                int size = shader->immediates_count;
+                uint32_t base = shader->first_immediate;
+                /* truncate size to avoid writing constants that shader
+                 * does not use:
+                 */
+                size = MIN2(size + base, shader->constlen) - base;
+                /* convert out of vec4: */
+                base *= 4;
+                size *= 4;
+                if (size > 0) {
+                        fd3_emit_constant(ring, sb, base,
+, size, shader->immediates[0].val, NULL);
+                }
+        }
+}
+#define VERT_TEX_OFF    0
+#define FRAG_TEX_OFF    16
+#define BASETABLE_SZ    A3XX_MAX_MIP_LEVELS
+static void
+emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
+                enum adreno_state_block sb, struct fd_texture_stateobj *tex)
+{
+        static const unsigned tex_off[] = {
+                        [SB_VERT_TEX] = VERT_TEX_OFF,
+                        [SB_FRAG_TEX] = FRAG_TEX_OFF,
+        };
+        static const enum adreno_state_block mipaddr[] = {
+                        [SB_VERT_TEX] = SB_VERT_MIPADDR,
+                        [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
+        };
+        static const uint32_t bcolor_reg[] = {
+                        [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
+                        [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
+        };
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        unsigned i, j, off;
+        void *ptr;
+        u_upload_alloc(fd3_ctx->border_color_uploader,
+, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
+                        &fd3_ctx->border_color_buf,
+                        &ptr);
+        if (tex->num_samplers > 0) {
+                /* output sampler state: */
+                OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
+                OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
+                                CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
+                                CP_LOAD_STATE_0_STATE_BLOCK(sb) |
+                                CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
+                OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
+                                CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
+                for (i = 0; i < tex->num_samplers; i++) {
+                        static const struct fd3_sampler_stateobj dummy_sampler = {};
+                        const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
+                                        fd3_sampler_stateobj(tex->samplers[i]) :
+                                        &dummy_sampler;
+                        uint16_t *bcolor = (uint16_t *)((uint8_t *)ptr +
+                                        (BORDERCOLOR_SIZE * tex_off[sb]) +
+                                        (BORDERCOLOR_SIZE * i));
+                        uint32_t *bcolor32 = (uint32_t *)&bcolor[16];
+                        /*
+                         * XXX HACK ALERT XXX
+                         *
+                         * The border colors need to be swizzled in a particular
+                         * format-dependent order. Even though samplers don't know about
+                         * formats, we can assume that with a GL state tracker, there's a
+                         * 1:1 correspondence between sampler and texture. Take advantage
+                         * of that knowledge.
+                         */
+                        if (i < tex->num_textures && tex->textures[i]) {
+                                const struct util_format_description *desc =
+                                        util_format_description(tex->textures[i]->format);
+                                for (j = 0; j < 4; j++) {
+                                        if (desc->swizzle[j] >= 4)
+                                                continue;
+                                        const struct util_format_channel_description *chan =
+                                                &desc->channel[desc->swizzle[j]];
+                                        int size = chan->size;
+                                        /* The Z16 texture format we use seems to look in the
+                                         * 32-bit border color slots
+                                         */
+                                        if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
+                                                size = 32;
+                                        /* Formats like R11G11B10 or RGB9_E5 don't specify
+                                         * per-channel sizes properly.
+                                         */
+                                        if (desc->layout == UTIL_FORMAT_LAYOUT_OTHER)
+                                                size = 16;
+                                        if (chan->pure_integer && size > 16)
+                                                bcolor32[desc->swizzle[j] + 4] =
+                                                        sampler->base.border_color.i[j];
+                                        else if (size > 16)
+                                                bcolor32[desc->swizzle[j]] =
+                                                        fui(sampler->base.border_color.f[j]);
+                                        else if (chan->pure_integer)
+                                                bcolor[desc->swizzle[j] + 8] =
+                                                        sampler->base.border_color.i[j];
+                                        else
+                                                bcolor[desc->swizzle[j]] =
+                                                        util_float_to_half(sampler->base.border_color.f[j]);
+                                }
+                        }
+                        OUT_RING(ring, sampler->texsamp0);
+                        OUT_RING(ring, sampler->texsamp1);
+                }
+        }
+        if (tex->num_textures > 0) {
+                /* emit texture state: */
+                OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
+                OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
+                                CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
+                                CP_LOAD_STATE_0_STATE_BLOCK(sb) |
+                                CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
+                OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
+                                CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
+                for (i = 0; i < tex->num_textures; i++) {
+                        static const struct fd3_pipe_sampler_view dummy_view = {};
+                        const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
+                                        fd3_pipe_sampler_view(tex->textures[i]) :
+                                        &dummy_view;
+                        OUT_RING(ring, view->texconst0);
+                        OUT_RING(ring, view->texconst1);
+                        OUT_RING(ring, view->texconst2 |
+                                        A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
+                        OUT_RING(ring, view->texconst3);
+                }
+                /* emit mipaddrs: */
+                OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
+                OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
+                                CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
+                                CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
+                                CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
+                OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
+                                CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
+                for (i = 0; i < tex->num_textures; i++) {
+                        static const struct fd3_pipe_sampler_view dummy_view = {
+                                        .base.u.tex.first_level = 1,
+                        };
+                        const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
+                                        fd3_pipe_sampler_view(tex->textures[i]) :
+                                        &dummy_view;
+                        struct fd_resource *rsc = fd_resource(view->base.texture);
+                        unsigned start = view->base.u.tex.first_level;
+                        unsigned end   = view->base.u.tex.last_level;
+                        for (j = 0; j < (end - start + 1); j++) {
+                                struct fd_resource_slice *slice =
+                                                fd_resource_slice(rsc, j + start);
+                                OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
+                        }
+                        /* pad the remaining entries w/ null: */
+                        for (; j < BASETABLE_SZ; j++) {
+                                OUT_RING(ring, 0x00000000);
+                        }
+                }
+        }
+        OUT_PKT0(ring, bcolor_reg[sb], 1);
+        OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
+        u_upload_unmap(fd3_ctx->border_color_uploader);
+}
+/* emit texture state for mem->gmem restore operation.. eventually it would
+ * be good to get rid of this and use normal CSO/etc state for more of these
+ * special cases, but for now the compiler is not sufficient..
+ *
+ * Also, for using normal state, not quite sure how to handle the special
+ * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
+ */
+void
+fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
+                                                  struct pipe_surface **psurf,
+                                                  int bufs)
+{
+        int i, j;
+        /* output sampler state: */
+        OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
+        OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
+                        CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
+                        CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
+                        CP_LOAD_STATE_0_NUM_UNIT(bufs));
+        OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
+                        CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
+        for (i = 0; i < bufs; i++) {
+                OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
+                                 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
+                                 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
+                                 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
+                                 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
+                OUT_RING(ring, 0x00000000);
+        }
+        /* emit texture state: */
+        OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
+        OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
+                        CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
+                        CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
+                        CP_LOAD_STATE_0_NUM_UNIT(bufs));
+        OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
+                        CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
+        for (i = 0; i < bufs; i++) {
+                if (!psurf[i]) {
+                        OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
+                                A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
+                                A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
+                                A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
+                                A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
+                        OUT_RING(ring, 0x00000000);
+                        OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
+                        OUT_RING(ring, 0x00000000);
+                        continue;
+                }
+                struct fd_resource *rsc = fd_resource(psurf[i]->texture);
+                enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
+                /* The restore blit_zs shader expects stencil in sampler 0, and depth
+                 * in sampler 1
+                 */
+                if (rsc->stencil && i == 0) {
+                        rsc = rsc->stencil;
+                        format = fd3_gmem_restore_format(rsc->base.b.format);
+                }
+                unsigned lvl = psurf[i]->u.tex.level;
+                struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
+                debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
+                OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
+                                 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
+                                 fd3_tex_swiz(format,  PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
+                                                          PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
+                OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
+                                 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
+                                 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
+                OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
+                                 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
+                OUT_RING(ring, 0x00000000);
+        }
+        /* emit mipaddrs: */
+        OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
+        OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
+                        CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
+                        CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
+                        CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
+        OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
+                        CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
+        for (i = 0; i < bufs; i++) {
+                if (psurf[i]) {
+                        struct fd_resource *rsc = fd_resource(psurf[i]->texture);
+                        /* Matches above logic for blit_zs shader */
+                        if (rsc->stencil && i == 0)
+                                rsc = rsc->stencil;
+                        unsigned lvl = psurf[i]->u.tex.level;
+                        uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
+                        OUT_RELOC(ring, rsc->bo, offset, 0, 0);
+                } else {
+                        OUT_RING(ring, 0x00000000);
+                }
+                /* pad the remaining entries w/ null: */
+                for (j = 1; j < BASETABLE_SZ; j++) {
+                        OUT_RING(ring, 0x00000000);
+                }
+        }
+}
+void
+fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
+{
+        int32_t i, j, last = -1;
+        uint32_t total_in = 0;
+        const struct fd_vertex_state *vtx = emit->vtx;
+        struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
+        unsigned vertex_regid = regid(63, 0), instance_regid = regid(63, 0);
+        for (i = 0; i < vp->inputs_count; i++) {
+                uint8_t semantic = sem2name(vp->inputs[i].semantic);
+                if (semantic == TGSI_SEMANTIC_VERTEXID_NOBASE)
+                        vertex_regid = vp->inputs[i].regid;
+                else if (semantic == TGSI_SEMANTIC_INSTANCEID)
+                        instance_regid = vp->inputs[i].regid;
+                else if (i < vtx->vtx->num_elements && vp->inputs[i].compmask)
+                        last = i;
+        }
+        /* hw doesn't like to be configured for zero vbo's, it seems: */
+        if (vtx->vtx->num_elements == 0 &&
+                vertex_regid == regid(63, 0) &&
+                instance_regid == regid(63, 0))
+                return;
+        for (i = 0, j = 0; i <= last; i++) {
+                assert(sem2name(vp->inputs[i].semantic) == 0);
+                if (vp->inputs[i].compmask) {
+                        struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
+                        const struct pipe_vertex_buffer *vb =
+                                        &vtx->vertexbuf.vb[elem->vertex_buffer_index];
+                        struct fd_resource *rsc = fd_resource(vb->buffer);
+                        enum pipe_format pfmt = elem->src_format;
+                        enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
+                        bool switchnext = (i != last) ||
+                                vertex_regid != regid(63, 0) ||
+                                instance_regid != regid(63, 0);
+                        bool isint = util_format_is_pure_integer(pfmt);
+                        uint32_t fs = util_format_get_blocksize(pfmt);
+                        debug_assert(fmt != ~0);
+                        OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
+                        OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
+                                        A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
+                                        COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
+                                        A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
+                                        COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
+                                        A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
+                        OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
+                        OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
+                        OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
+                                        A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
+                                        A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
+                                        A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
+                                        A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
+                                        A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
+                                        A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
+                                        COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
+                                        COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
+                        total_in += vp->inputs[i].ncomp;
+                        j++;
+                }
+        }
+        OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
+        OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
+                        A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
+                        A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
+                        A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
+        OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
+                        A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
+                        A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
+}
+void
+fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
+                struct fd3_emit *emit)
+{
+        struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
+        struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
+        uint32_t dirty = emit->dirty;
+        emit_marker(ring, 5);
+        if (dirty & FD_DIRTY_SAMPLE_MASK) {
+                OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
+                OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
+                                A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
+                                A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
+        }
+        if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
+                uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control;
+                val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
+                val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
+                                A3XX_RB_RENDER_CONTROL_YCOORD |
+                                A3XX_RB_RENDER_CONTROL_ZCOORD |
+                                A3XX_RB_RENDER_CONTROL_WCOORD);
+                /* I suppose if we needed to (which I don't *think* we need
+                 * to), we could emit this for binning pass too.  But we
+                 * would need to keep a different patch-list for binning
+                 * vs render pass.
+                 */
+                OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
+                OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
+        }
+        if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
+                struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
+                struct pipe_stencil_ref *sr = &ctx->stencil_ref;
+                OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
+                OUT_RING(ring, zsa->rb_alpha_ref);
+                OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
+                OUT_RING(ring, zsa->rb_stencil_control);
+                OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
+                OUT_RING(ring, zsa->rb_stencilrefmask |
+                                A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
+                OUT_RING(ring, zsa->rb_stencilrefmask_bf |
+                                A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
+        }
+        if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
+                uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
+                if (fp->writes_pos) {
+                        val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
+                        val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
+                }
+                if (fp->has_kill) {
+                        val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
+                }
+                OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
+                OUT_RING(ring, val);
+        }
+        if (dirty & FD_DIRTY_RASTERIZER) {
+                struct fd3_rasterizer_stateobj *rasterizer =
+                                fd3_rasterizer_stateobj(ctx->rasterizer);
+                OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
+                OUT_RING(ring, rasterizer->gras_su_mode_control);
+                OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
+                OUT_RING(ring, rasterizer->gras_su_point_minmax);
+                OUT_RING(ring, rasterizer->gras_su_point_size);
+                OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
+                OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
+                OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
+        }
+        if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
+                uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
+                                ->gras_cl_clip_cntl;
+                val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
+                val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
+                                A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
+                OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
+                OUT_RING(ring, val);
+        }
+        /* NOTE: since primitive_restart is not actually part of any
+         * state object, we need to make sure that we always emit
+         * PRIM_VTX_CNTL.. either that or be more clever and detect
+         * when it changes.
+         */
+        if (emit->info) {
+                const struct pipe_draw_info *info = emit->info;
+                uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
+                                ->pc_prim_vtx_cntl;
+                if (!emit->key.binning_pass) {
+                        uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
+                        if (stride_in_vpc > 0)
+                                stride_in_vpc = MAX2(stride_in_vpc, 2);
+                        val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
+                }
+                if (info->indexed && info->primitive_restart) {
+                        val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
+                }
+                val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
+                OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
+                OUT_RING(ring, val);
+        }
+        if (dirty & FD_DIRTY_SCISSOR) {
+                struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
+                OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
+                OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
+                                A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
+                OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
+                                A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
+                ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
+                ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
+                ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
+                ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
+        }
+        if (dirty & FD_DIRTY_VIEWPORT) {
+                fd_wfi(ctx, ring);
+                OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
+                OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
+                OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
+                OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
+                OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
+                OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
+                OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
+        }
+        if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
+                struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+                fd3_program_emit(ring, emit, pfb->nr_cbufs, pfb->cbufs);
+        }
+        /* TODO we should not need this or fd_wfi() before emit_constants():
+         */
+        OUT_PKT3(ring, CP_EVENT_WRITE, 1);
+        OUT_RING(ring, HLSQ_FLUSH);
+        if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
+                        /* evil hack to deal sanely with clear path: */
+                        (emit->prog == &ctx->prog)) {
+                fd_wfi(ctx, ring);
+                emit_constants(ring,  SB_VERT_SHADER,
+                                &ctx->constbuf[PIPE_SHADER_VERTEX],
+                                vp, emit->prog->dirty & FD_SHADER_DIRTY_VP);
+                if (!emit->key.binning_pass) {
+                        emit_constants(ring, SB_FRAG_SHADER,
+                                        &ctx->constbuf[PIPE_SHADER_FRAGMENT],
+                                        fp, emit->prog->dirty & FD_SHADER_DIRTY_FP);
+                }
+        }
+        /* emit driver params every time */
+        if (emit->info && emit->prog == &ctx->prog) {
+                uint32_t vertex_params[4] = {
+                        emit->info->indexed ? emit->info->index_bias : emit->info->start,
+,
+,
+                };
+                if (vp->constlen >= vp->first_driver_param + 4) {
+                        fd3_emit_constant(ring, SB_VERT_SHADER,
+                                                          (vp->first_driver_param + 4) * 4,
+, 4, vertex_params, NULL);
+                }
+        }
+        if ((dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) && ctx->blend) {
+                struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
+                uint32_t i;
+                for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
+                        enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
+                        const struct util_format_description *desc =
+                                util_format_description(format);
+                        bool is_float = util_format_is_float(format);
+                        bool is_int = util_format_is_pure_integer(format);
+                        bool has_alpha = util_format_has_alpha(format);
+                        uint32_t control = blend->rb_mrt[i].control;
+                        uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
+                        if (is_int) {
+                                control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
+                                                        A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
+                                control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
+                        }
+                        if (format == PIPE_FORMAT_NONE)
+                                control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
+                        if (has_alpha) {
+                                blend_control |= blend->rb_mrt[i].blend_control_rgb;
+                        } else {
+                                blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
+                                control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
+                        }
+                        if (format && util_format_get_component_bits(
+                                                format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
+                                const struct pipe_rt_blend_state *rt;
+                                if (ctx->blend->independent_blend_enable)
+                                        rt = &ctx->blend->rt[i];
+                                else
+                                        rt = &ctx->blend->rt[0];
+                                if (!util_format_colormask_full(desc, rt->colormask))
+                                        control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
+                        }
+                        OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
+                        OUT_RING(ring, control);
+                        OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
+                        OUT_RING(ring, blend_control |
+                                        COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
+                }
+        }
+        if (dirty & FD_DIRTY_BLEND_COLOR) {
+                struct pipe_blend_color *bcolor = &ctx->blend_color;
+                OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
+                OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
+                                A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
+                OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
+                                A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
+                OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
+                                A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
+                OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
+                                A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
+        }
+        if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
+                fd_wfi(ctx, ring);
+        if (dirty & FD_DIRTY_VERTTEX) {
+                if (vp->has_samp)
+                        emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
+                else
+                        dirty &= ~FD_DIRTY_VERTTEX;
+        }
+        if (dirty & FD_DIRTY_FRAGTEX) {
+                if (fp->has_samp)
+                        emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
+                else
+                        dirty &= ~FD_DIRTY_FRAGTEX;
+        }
+        ctx->dirty &= ~dirty;
+}
+/* emit setup at begin of new cmdstream buffer (don't rely on previous
+ * state, there could have been a context switch between ioctls):
+ */
+void
+fd3_emit_restore(struct fd_context *ctx)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd_ringbuffer *ring = ctx->ring;
+        int i;
+        if (ctx->screen->gpu_id == 320) {
+                OUT_PKT3(ring, CP_REG_RMW, 3);
+                OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
+                OUT_RING(ring, 0xfffcffff);
+                OUT_RING(ring, 0x00000000);
+        }
+        fd_wfi(ctx, ring);
+        OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
+        OUT_RING(ring, 0x00007fff);
+        OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
+        OUT_RING(ring, 0x08000001);                  /* SP_VS_PVT_MEM_CTRL_REG */
+        OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
+        OUT_RING(ring, 0x00000000);                  /* SP_VS_PVT_MEM_SIZE_REG */
+        OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
+        OUT_RING(ring, 0x08000001);                  /* SP_FS_PVT_MEM_CTRL_REG */
+        OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
+        OUT_RING(ring, 0x00000000);                  /* SP_FS_PVT_MEM_SIZE_REG */
+        OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
+        OUT_RING(ring, 0x0000000b);                  /* PC_VERTEX_REUSE_BLOCK_CNTL */
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+        OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
+        OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
+                        A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
+                        A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
+        OUT_RING(ring, 0x00000000);        /* RB_ALPHA_REF */
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
+        OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
+                        A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
+        OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
+        OUT_RING(ring, 0x00000001);        /* GRAS_TSE_DEBUG_ECO */
+        OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
+        OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
+                        A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
+                        A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
+        OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
+        OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
+                        A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
+                        A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
+        OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
+        OUT_RING(ring, 0x00000000);        /* VPC_VARY_CYLWRAP_ENABLE_0 */
+        OUT_RING(ring, 0x00000000);        /* VPC_VARY_CYLWRAP_ENABLE_1 */
+        OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
+        OUT_RING(ring, 0x00000001);        /* UNKNOWN_0E43 */
+        OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
+        OUT_RING(ring, 0x00000001);        /* UNKNOWN_0F03 */
+        OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
+        OUT_RING(ring, 0x00000003);        /* UNKNOWN_0EE0 */
+        OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
+        OUT_RING(ring, 0x00000001);        /* UNKNOWN_0C3D */
+        OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
+        OUT_RING(ring, 0x00000000);        /* HLSQ_PERFCOUNTER0_SELECT */
+        OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
+        OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
+                        A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
+        OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
+                        A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
+        OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
+        OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
+        OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
+                        A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
+                        A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
+        OUT_RING(ring, 0x00000000);                  /* GRAS_CL_CLIP_CNTL */
+        OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
+        OUT_RING(ring, 0xffc00010);        /* GRAS_SU_POINT_MINMAX */
+        OUT_RING(ring, 0x00000008);        /* GRAS_SU_POINT_SIZE */
+        OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
+        OUT_RING(ring, 0xffffffff);        /* PC_RESTART_INDEX */
+        OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
+        OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
+                        A3XX_RB_WINDOW_OFFSET_Y(0));
+        OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
+        OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
+                        A3XX_RB_BLEND_RED_FLOAT(0.0));
+        OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
+                        A3XX_RB_BLEND_GREEN_FLOAT(0.0));
+        OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
+                        A3XX_RB_BLEND_BLUE_FLOAT(0.0));
+        OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
+                        A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
+        for (i = 0; i < 6; i++) {
+                OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
+                OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].X */
+                OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].Y */
+                OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].Z */
+                OUT_RING(ring, 0x00000000);    /* GRAS_CL_USER_PLANE[i].W */
+        }
+        OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
+        OUT_RING(ring, 0x00000000);
+        fd_event_write(ctx, ring, CACHE_FLUSH);
+        if (is_a3xx_p0(ctx->screen)) {
+                OUT_PKT3(ring, CP_DRAW_INDX, 3);
+                OUT_RING(ring, 0x00000000);
+                OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
+                                                        INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
+                OUT_RING(ring, 0);                                      /* NumIndices */
+        }
+        OUT_PKT3(ring, CP_NOP, 4);
+        OUT_RING(ring, 0x00000000);
+        OUT_RING(ring, 0x00000000);
+        OUT_RING(ring, 0x00000000);
+        OUT_RING(ring, 0x00000000);
+        fd_wfi(ctx, ring);
+        ctx->needs_rb_fbd = true;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
 ,0 → 1,93
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_EMIT_H
+#define FD3_EMIT_H
+#include "pipe/p_context.h"
+#include "freedreno_context.h"
+#include "fd3_format.h"
+#include "fd3_program.h"
+#include "ir3_shader.h"
+struct fd_ringbuffer;
+enum adreno_state_block;
+void fd3_emit_constant(struct fd_ringbuffer *ring,
+                enum adreno_state_block sb,
+                uint32_t regid, uint32_t offset, uint32_t sizedwords,
+                const uint32_t *dwords, struct pipe_resource *prsc);
+void fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
+                struct pipe_surface **psurf, int bufs);
+/* grouped together emit-state for prog/vertex/state emit: */
+struct fd3_emit {
+        const struct fd_vertex_state *vtx;
+        const struct fd_program_stateobj *prog;
+        const struct pipe_draw_info *info;
+        struct ir3_shader_key key;
+        uint32_t dirty;
+        uint32_t sprite_coord_enable;
+        bool sprite_coord_mode;
+        bool rasterflat;
+        /* cached to avoid repeated lookups of same variants: */
+        struct ir3_shader_variant *vp, *fp;
+};
+static inline struct ir3_shader_variant *
+fd3_emit_get_vp(struct fd3_emit *emit)
+{
+        if (!emit->vp) {
+                struct fd3_shader_stateobj *so = emit->prog->vp;
+                emit->vp = ir3_shader_variant(so->shader, emit->key);
+        }
+        return emit->vp;
+}
+static inline struct ir3_shader_variant *
+fd3_emit_get_fp(struct fd3_emit *emit)
+{
+        if (!emit->fp) {
+                struct fd3_shader_stateobj *so = emit->prog->fp;
+                emit->fp = ir3_shader_variant(so->shader, emit->key);
+        }
+        return emit->fp;
+}
+void fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit);
+void fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
+                struct fd3_emit *emit);
+void fd3_emit_restore(struct fd_context *ctx);
+#endif /* FD3_EMIT_H */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_format.c
 ,0 → 1,384
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+#include "pipe/p_defines.h"
+#include "util/u_format.h"
+#include "fd3_format.h"
+/* Specifies the table of all the formats and their features. Also supplies
+ * the helpers that look up various data in those tables.
+ */
+struct fd3_format {
+        enum a3xx_vtx_fmt vtx;
+        enum a3xx_tex_fmt tex;
+        enum a3xx_color_fmt rb;
+        enum a3xx_color_swap swap;
+        boolean present;
+};
+#define RB_NONE ~0
+/* vertex + texture */
+#define VT(pipe, fmt, rbfmt, swapfmt) \
+        [PIPE_FORMAT_ ## pipe] = { \
+                .present = 1, \
+                .vtx = VFMT_ ## fmt, \
+                .tex = TFMT_ ## fmt, \
+                .rb = RB_ ## rbfmt, \
+                .swap = swapfmt \
+        }
+/* texture-only */
+#define _T(pipe, fmt, rbfmt, swapfmt) \
+        [PIPE_FORMAT_ ## pipe] = { \
+                .present = 1, \
+                .vtx = ~0, \
+                .tex = TFMT_ ## fmt, \
+                .rb = RB_ ## rbfmt, \
+                .swap = swapfmt \
+        }
+/* vertex-only */
+#define V_(pipe, fmt, rbfmt, swapfmt) \
+        [PIPE_FORMAT_ ## pipe] = { \
+                .present = 1, \
+                .vtx = VFMT_ ## fmt, \
+                .tex = ~0, \
+                .rb = RB_ ## rbfmt, \
+                .swap = swapfmt \
+        }
+static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
+        /* 8-bit */
+        VT(R8_UNORM,   8_UNORM, R8_UNORM, WZYX),
+        VT(R8_SNORM,   8_SNORM, NONE,     WZYX),
+        VT(R8_UINT,    8_UINT,  R8_UINT,  WZYX),
+        VT(R8_SINT,    8_SINT,  R8_SINT,  WZYX),
+        V_(R8_USCALED, 8_UINT,  NONE,     WZYX),
+        V_(R8_SSCALED, 8_UINT,  NONE,     WZYX),
+        _T(A8_UNORM,   8_UNORM, A8_UNORM, WZYX),
+        _T(L8_UNORM,   8_UNORM, R8_UNORM, WZYX),
+        _T(I8_UNORM,   8_UNORM, NONE,     WZYX),
+        _T(A8_UINT,    8_UINT,  NONE,     WZYX),
+        _T(A8_SINT,    8_SINT,  NONE,     WZYX),
+        _T(L8_UINT,    8_UINT,  NONE,     WZYX),
+        _T(L8_SINT,    8_SINT,  NONE,     WZYX),
+        _T(I8_UINT,    8_UINT,  NONE,     WZYX),
+        _T(I8_SINT,    8_SINT,  NONE,     WZYX),
+        _T(S8_UINT,    8_UINT,  R8_UNORM, WZYX),
+        /* 16-bit */
+        VT(R16_UNORM,   16_UNORM, NONE,     WZYX),
+        VT(R16_SNORM,   16_SNORM, NONE,     WZYX),
+        VT(R16_UINT,    16_UINT,  R16_UINT, WZYX),
+        VT(R16_SINT,    16_SINT,  R16_SINT, WZYX),
+        V_(R16_USCALED, 16_UINT,  NONE,     WZYX),
+        V_(R16_SSCALED, 16_UINT,  NONE,     WZYX),
+        VT(R16_FLOAT,   16_FLOAT, R16_FLOAT,WZYX),
+        _T(A16_UINT,    16_UINT,  NONE,     WZYX),
+        _T(A16_SINT,    16_SINT,  NONE,     WZYX),
+        _T(L16_UINT,    16_UINT,  NONE,     WZYX),
+        _T(L16_SINT,    16_SINT,  NONE,     WZYX),
+        _T(I16_UINT,    16_UINT,  NONE,     WZYX),
+        _T(I16_SINT,    16_SINT,  NONE,     WZYX),
+        VT(R8G8_UNORM,   8_8_UNORM, R8G8_UNORM, WZYX),
+        VT(R8G8_SNORM,   8_8_SNORM, R8G8_SNORM, WZYX),
+        VT(R8G8_UINT,    8_8_UINT,  NONE,       WZYX),
+        VT(R8G8_SINT,    8_8_SINT,  NONE,       WZYX),
+        V_(R8G8_USCALED, 8_8_UINT,  NONE,       WZYX),
+        V_(R8G8_SSCALED, 8_8_SINT,  NONE,       WZYX),
+        _T(L8A8_UINT,    8_8_UINT,  NONE,       WZYX),
+        _T(L8A8_SINT,    8_8_SINT,  NONE,       WZYX),
+        _T(Z16_UNORM,      Z16_UNORM,     R8G8_UNORM,     WZYX),
+        _T(B5G6R5_UNORM,   5_6_5_UNORM,   R5G6B5_UNORM,   WXYZ),
+        _T(B5G5R5A1_UNORM, 5_5_5_1_UNORM, R5G5B5A1_UNORM, WXYZ),
+        _T(B5G5R5X1_UNORM, 5_5_5_1_UNORM, R5G5B5A1_UNORM, WXYZ),
+        _T(B4G4R4A4_UNORM, 4_4_4_4_UNORM, R4G4B4A4_UNORM, WXYZ),
+        /* 24-bit */
+        V_(R8G8B8_UNORM,   8_8_8_UNORM, NONE, WZYX),
+        V_(R8G8B8_SNORM,   8_8_8_SNORM, NONE, WZYX),
+        V_(R8G8B8_UINT,    8_8_8_UINT,  NONE, WZYX),
+        V_(R8G8B8_SINT,    8_8_8_SINT,  NONE, WZYX),
+        V_(R8G8B8_USCALED, 8_8_8_UINT,  NONE, WZYX),
+        V_(R8G8B8_SSCALED, 8_8_8_SINT,  NONE, WZYX),
+        /* 32-bit */
+        VT(R32_UINT,    32_UINT,  R32_UINT, WZYX),
+        VT(R32_SINT,    32_SINT,  R32_SINT, WZYX),
+        V_(R32_USCALED, 32_UINT,  NONE,     WZYX),
+        V_(R32_SSCALED, 32_UINT,  NONE,     WZYX),
+        VT(R32_FLOAT,   32_FLOAT, R32_FLOAT,WZYX),
+        V_(R32_FIXED,   32_FIXED, NONE,     WZYX),
+        _T(A32_UINT,    32_UINT,  NONE,     WZYX),
+        _T(A32_SINT,    32_SINT,  NONE,     WZYX),
+        _T(L32_UINT,    32_UINT,  NONE,     WZYX),
+        _T(L32_SINT,    32_SINT,  NONE,     WZYX),
+        _T(I32_UINT,    32_UINT,  NONE,     WZYX),
+        _T(I32_SINT,    32_SINT,  NONE,     WZYX),
+        VT(R16G16_UNORM,   16_16_UNORM, NONE,        WZYX),
+        VT(R16G16_SNORM,   16_16_SNORM, NONE,        WZYX),
+        VT(R16G16_UINT,    16_16_UINT,  R16G16_UINT, WZYX),
+        VT(R16G16_SINT,    16_16_SINT,  R16G16_SINT, WZYX),
+        V_(R16G16_USCALED, 16_16_UINT,  NONE,        WZYX),
+        V_(R16G16_SSCALED, 16_16_SINT,  NONE,        WZYX),
+        VT(R16G16_FLOAT,   16_16_FLOAT, R16G16_FLOAT,WZYX),
+        _T(L16A16_UINT,    16_16_UINT,  NONE,        WZYX),
+        _T(L16A16_SINT,    16_16_SINT,  NONE,        WZYX),
+        VT(R8G8B8A8_UNORM,   8_8_8_8_UNORM, R8G8B8A8_UNORM, WZYX),
+        _T(R8G8B8X8_UNORM,   8_8_8_8_UNORM, R8G8B8A8_UNORM, WZYX),
+        _T(R8G8B8A8_SRGB,    8_8_8_8_UNORM, R8G8B8A8_UNORM, WZYX),
+        _T(R8G8B8X8_SRGB,    8_8_8_8_UNORM, R8G8B8A8_UNORM, WZYX),
+        VT(R8G8B8A8_SNORM,   8_8_8_8_SNORM, R8G8B8A8_SNORM, WZYX),
+        VT(R8G8B8A8_UINT,    8_8_8_8_UINT,  R8G8B8A8_UINT,  WZYX),
+        VT(R8G8B8A8_SINT,    8_8_8_8_SINT,  R8G8B8A8_SINT,  WZYX),
+        V_(R8G8B8A8_USCALED, 8_8_8_8_UINT,  NONE,           WZYX),
+        V_(R8G8B8A8_SSCALED, 8_8_8_8_SINT,  NONE,           WZYX),
+        VT(B8G8R8A8_UNORM,   8_8_8_8_UNORM, R8G8B8A8_UNORM, WXYZ),
+        _T(B8G8R8X8_UNORM,   8_8_8_8_UNORM, R8G8B8A8_UNORM, WXYZ),
+        VT(B8G8R8A8_SRGB,    8_8_8_8_UNORM, R8G8B8A8_UNORM, WXYZ),
+        _T(B8G8R8X8_SRGB,    8_8_8_8_UNORM, R8G8B8A8_UNORM, WXYZ),
+        VT(A8B8G8R8_UNORM,   8_8_8_8_UNORM, R8G8B8A8_UNORM, XYZW),
+        _T(X8B8G8R8_UNORM,   8_8_8_8_UNORM, R8G8B8A8_UNORM, XYZW),
+        _T(A8B8G8R8_SRGB,    8_8_8_8_UNORM, R8G8B8A8_UNORM, XYZW),
+        _T(X8B8G8R8_SRGB,    8_8_8_8_UNORM, R8G8B8A8_UNORM, XYZW),
+        VT(A8R8G8B8_UNORM,   8_8_8_8_UNORM, R8G8B8A8_UNORM, ZYXW),
+        _T(X8R8G8B8_UNORM,   8_8_8_8_UNORM, R8G8B8A8_UNORM, ZYXW),
+        _T(A8R8G8B8_SRGB,    8_8_8_8_UNORM, R8G8B8A8_UNORM, ZYXW),
+        _T(X8R8G8B8_SRGB,    8_8_8_8_UNORM, R8G8B8A8_UNORM, ZYXW),
+        VT(R10G10B10A2_UNORM,   10_10_10_2_UNORM, R10G10B10A2_UNORM, WZYX),
+        VT(B10G10R10A2_UNORM,   10_10_10_2_UNORM, R10G10B10A2_UNORM, WXYZ),
+        _T(B10G10R10X2_UNORM,   10_10_10_2_UNORM, R10G10B10A2_UNORM, WXYZ),
+        V_(R10G10B10A2_SNORM,   10_10_10_2_SNORM, NONE,              WZYX),
+        V_(R10G10B10A2_UINT,    10_10_10_2_UINT,  NONE,              WZYX),
+        V_(R10G10B10A2_USCALED, 10_10_10_2_UINT,  NONE,              WZYX),
+        V_(R10G10B10A2_SSCALED, 10_10_10_2_SINT,  NONE,              WZYX),
+        _T(R11G11B10_FLOAT, 11_11_10_FLOAT, R11G11B10_FLOAT, WZYX),
+        _T(R9G9B9E5_FLOAT,  9_9_9_E5_FLOAT, NONE,            WZYX),
+        _T(Z24X8_UNORM,       X8Z24_UNORM, R8G8B8A8_UNORM, WZYX),
+        _T(Z24_UNORM_S8_UINT, X8Z24_UNORM, R8G8B8A8_UNORM, WZYX),
+        _T(Z32_FLOAT,         Z32_FLOAT,   R8G8B8A8_UNORM, WZYX),
+        _T(Z32_FLOAT_S8X24_UINT, Z32_FLOAT,R8G8B8A8_UNORM, WZYX),
+        /* 48-bit */
+        V_(R16G16B16_UNORM,   16_16_16_UNORM, NONE, WZYX),
+        V_(R16G16B16_SNORM,   16_16_16_SNORM, NONE, WZYX),
+        V_(R16G16B16_UINT,    16_16_16_UINT,  NONE, WZYX),
+        V_(R16G16B16_SINT,    16_16_16_SINT,  NONE, WZYX),
+        V_(R16G16B16_USCALED, 16_16_16_UINT,  NONE, WZYX),
+        V_(R16G16B16_SSCALED, 16_16_16_SINT,  NONE, WZYX),
+        V_(R16G16B16_FLOAT,   16_16_16_FLOAT, NONE, WZYX),
+        /* 64-bit */
+        VT(R16G16B16A16_UNORM,   16_16_16_16_UNORM, NONE,               WZYX),
+        VT(R16G16B16A16_SNORM,   16_16_16_16_SNORM, NONE,               WZYX),
+        VT(R16G16B16A16_UINT,    16_16_16_16_UINT,  R16G16B16A16_UINT,  WZYX),
+        _T(R16G16B16X16_UINT,    16_16_16_16_UINT,  R16G16B16A16_UINT,  WZYX),
+        VT(R16G16B16A16_SINT,    16_16_16_16_SINT,  R16G16B16A16_SINT,  WZYX),
+        _T(R16G16B16X16_SINT,    16_16_16_16_SINT,  R16G16B16A16_SINT,  WZYX),
+        V_(R16G16B16A16_USCALED, 16_16_16_16_UINT,  NONE,               WZYX),
+        V_(R16G16B16A16_SSCALED, 16_16_16_16_SINT,  NONE,               WZYX),
+        VT(R16G16B16A16_FLOAT,   16_16_16_16_FLOAT, R16G16B16A16_FLOAT, WZYX),
+        _T(R16G16B16X16_FLOAT,   16_16_16_16_FLOAT, R16G16B16A16_FLOAT, WZYX),
+        VT(R32G32_UINT,    32_32_UINT,  R32G32_UINT, WZYX),
+        VT(R32G32_SINT,    32_32_SINT,  R32G32_SINT, WZYX),
+        V_(R32G32_USCALED, 32_32_UINT,  NONE,        WZYX),
+        V_(R32G32_SSCALED, 32_32_SINT,  NONE,        WZYX),
+        VT(R32G32_FLOAT,   32_32_FLOAT, R32G32_FLOAT,WZYX),
+        V_(R32G32_FIXED,   32_32_FIXED, NONE,        WZYX),
+        _T(L32A32_UINT,    32_32_UINT,  NONE,        WZYX),
+        _T(L32A32_SINT,    32_32_SINT,  NONE,        WZYX),
+        /* 96-bit */
+        V_(R32G32B32_UINT,    32_32_32_UINT,  NONE, WZYX),
+        V_(R32G32B32_SINT,    32_32_32_SINT,  NONE, WZYX),
+        V_(R32G32B32_USCALED, 32_32_32_UINT,  NONE, WZYX),
+        V_(R32G32B32_SSCALED, 32_32_32_SINT,  NONE, WZYX),
+        V_(R32G32B32_FLOAT,   32_32_32_FLOAT, NONE, WZYX),
+        V_(R32G32B32_FIXED,   32_32_32_FIXED, NONE, WZYX),
+        /* 128-bit */
+        VT(R32G32B32A32_UINT,    32_32_32_32_UINT,  R32G32B32A32_UINT,  WZYX),
+        _T(R32G32B32X32_UINT,    32_32_32_32_UINT,  R32G32B32A32_UINT,  WZYX),
+        VT(R32G32B32A32_SINT,    32_32_32_32_SINT,  R32G32B32A32_SINT,  WZYX),
+        _T(R32G32B32X32_SINT,    32_32_32_32_SINT,  R32G32B32A32_SINT,  WZYX),
+        V_(R32G32B32A32_USCALED, 32_32_32_32_UINT,  NONE,               WZYX),
+        V_(R32G32B32A32_SSCALED, 32_32_32_32_SINT,  NONE,               WZYX),
+        VT(R32G32B32A32_FLOAT,   32_32_32_32_FLOAT, R32G32B32A32_FLOAT, WZYX),
+        _T(R32G32B32X32_FLOAT,   32_32_32_32_FLOAT, R32G32B32A32_FLOAT, WZYX),
+        V_(R32G32B32A32_FIXED,   32_32_32_32_FIXED, NONE,               WZYX),
+        /* compressed */
+        _T(ETC1_RGB8, ETC1, NONE, WZYX),
+        _T(ETC2_RGB8, ETC2_RGB8, NONE, WZYX),
+        _T(ETC2_SRGB8, ETC2_RGB8, NONE, WZYX),
+        _T(ETC2_RGB8A1, ETC2_RGB8A1, NONE, WZYX),
+        _T(ETC2_SRGB8A1, ETC2_RGB8A1, NONE, WZYX),
+        _T(ETC2_RGBA8, ETC2_RGBA8, NONE, WZYX),
+        _T(ETC2_SRGBA8, ETC2_RGBA8, NONE, WZYX),
+        _T(ETC2_R11_UNORM, ETC2_R11_UNORM, NONE, WZYX),
+        _T(ETC2_R11_SNORM, ETC2_R11_SNORM, NONE, WZYX),
+        _T(ETC2_RG11_UNORM, ETC2_RG11_UNORM, NONE, WZYX),
+        _T(ETC2_RG11_SNORM, ETC2_RG11_SNORM, NONE, WZYX),
+};
+enum a3xx_vtx_fmt
+fd3_pipe2vtx(enum pipe_format format)
+{
+        if (!formats[format].present)
+                return ~0;
+        return formats[format].vtx;
+}
+enum a3xx_tex_fmt
+fd3_pipe2tex(enum pipe_format format)
+{
+        if (!formats[format].present)
+                return ~0;
+        return formats[format].tex;
+}
+enum a3xx_color_fmt
+fd3_pipe2color(enum pipe_format format)
+{
+        if (!formats[format].present)
+                return ~0;
+        return formats[format].rb;
+}
+enum a3xx_color_swap
+fd3_pipe2swap(enum pipe_format format)
+{
+        if (!formats[format].present)
+                return WZYX;
+        return formats[format].swap;
+}
+enum a3xx_tex_fetchsize
+fd3_pipe2fetchsize(enum pipe_format format)
+{
+        if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
+                format = PIPE_FORMAT_Z32_FLOAT;
+        switch (util_format_get_blocksizebits(format)) {
+        case 8: return TFETCH_1_BYTE;
+        case 16: return TFETCH_2_BYTE;
+        case 32: return TFETCH_4_BYTE;
+        case 64: return TFETCH_8_BYTE;
+        case 128: return TFETCH_16_BYTE;
+        default:
+                debug_printf("Unknown block size for format %s: %d\n",
+                                         util_format_name(format),
+                                         util_format_get_blocksizebits(format));
+                return TFETCH_DISABLE;
+        }
+}
+/* we need to special case a bit the depth/stencil restore, because we are
+ * using the texture sampler to blit into the depth/stencil buffer, *not*
+ * into a color buffer.  Otherwise fd3_tex_swiz() will do the wrong thing,
+ * as it is assuming that you are sampling into normal render target..
+ */
+enum pipe_format
+fd3_gmem_restore_format(enum pipe_format format)
+{
+        switch (format) {
+        case PIPE_FORMAT_Z24X8_UNORM:
+        case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+                return PIPE_FORMAT_R8G8B8A8_UNORM;
+        case PIPE_FORMAT_Z16_UNORM:
+                return PIPE_FORMAT_R8G8_UNORM;
+        case PIPE_FORMAT_S8_UINT:
+                return PIPE_FORMAT_R8_UNORM;
+        default:
+                return format;
+        }
+}
+enum a3xx_color_fmt
+fd3_fs_output_format(enum pipe_format format)
+{
+        if (util_format_is_srgb(format))
+                return RB_R16G16B16A16_FLOAT;
+        switch (format) {
+        case PIPE_FORMAT_R16_FLOAT:
+        case PIPE_FORMAT_R16G16_FLOAT:
+        case PIPE_FORMAT_R11G11B10_FLOAT:
+                return RB_R16G16B16A16_FLOAT;
+        default:
+                return fd3_pipe2color(format);
+        }
+}
+static inline enum a3xx_tex_swiz
+tex_swiz(unsigned swiz)
+{
+        switch (swiz) {
+        default:
+        case PIPE_SWIZZLE_RED:   return A3XX_TEX_X;
+        case PIPE_SWIZZLE_GREEN: return A3XX_TEX_Y;
+        case PIPE_SWIZZLE_BLUE:  return A3XX_TEX_Z;
+        case PIPE_SWIZZLE_ALPHA: return A3XX_TEX_W;
+        case PIPE_SWIZZLE_ZERO:  return A3XX_TEX_ZERO;
+        case PIPE_SWIZZLE_ONE:   return A3XX_TEX_ONE;
+        }
+}
+uint32_t
+fd3_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g,
+                unsigned swizzle_b, unsigned swizzle_a)
+{
+        const struct util_format_description *desc =
+                        util_format_description(format);
+        unsigned char swiz[4] = {
+                        swizzle_r, swizzle_g, swizzle_b, swizzle_a,
+        }, rswiz[4];
+        util_format_compose_swizzles(desc->swizzle, swiz, rswiz);
+        return A3XX_TEX_CONST_0_SWIZ_X(tex_swiz(rswiz[0])) |
+                        A3XX_TEX_CONST_0_SWIZ_Y(tex_swiz(rswiz[1])) |
+                        A3XX_TEX_CONST_0_SWIZ_Z(tex_swiz(rswiz[2])) |
+                        A3XX_TEX_CONST_0_SWIZ_W(tex_swiz(rswiz[3]));
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_format.h
 ,0 → 1,67
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+#ifndef FD3_FORMAT_H_
+#define FD3_FORMAT_H_
+#include "util/u_format.h"
+#include "freedreno_util.h"
+#include "a3xx.xml.h"
+enum a3xx_vtx_fmt fd3_pipe2vtx(enum pipe_format format);
+enum a3xx_tex_fmt fd3_pipe2tex(enum pipe_format format);
+enum a3xx_tex_fetchsize fd3_pipe2fetchsize(enum pipe_format format);
+enum a3xx_color_fmt fd3_pipe2color(enum pipe_format format);
+enum pipe_format fd3_gmem_restore_format(enum pipe_format format);
+enum a3xx_color_fmt fd3_fs_output_format(enum pipe_format format);
+enum a3xx_color_swap fd3_pipe2swap(enum pipe_format format);
+uint32_t fd3_tex_swiz(enum pipe_format format, unsigned swizzle_r,
+                unsigned swizzle_g, unsigned swizzle_b, unsigned swizzle_a);
+static INLINE bool
+fd3_half_precision(const struct pipe_surface *surface)
+{
+        enum pipe_format format;
+        if (!surface)
+                return true;
+        format = surface->format;
+        /* colors are provided in consts, which go through cov.f32f16, which will
+         * break these values
+         */
+        if (util_format_is_pure_integer(format))
+                return false;
+        /* avoid losing precision on 32-bit float formats */
+        if (util_format_is_float(format) &&
+                util_format_get_component_bits(format, UTIL_FORMAT_COLORSPACE_RGB, 0) == 32)
+                return false;
+        return true;
+}
+#endif /* FD3_FORMAT_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
 ,0 → 1,1057
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_state.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "util/u_inlines.h"
+#include "util/u_format.h"
+#include "freedreno_draw.h"
+#include "freedreno_state.h"
+#include "freedreno_resource.h"
+#include "fd3_gmem.h"
+#include "fd3_context.h"
+#include "fd3_emit.h"
+#include "fd3_program.h"
+#include "fd3_format.h"
+#include "fd3_zsa.h"
+static void
+emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
+                 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w,
+                 bool decode_srgb)
+{
+        enum a3xx_tile_mode tile_mode;
+        unsigned i;
+        if (bin_w) {
+                tile_mode = TILE_32X32;
+        } else {
+                tile_mode = LINEAR;
+        }
+        for (i = 0; i < 4; i++) {
+                enum pipe_format pformat = 0;
+                enum a3xx_color_fmt format = 0;
+                enum a3xx_color_swap swap = WZYX;
+                bool srgb = false;
+                struct fd_resource *rsc = NULL;
+                struct fd_resource_slice *slice = NULL;
+                uint32_t stride = 0;
+                uint32_t base = 0;
+                uint32_t offset = 0;
+                if ((i < nr_bufs) && bufs[i]) {
+                        struct pipe_surface *psurf = bufs[i];
+                        rsc = fd_resource(psurf->texture);
+                        pformat = psurf->format;
+                        /* In case we're drawing to Z32F_S8, the "color" actually goes to
+                         * the stencil
+                         */
+                        if (rsc->stencil) {
+                                rsc = rsc->stencil;
+                                pformat = rsc->base.b.format;
+                                bases++;
+                        }
+                        slice = fd_resource_slice(rsc, psurf->u.tex.level);
+                        format = fd3_pipe2color(pformat);
+                        swap = fd3_pipe2swap(pformat);
+                        if (decode_srgb)
+                                srgb = util_format_is_srgb(pformat);
+                        else
+                                pformat = util_format_linear(pformat);
+                        debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
+                        offset = fd_resource_offset(rsc, psurf->u.tex.level,
+                                        psurf->u.tex.first_layer);
+                        if (bin_w) {
+                                stride = bin_w * rsc->cpp;
+                                if (bases) {
+                                        base = bases[i];
+                                }
+                        } else {
+                                stride = slice->pitch * rsc->cpp;
+                        }
+                } else if (i < nr_bufs && bases) {
+                        base = bases[i];
+                }
+                OUT_PKT0(ring, REG_A3XX_RB_MRT_BUF_INFO(i), 2);
+                OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
+                                A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
+                                A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
+                                A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
+                                COND(srgb, A3XX_RB_MRT_BUF_INFO_COLOR_SRGB));
+                if (bin_w || (i >= nr_bufs) || !bufs[i]) {
+                        OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
+                } else {
+                        OUT_RELOCW(ring, rsc->bo, offset, 0, -1);
+                }
+                OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
+                OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
+                                                        A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(
+                                                                        fd3_fs_output_format(pformat))));
+        }
+}
+static bool
+use_hw_binning(struct fd_context *ctx)
+{
+        struct fd_gmem_stateobj *gmem = &ctx->gmem;
+        /* workaround: combining scissor optimization and hw binning
+         * seems problematic.  Seems like we end up with a mismatch
+         * between binning pass and rendering pass, wrt. where the hw
+         * thinks the vertices belong.  And the blob driver doesn't
+         * seem to implement anything like scissor optimization, so
+         * not entirely sure what I might be missing.
+         *
+         * But scissor optimization is mainly for window managers,
+         * which don't have many vertices (and therefore doesn't
+         * benefit much from binning pass).
+         *
+         * So for now just disable binning if scissor optimization is
+         * used.
+         */
+        if (gmem->minx || gmem->miny)
+                return false;
+        return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
+}
+/* workaround for (hlsq?) lockup with hw binning on a3xx patchlevel 0 */
+static void update_vsc_pipe(struct fd_context *ctx);
+static void
+emit_binning_workaround(struct fd_context *ctx)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd_gmem_stateobj *gmem = &ctx->gmem;
+        struct fd_ringbuffer *ring = ctx->ring;
+        struct fd3_emit emit = {
+                        .vtx = &fd3_ctx->solid_vbuf_state,
+                        .prog = &ctx->solid_prog,
+                        .key = {
+                                .half_precision = true,
+                        },
+        };
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
+                        A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                        A3XX_RB_MODE_CONTROL_MRT(0));
+        OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
+                        A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
+                        A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
+        OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
+        OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
+                        A3XX_RB_COPY_CONTROL_MODE(0) |
+                        A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
+        OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1);  /* RB_COPY_DEST_BASE */
+        OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
+        OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
+                        A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
+                        A3XX_RB_COPY_DEST_INFO_SWAP(WZYX) |
+                        A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
+                        A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
+        fd3_program_emit(ring, &emit, 0, NULL);
+        fd3_emit_vertex_bufs(ring, &emit);
+        OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 4);
+        OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
+                        A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
+                        A3XX_HLSQ_CONTROL_0_REG_RESERVED2 |
+                        A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
+        OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
+                        A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
+        OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
+        OUT_RING(ring, 0); /* HLSQ_CONTROL_3_REG */
+        OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG, 1);
+        OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0x20) |
+                        A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0x20));
+        OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
+                        A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
+                        A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
+        OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
+        OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
+                        A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
+                        A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
+        OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
+        OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
+        OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
+        OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
+        OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
+        OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
+        OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
+        OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
+                        A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(1));
+        OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(0) |
+                        A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(1));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
+        fd_wfi(ctx, ring);
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
+        OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
+                        A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE |
+                        A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE |
+                        A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE |
+                        A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE);
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
+        OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
+                        A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
+        OUT_PKT3(ring, CP_DRAW_INDX_2, 5);
+        OUT_RING(ring, 0x00000000);   /* viz query info. */
+        OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE,
+                                                INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0));
+        OUT_RING(ring, 2);            /* NumIndices */
+        OUT_RING(ring, 2);
+        OUT_RING(ring, 1);
+        fd_reset_wfi(ctx);
+        OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
+        OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
+        OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
+        OUT_RING(ring, 0x00000000);
+        fd_wfi(ctx, ring);
+        OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
+        OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
+                        A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
+        OUT_RING(ring, 0x00000000);
+}
+/* transfer from gmem to system memory (ie. normal RAM) */
+static void
+emit_gmem2mem_surf(struct fd_context *ctx,
+                                   enum adreno_rb_copy_control_mode mode,
+                                   bool stencil,
+                                   uint32_t base, struct pipe_surface *psurf)
+{
+        struct fd_ringbuffer *ring = ctx->ring;
+        struct fd_resource *rsc = fd_resource(psurf->texture);
+        enum pipe_format format = psurf->format;
+        if (stencil) {
+                rsc = rsc->stencil;
+                format = rsc->base.b.format;
+        }
+        struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
+        uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
+                        psurf->u.tex.first_layer);
+        debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
+        OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
+        OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
+                        A3XX_RB_COPY_CONTROL_MODE(mode) |
+                        A3XX_RB_COPY_CONTROL_GMEM_BASE(base) |
+                        COND(format == PIPE_FORMAT_Z32_FLOAT ||
+                                 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
+                                 A3XX_RB_COPY_CONTROL_UNK12));
+        OUT_RELOCW(ring, rsc->bo, offset, 0, -1);    /* RB_COPY_DEST_BASE */
+        OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
+        OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
+                        A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
+                        A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
+                        A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
+                        A3XX_RB_COPY_DEST_INFO_SWAP(fd3_pipe2swap(format)));
+        fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+                        DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
+}
+static void
+fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd_ringbuffer *ring = ctx->ring;
+        struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+        struct fd3_emit emit = {
+                        .vtx = &fd3_ctx->solid_vbuf_state,
+                        .prog = &ctx->solid_prog,
+                        .key = {
+                                .half_precision = true,
+                        },
+        };
+        int i;
+        OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
+        OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
+                        A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
+                        A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
+        OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
+        OUT_RING(ring, 0xff000000 |
+                        A3XX_RB_STENCILREFMASK_STENCILREF(0) |
+                        A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
+                        A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
+        OUT_RING(ring, 0xff000000 |
+                        A3XX_RB_STENCILREFMASK_STENCILREF(0) |
+                        A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
+                        A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
+        OUT_RING(ring, 0x00000000);   /* GRAS_CL_CLIP_CNTL */
+        fd_wfi(ctx, ring);
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
+                        A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                        A3XX_RB_MODE_CONTROL_MRT(0));
+        OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
+                        A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
+                        A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
+                        A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
+        OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
+        OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
+        OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
+                        A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
+        OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
+                        A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
+        OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
+        OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
+        OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
+        OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
+        OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
+        fd3_program_emit(ring, &emit, 0, NULL);
+        fd3_emit_vertex_bufs(ring, &emit);
+        if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
+                struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
+                if (!rsc->stencil || ctx->resolve & FD_BUFFER_DEPTH)
+                        emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, false,
+                                                           ctx->gmem.zsbuf_base[0], pfb->zsbuf);
+                if (rsc->stencil && ctx->resolve & FD_BUFFER_STENCIL)
+                        emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, true,
+                                                           ctx->gmem.zsbuf_base[1], pfb->zsbuf);
+        }
+        if (ctx->resolve & FD_BUFFER_COLOR) {
+                for (i = 0; i < pfb->nr_cbufs; i++) {
+                        if (!pfb->cbufs[i])
+                                continue;
+                        if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
+                                continue;
+                        emit_gmem2mem_surf(ctx, RB_COPY_RESOLVE, false,
+                                                           ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
+                }
+        }
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                        A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+}
+/* transfer from system memory to gmem */
+static void
+emit_mem2gmem_surf(struct fd_context *ctx, uint32_t bases[],
+                struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
+{
+        struct fd_ringbuffer *ring = ctx->ring;
+        struct pipe_surface *zsbufs[2];
+        assert(bufs > 0);
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                                   A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                                   A3XX_RB_MODE_CONTROL_MRT(bufs - 1));
+        emit_mrt(ring, bufs, psurf, bases, bin_w, false);
+        if (psurf[0] && (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT ||
+                                         psurf[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
+                /* Depth is stored as unorm in gmem, so we have to write it in using a
+                 * special blit shader which writes depth.
+                 */
+                OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
+                OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
+                                                A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
+                                                A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
+                                                A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
+                                                A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
+                OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
+                OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
+                                 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
+                OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * ctx->gmem.bin_w));
+                if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
+                        OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
+                        OUT_RING(ring, 0);
+                } else {
+                        /* The gmem_restore_tex logic will put the first buffer's stencil
+                         * as color. Supply it with the proper information to make that
+                         * happen.
+                         */
+                        zsbufs[0] = zsbufs[1] = psurf[0];
+                        psurf = zsbufs;
+                        bufs = 2;
+                }
+        } else {
+                OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
+                OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_MRT(bufs - 1));
+        }
+        fd3_emit_gmem_restore_tex(ring, psurf, bufs);
+        fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+                        DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
+}
+static void
+fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd_gmem_stateobj *gmem = &ctx->gmem;
+        struct fd_ringbuffer *ring = ctx->ring;
+        struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+        struct fd3_emit emit = {
+                        .vtx = &fd3_ctx->blit_vbuf_state,
+                        .sprite_coord_enable = 1,
+                        /* NOTE: They all use the same VP, this is for vtx bufs. */
+                        .prog = &ctx->blit_prog[0],
+                        .key = {
+                                .half_precision = (fd3_half_precision(pfb->cbufs[0]) &&
+                                                                   fd3_half_precision(pfb->cbufs[1]) &&
+                                                                   fd3_half_precision(pfb->cbufs[2]) &&
+                                                                   fd3_half_precision(pfb->cbufs[3]))
+                        },
+        };
+        float x0, y0, x1, y1;
+        unsigned bin_w = tile->bin_w;
+        unsigned bin_h = tile->bin_h;
+        unsigned i;
+        /* write texture coordinates to vertexbuf: */
+        x0 = ((float)tile->xoff) / ((float)pfb->width);
+        x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
+        y0 = ((float)tile->yoff) / ((float)pfb->height);
+        y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
+        OUT_PKT3(ring, CP_MEM_WRITE, 5);
+        OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
+        OUT_RING(ring, fui(x0));
+        OUT_RING(ring, fui(y0));
+        OUT_RING(ring, fui(x1));
+        OUT_RING(ring, fui(y1));
+        for (i = 0; i < 4; i++) {
+                OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
+                OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
+                                A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
+                                A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
+                OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
+                OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
+                                A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
+                                A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
+        }
+        OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
+                        A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
+        fd_wfi(ctx, ring);
+        OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
+        OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
+        OUT_RING(ring, 0);
+        OUT_RING(ring, 0);
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
+        OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);   /* GRAS_CL_CLIP_CNTL */
+        fd_wfi(ctx, ring);
+        OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h/2.0 - 0.5));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h/2.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
+        OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
+        OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
+                        A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
+        OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
+                        A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
+        OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
+        OUT_RING(ring, 0x2 |
+                        A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
+                        A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
+                        A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
+                        A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
+        OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
+        OUT_RING(ring, 0); /* RB_STENCIL_INFO */
+        OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
+        OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
+        OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(2) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
+                        A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
+        OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
+        OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
+        OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
+        OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
+        OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
+        fd3_emit_vertex_bufs(ring, &emit);
+        /* for gmem pitch/base calculations, we need to use the non-
+         * truncated tile sizes:
+         */
+        bin_w = gmem->bin_w;
+        bin_h = gmem->bin_h;
+        if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
+                emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
+                fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
+                emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
+        }
+        if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
+                if (pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
+                        pfb->zsbuf->format != PIPE_FORMAT_Z32_FLOAT) {
+                        /* Non-float can use a regular color write. It's split over 8-bit
+                         * components, so half precision is always sufficient.
+                         */
+                        emit.prog = &ctx->blit_prog[0];
+                        emit.key.half_precision = true;
+                } else {
+                        /* Float depth needs special blit shader that writes depth */
+                        if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
+                                emit.prog = &ctx->blit_z;
+                        else
+                                emit.prog = &ctx->blit_zs;
+                        emit.key.half_precision = false;
+                }
+                fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
+                emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
+        }
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                                   A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                                   A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
+}
+static void
+patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
+{
+        unsigned i;
+        for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
+                struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
+                *patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
+        }
+        util_dynarray_resize(&ctx->draw_patches, 0);
+}
+static void
+patch_rbrc(struct fd_context *ctx, uint32_t val)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        unsigned i;
+        for (i = 0; i < fd_patch_num_elements(&fd3_ctx->rbrc_patches); i++) {
+                struct fd_cs_patch *patch = fd_patch_element(&fd3_ctx->rbrc_patches, i);
+                *patch->cs = patch->val | val;
+        }
+        util_dynarray_resize(&fd3_ctx->rbrc_patches, 0);
+}
+/* for rendering directly to system memory: */
+static void
+fd3_emit_sysmem_prep(struct fd_context *ctx)
+{
+        struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+        struct fd_ringbuffer *ring = ctx->ring;
+        uint32_t i, pitch = 0;
+        for (i = 0; i < pfb->nr_cbufs; i++) {
+                struct pipe_surface *psurf = pfb->cbufs[i];
+                if (!psurf)
+                        continue;
+                pitch = fd_resource(psurf->texture)->slices[psurf->u.tex.level].pitch;
+        }
+        fd3_emit_restore(ctx);
+        OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
+        OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
+                        A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
+        emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
+        /* setup scissor/offset for current tile: */
+        OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
+        OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
+                        A3XX_RB_WINDOW_OFFSET_Y(0));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_RB_MODE_CONTROL_GMEM_BYPASS |
+                        A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                        A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
+        patch_draws(ctx, IGNORE_VISIBILITY);
+        patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
+}
+static void
+update_vsc_pipe(struct fd_context *ctx)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd_ringbuffer *ring = ctx->ring;
+        int i;
+        OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
+        OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
+        for (i = 0; i < 8; i++) {
+                struct fd_vsc_pipe *pipe = &ctx->pipe[i];
+                if (!pipe->bo) {
+                        pipe->bo = fd_bo_new(ctx->dev, 0x40000,
+                                        DRM_FREEDRENO_GEM_TYPE_KMEM);
+                }
+                OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
+                OUT_RING(ring, A3XX_VSC_PIPE_CONFIG_X(pipe->x) |
+                                A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
+                                A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
+                                A3XX_VSC_PIPE_CONFIG_H(pipe->h));
+                OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE[i].DATA_ADDRESS */
+                OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
+        }
+}
+static void
+emit_binning_pass(struct fd_context *ctx)
+{
+        struct fd_gmem_stateobj *gmem = &ctx->gmem;
+        struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+        struct fd_ringbuffer *ring = ctx->ring;
+        int i;
+        uint32_t x1 = gmem->minx;
+        uint32_t y1 = gmem->miny;
+        uint32_t x2 = gmem->minx + gmem->width - 1;
+        uint32_t y2 = gmem->miny + gmem->height - 1;
+        if (ctx->screen->gpu_id == 320) {
+                emit_binning_workaround(ctx);
+                fd_wfi(ctx, ring);
+                OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
+                OUT_RING(ring, 0x00007fff);
+        }
+        OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
+        OUT_RING(ring, A3XX_VSC_BIN_CONTROL_BINNING_ENABLE);
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+        OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
+        OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
+                        A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
+        OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
+                        A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
+                        A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
+        /* setup scissor/offset for whole screen: */
+        OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
+        OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(x1) |
+                        A3XX_RB_WINDOW_OFFSET_Y(y1));
+        OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE);
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_TILING_PASS) |
+                        A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                        A3XX_RB_MODE_CONTROL_MRT(0));
+        for (i = 0; i < 4; i++) {
+                OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
+                OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
+                                A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_DISABLE) |
+                                A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0));
+        }
+        OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
+        OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(1) |
+                        A3XX_PC_VSTREAM_CONTROL_N(0));
+        /* emit IB to binning drawcmds: */
+        OUT_IB(ring, ctx->binning_start, ctx->binning_end);
+        fd_reset_wfi(ctx);
+        fd_wfi(ctx, ring);
+        /* and then put stuff back the way it was: */
+        OUT_PKT0(ring, REG_A3XX_VSC_BIN_CONTROL, 1);
+        OUT_RING(ring, 0x00000000);
+        OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
+        OUT_RING(ring, A3XX_SP_SP_CTRL_REG_RESOLVE |
+                        A3XX_SP_SP_CTRL_REG_CONSTMODE(1) |
+                        A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
+                        A3XX_SP_SP_CTRL_REG_L0MODE(0));
+        OUT_PKT0(ring, REG_A3XX_RB_LRZ_VSC_CONTROL, 1);
+        OUT_RING(ring, 0x00000000);
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
+        OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+                        A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                        A3XX_RB_MODE_CONTROL_MRT(pfb->nr_cbufs - 1));
+        OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
+                        A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
+                        A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
+        fd_event_write(ctx, ring, CACHE_FLUSH);
+        fd_wfi(ctx, ring);
+        if (ctx->screen->gpu_id == 320) {
+                /* dummy-draw workaround: */
+                OUT_PKT3(ring, CP_DRAW_INDX, 3);
+                OUT_RING(ring, 0x00000000);
+                OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
+                                                        INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
+                OUT_RING(ring, 0);             /* NumIndices */
+                fd_reset_wfi(ctx);
+        }
+        OUT_PKT3(ring, CP_NOP, 4);
+        OUT_RING(ring, 0x00000000);
+        OUT_RING(ring, 0x00000000);
+        OUT_RING(ring, 0x00000000);
+        OUT_RING(ring, 0x00000000);
+        fd_wfi(ctx, ring);
+        if (ctx->screen->gpu_id == 320) {
+                emit_binning_workaround(ctx);
+        }
+}
+/* before first tile */
+static void
+fd3_emit_tile_init(struct fd_context *ctx)
+{
+        struct fd_ringbuffer *ring = ctx->ring;
+        struct fd_gmem_stateobj *gmem = &ctx->gmem;
+        uint32_t rb_render_control;
+        fd3_emit_restore(ctx);
+        /* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
+         * at the right and bottom edge tiles
+         */
+        OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
+        OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
+                        A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
+        update_vsc_pipe(ctx);
+        if (use_hw_binning(ctx)) {
+                /* mark the end of the binning cmds: */
+                fd_ringmarker_mark(ctx->binning_end);
+                /* emit hw binning pass: */
+                emit_binning_pass(ctx);
+                patch_draws(ctx, USE_VISIBILITY);
+        } else {
+                patch_draws(ctx, IGNORE_VISIBILITY);
+        }
+        rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
+                        A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
+        patch_rbrc(ctx, rb_render_control);
+}
+/* before mem2gmem */
+static void
+fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
+{
+        struct fd_ringbuffer *ring = ctx->ring;
+        struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+        if (ctx->needs_rb_fbd) {
+                fd_wfi(ctx, ring);
+                OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
+                OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
+                                A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
+                ctx->needs_rb_fbd = false;
+        }
+        OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+                        A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE |
+                        A3XX_RB_MODE_CONTROL_MRT(MAX2(1, pfb->nr_cbufs) - 1));
+}
+/* before IB to rendering cmds: */
+static void
+fd3_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
+{
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd_ringbuffer *ring = ctx->ring;
+        struct fd_gmem_stateobj *gmem = &ctx->gmem;
+        struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+        uint32_t x1 = tile->xoff;
+        uint32_t y1 = tile->yoff;
+        uint32_t x2 = tile->xoff + tile->bin_w - 1;
+        uint32_t y2 = tile->yoff + tile->bin_h - 1;
+        uint32_t reg;
+        OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
+        reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
+        if (pfb->zsbuf) {
+                reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
+        }
+        OUT_RING(ring, reg);
+        if (pfb->zsbuf) {
+                struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
+                OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->cpp * gmem->bin_w));
+                if (rsc->stencil) {
+                        OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
+                        OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
+                        OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
+                }
+        } else {
+                OUT_RING(ring, 0x00000000);
+        }
+        if (use_hw_binning(ctx)) {
+                struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
+                assert(pipe->w * pipe->h);
+                fd_event_write(ctx, ring, HLSQ_FLUSH);
+                fd_wfi(ctx, ring);
+                OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
+                OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
+                                A3XX_PC_VSTREAM_CONTROL_N(tile->n));
+                OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
+                OUT_RELOC(ring, pipe->bo, 0, 0, 0);    /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
+                OUT_RELOC(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
+                                (tile->p * 4), 0, 0);
+        } else {
+                OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
+                OUT_RING(ring, 0x00000000);
+        }
+        OUT_PKT3(ring, CP_SET_BIN, 3);
+        OUT_RING(ring, 0x00000000);
+        OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
+        OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
+        emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
+        /* setup scissor/offset for current tile: */
+        OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
+        OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(tile->xoff) |
+                        A3XX_RB_WINDOW_OFFSET_Y(tile->yoff));
+        OUT_PKT0(ring, REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
+        OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
+                        A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
+}
+void
+fd3_gmem_init(struct pipe_context *pctx)
+{
+        struct fd_context *ctx = fd_context(pctx);
+        ctx->emit_sysmem_prep = fd3_emit_sysmem_prep;
+        ctx->emit_tile_init = fd3_emit_tile_init;
+        ctx->emit_tile_prep = fd3_emit_tile_prep;
+        ctx->emit_tile_mem2gmem = fd3_emit_tile_mem2gmem;
+        ctx->emit_tile_renderprep = fd3_emit_tile_renderprep;
+        ctx->emit_tile_gmem2mem = fd3_emit_tile_gmem2mem;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_gmem.h
 ,0 → 1,36
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_GMEM_H_
+#define FD3_GMEM_H_
+#include "pipe/p_context.h"
+void fd3_gmem_init(struct pipe_context *pctx);
+#endif /* FD3_GMEM_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_program.c
 ,0 → 1,481
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_state.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "util/u_inlines.h"
+#include "util/u_format.h"
+#include "freedreno_program.h"
+#include "fd3_program.h"
+#include "fd3_emit.h"
+#include "fd3_texture.h"
+#include "fd3_format.h"
+static void
+delete_shader_stateobj(struct fd3_shader_stateobj *so)
+{
+        ir3_shader_destroy(so->shader);
+        free(so);
+}
+static struct fd3_shader_stateobj *
+create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
+                enum shader_t type)
+{
+        struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
+        so->shader = ir3_shader_create(pctx, cso->tokens, type);
+        return so;
+}
+static void *
+fd3_fp_state_create(struct pipe_context *pctx,
+                const struct pipe_shader_state *cso)
+{
+        return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
+}
+static void
+fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
+{
+        struct fd3_shader_stateobj *so = hwcso;
+        delete_shader_stateobj(so);
+}
+static void *
+fd3_vp_state_create(struct pipe_context *pctx,
+                const struct pipe_shader_state *cso)
+{
+        return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
+}
+static void
+fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
+{
+        struct fd3_shader_stateobj *so = hwcso;
+        delete_shader_stateobj(so);
+}
+static void
+emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
+{
+        const struct ir3_info *si = &so->info;
+        enum adreno_state_block sb;
+        enum adreno_state_src src;
+        uint32_t i, sz, *bin;
+        if (so->type == SHADER_VERTEX) {
+                sb = SB_VERT_SHADER;
+        } else {
+                sb = SB_FRAG_SHADER;
+        }
+        if (fd_mesa_debug & FD_DBG_DIRECT) {
+                sz = si->sizedwords;
+                src = SS_DIRECT;
+                bin = fd_bo_map(so->bo);
+        } else {
+                sz = 0;
+                src = SS_INDIRECT;
+                bin = NULL;
+        }
+        OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
+        OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
+                        CP_LOAD_STATE_0_STATE_SRC(src) |
+                        CP_LOAD_STATE_0_STATE_BLOCK(sb) |
+                        CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
+        if (bin) {
+                OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
+                                CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
+        } else {
+                OUT_RELOC(ring, so->bo, 0,
+                                CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
+        }
+        for (i = 0; i < sz; i++) {
+                OUT_RING(ring, bin[i]);
+        }
+}
+void
+fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
+                                 int nr, struct pipe_surface **bufs)
+{
+        const struct ir3_shader_variant *vp, *fp;
+        const struct ir3_info *vsi, *fsi;
+        enum a3xx_instrbuffermode fpbuffer, vpbuffer;
+        uint32_t fpbuffersz, vpbuffersz, fsoff;
+        uint32_t pos_regid, posz_regid, psize_regid, color_regid[4] = {0};
+        int constmode;
+        int i, j, k;
+        vp = fd3_emit_get_vp(emit);
+        if (emit->key.binning_pass) {
+                /* use dummy stateobj to simplify binning vs non-binning: */
+                static const struct ir3_shader_variant binning_fp = {};
+                fp = &binning_fp;
+        } else {
+                fp = fd3_emit_get_fp(emit);
+        }
+        vsi = &vp->info;
+        fsi = &fp->info;
+        fpbuffer = BUFFER;
+        vpbuffer = BUFFER;
+        fpbuffersz = fp->instrlen;
+        vpbuffersz = vp->instrlen;
+        /*
+         * Decide whether to use BUFFER or CACHE mode for VS and FS.  It
+         * appears like 256 is the hard limit, but when the combined size
+         * exceeds 128 then blob will try to keep FS in BUFFER mode and
+         * switch to CACHE for VS until VS is too large.  The blob seems
+         * to switch FS out of BUFFER mode at slightly under 128.  But
+         * a bit fuzzy on the decision tree, so use slightly conservative
+         * limits.
+         *
+         * TODO check if these thresholds for BUFFER vs CACHE mode are the
+         *      same for all a3xx or whether we need to consider the gpuid
+         */
+        if ((fpbuffersz + vpbuffersz) > 128) {
+                if (fpbuffersz < 112) {
+                        /* FP:BUFFER   VP:CACHE  */
+                        vpbuffer = CACHE;
+                        vpbuffersz = 256 - fpbuffersz;
+                } else if (vpbuffersz < 112) {
+                        /* FP:CACHE    VP:BUFFER */
+                        fpbuffer = CACHE;
+                        fpbuffersz = 256 - vpbuffersz;
+                } else {
+                        /* FP:CACHE    VP:CACHE  */
+                        vpbuffer = fpbuffer = CACHE;
+                        vpbuffersz = fpbuffersz = 192;
+                }
+        }
+        if (fpbuffer == BUFFER) {
+                fsoff = 128 - fpbuffersz;
+        } else {
+                fsoff = 256 - fpbuffersz;
+        }
+        /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
+        constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
+        pos_regid = ir3_find_output_regid(vp,
+                ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
+        posz_regid = ir3_find_output_regid(fp,
+                ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
+        psize_regid = ir3_find_output_regid(vp,
+                ir3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
+        if (fp->color0_mrt) {
+                color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
+                        ir3_find_output_regid(fp, ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
+        } else {
+                for (int i = 0; i < fp->outputs_count; i++) {
+                        ir3_semantic sem = fp->outputs[i].semantic;
+                        unsigned idx = sem2idx(sem);
+                        if (sem2name(sem) != TGSI_SEMANTIC_COLOR)
+                                continue;
+                        assert(idx < 4);
+                        color_regid[idx] = fp->outputs[i].regid;
+                }
+        }
+        /* adjust regids for alpha output formats. there is no alpha render
+         * format, so it's just treated like red
+         */
+        for (i = 0; i < nr; i++)
+                if (util_format_is_alpha(pipe_surface_format(bufs[i])))
+                        color_regid[i] += 3;
+        /* we could probably divide this up into things that need to be
+         * emitted if frag-prog is dirty vs if vert-prog is dirty..
+         */
+        OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
+        OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
+                        A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
+                        /* NOTE:  I guess SHADERRESTART and CONSTFULLUPDATE maybe
+                         * flush some caches? I think we only need to set those
+                         * bits if we have updated const or shader..
+                         */
+                        A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
+                        A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
+        OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
+                        A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
+                        COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_ZWCOORD));
+        OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
+        OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
+        OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
+                        A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
+                        A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
+        OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
+                        A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
+                        A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
+        OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
+        OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
+                        COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
+                        A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
+                        A3XX_SP_SP_CTRL_REG_L0MODE(0));
+        OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
+        OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
+        OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
+        OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
+                        A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
+                        COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
+                        A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
+                        A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
+                        A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
+                        A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
+                        A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
+                        COND(vp->has_samp, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
+                        A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
+        OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
+                        A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
+                        A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
+        OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
+                        A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
+                        A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp->total_in, 4) / 4));
+        for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
+                uint32_t reg = 0;
+                OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
+                j = ir3_next_varying(fp, j);
+                if (j < fp->inputs_count) {
+                        k = ir3_find_output(vp, fp->inputs[j].semantic);
+                        reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
+                        reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
+                }
+                j = ir3_next_varying(fp, j);
+                if (j < fp->inputs_count) {
+                        k = ir3_find_output(vp, fp->inputs[j].semantic);
+                        reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
+                        reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
+                }
+                OUT_RING(ring, reg);
+        }
+        for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
+                uint32_t reg = 0;
+                OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
+                j = ir3_next_varying(fp, j);
+                if (j < fp->inputs_count)
+                        reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
+                j = ir3_next_varying(fp, j);
+                if (j < fp->inputs_count)
+                        reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
+                j = ir3_next_varying(fp, j);
+                if (j < fp->inputs_count)
+                        reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
+                j = ir3_next_varying(fp, j);
+                if (j < fp->inputs_count)
+                        reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);
+                OUT_RING(ring, reg);
+        }
+        OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
+        OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
+                        A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
+        OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */
+        if (emit->key.binning_pass) {
+                OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
+                OUT_RING(ring, 0x00000000);
+                OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
+                OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
+                                A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
+                OUT_RING(ring, 0x00000000);
+                OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
+                OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
+                                A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
+        } else {
+                OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
+                OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
+                OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
+                OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
+                                A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
+                                COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
+                                A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
+                                A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
+                                A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
+                                A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
+                                A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
+                                COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
+                                A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
+                OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
+                                A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
+                                A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
+                                A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
+                OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
+                OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
+                                        MAX2(128, vp->constlen)) |
+                                A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
+                OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
+        }
+        OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
+        OUT_RING(ring,
+                         COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
+                         A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
+                         A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
+        OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
+        for (i = 0; i < 4; i++) {
+                uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
+                        COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
+                if (i < nr) {
+                        enum pipe_format fmt = pipe_surface_format(bufs[i]);
+                        mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
+                                COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
+                }
+                OUT_RING(ring, mrt_reg);
+        }
+        if (emit->key.binning_pass) {
+                OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
+                OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
+                                A3XX_VPC_ATTR_LMSIZE(1) |
+                                COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
+                OUT_RING(ring, 0x00000000);
+        } else {
+                uint32_t vinterp[4], flatshade[2], vpsrepl[4];
+                memset(vinterp, 0, sizeof(vinterp));
+                memset(flatshade, 0, sizeof(flatshade));
+                memset(vpsrepl, 0, sizeof(vpsrepl));
+                /* figure out VARYING_INTERP / FLAT_SHAD register values: */
+                for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
+                        uint32_t interp = fp->inputs[j].interpolate;
+                        /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
+                         * instead.. rather than -8 everywhere else..
+                         */
+                        uint32_t inloc = fp->inputs[j].inloc - 8;
+                        /* currently assuming varyings aligned to 4 (not
+                         * packed):
+                         */
+                        debug_assert((inloc % 4) == 0);
+                        if ((interp == TGSI_INTERPOLATE_CONSTANT) ||
+                                        ((interp == TGSI_INTERPOLATE_COLOR) && emit->rasterflat)) {
+                                uint32_t loc = inloc;
+                                for (i = 0; i < 4; i++, loc++) {
+                                        vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
+                                        flatshade[loc / 32] |= 1 << (loc % 32);
+                                }
+                        }
+                        /* Replace the .xy coordinates with S/T from the point sprite. Set
+                         * interpolation bits for .zw such that they become .01
+                         */
+                        if (emit->sprite_coord_enable & (1 << sem2idx(fp->inputs[j].semantic))) {
+                                vpsrepl[inloc / 16] |= (emit->sprite_coord_mode ? 0x0d : 0x09)
+                                        << ((inloc % 16) * 2);
+                                vinterp[(inloc + 2) / 16] |= 2 << (((inloc + 2) % 16) * 2);
+                                vinterp[(inloc + 3) / 16] |= 3 << (((inloc + 3) % 16) * 2);
+                        }
+                }
+                OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
+                OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
+                                A3XX_VPC_ATTR_THRDASSIGN(1) |
+                                A3XX_VPC_ATTR_LMSIZE(1) |
+                                COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
+                OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
+                                A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
+                OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
+                OUT_RING(ring, vinterp[0]);    /* VPC_VARYING_INTERP[0].MODE */
+                OUT_RING(ring, vinterp[1]);    /* VPC_VARYING_INTERP[1].MODE */
+                OUT_RING(ring, vinterp[2]);    /* VPC_VARYING_INTERP[2].MODE */
+                OUT_RING(ring, vinterp[3]);    /* VPC_VARYING_INTERP[3].MODE */
+                OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
+                OUT_RING(ring, vpsrepl[0]);    /* VPC_VARYING_PS_REPL[0].MODE */
+                OUT_RING(ring, vpsrepl[1]);    /* VPC_VARYING_PS_REPL[1].MODE */
+                OUT_RING(ring, vpsrepl[2]);    /* VPC_VARYING_PS_REPL[2].MODE */
+                OUT_RING(ring, vpsrepl[3]);    /* VPC_VARYING_PS_REPL[3].MODE */
+                OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
+                OUT_RING(ring, flatshade[0]);        /* SP_FS_FLAT_SHAD_MODE_REG_0 */
+                OUT_RING(ring, flatshade[1]);        /* SP_FS_FLAT_SHAD_MODE_REG_1 */
+        }
+        OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
+        OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
+                        A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
+        if (vpbuffer == BUFFER)
+                emit_shader(ring, vp);
+        OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
+        OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
+        if (!emit->key.binning_pass) {
+                if (fpbuffer == BUFFER)
+                        emit_shader(ring, fp);
+                OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
+                OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
+        }
+}
+void
+fd3_prog_init(struct pipe_context *pctx)
+{
+        pctx->create_fs_state = fd3_fp_state_create;
+        pctx->delete_fs_state = fd3_fp_state_delete;
+        pctx->create_vs_state = fd3_vp_state_create;
+        pctx->delete_vs_state = fd3_vp_state_delete;
+        fd_prog_init(pctx);
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_program.h
 ,0 → 1,53
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_PROGRAM_H_
+#define FD3_PROGRAM_H_
+#include "pipe/p_context.h"
+#include "freedreno_context.h"
+#include "ir3_shader.h"
+struct fd3_shader_stateobj {
+        struct ir3_shader *shader;
+};
+struct fd3_emit;
+void fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
+                                          int nr, struct pipe_surface **bufs);
+void fd3_prog_init(struct pipe_context *pctx);
+static inline struct ir3_shader_variant *
+fd3_shader_variant(struct fd3_shader_stateobj *so, struct ir3_shader_key key)
+{
+        return ir3_shader_variant(so->shader, key);
+}
+#endif /* FD3_PROGRAM_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_query.c
 ,0 → 1,138
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "freedreno_query_hw.h"
+#include "freedreno_context.h"
+#include "freedreno_util.h"
+#include "fd3_query.h"
+#include "fd3_format.h"
+struct fd_rb_samp_ctrs {
+        uint64_t ctr[16];
+};
+/*
+ * Occlusion Query:
+ *
+ * OCCLUSION_COUNTER and OCCLUSION_PREDICATE differ only in how they
+ * interpret results
+ */
+static struct fd_hw_sample *
+occlusion_get_sample(struct fd_context *ctx, struct fd_ringbuffer *ring)
+{
+        struct fd_hw_sample *samp =
+                        fd_hw_sample_init(ctx, sizeof(struct fd_rb_samp_ctrs));
+        /* Set RB_SAMPLE_COUNT_ADDR to samp->offset plus value of
+         * HW_QUERY_BASE_REG register:
+         */
+        OUT_PKT3(ring, CP_SET_CONSTANT, 3);
+        OUT_RING(ring, CP_REG(REG_A3XX_RB_SAMPLE_COUNT_ADDR) | 0x80000000);
+        OUT_RING(ring, HW_QUERY_BASE_REG);
+        OUT_RING(ring, samp->offset);
+        OUT_PKT0(ring, REG_A3XX_RB_SAMPLE_COUNT_CONTROL, 1);
+        OUT_RING(ring, A3XX_RB_SAMPLE_COUNT_CONTROL_COPY);
+        OUT_PKT3(ring, CP_DRAW_INDX, 3);
+        OUT_RING(ring, 0x00000000);
+        OUT_RING(ring, DRAW(DI_PT_POINTLIST_A2XX, DI_SRC_SEL_AUTO_INDEX,
+                                                INDEX_SIZE_IGN, USE_VISIBILITY, 0));
+        OUT_RING(ring, 0);             /* NumIndices */
+        fd_event_write(ctx, ring, ZPASS_DONE);
+        OUT_PKT0(ring, REG_A3XX_RBBM_PERFCTR_CTL, 1);
+        OUT_RING(ring, A3XX_RBBM_PERFCTR_CTL_ENABLE);
+        OUT_PKT0(ring, REG_A3XX_VBIF_PERF_CNT_EN, 1);
+        OUT_RING(ring, A3XX_VBIF_PERF_CNT_EN_CNT0 |
+                        A3XX_VBIF_PERF_CNT_EN_CNT1 |
+                        A3XX_VBIF_PERF_CNT_EN_PWRCNT0 |
+                        A3XX_VBIF_PERF_CNT_EN_PWRCNT1 |
+                        A3XX_VBIF_PERF_CNT_EN_PWRCNT2);
+        return samp;
+}
+static uint64_t
+count_samples(const struct fd_rb_samp_ctrs *start,
+                const struct fd_rb_samp_ctrs *end)
+{
+        uint64_t n = 0;
+        unsigned i;
+        /* not quite sure what all of these are, possibly different
+         * counters for each MRT render target:
+         */
+        for (i = 0; i < 16; i += 4)
+                n += end->ctr[i] - start->ctr[i];
+        return n;
+}
+static void
+occlusion_counter_accumulate_result(struct fd_context *ctx,
+                const void *start, const void *end,
+                union pipe_query_result *result)
+{
+        uint64_t n = count_samples(start, end);
+        result->u64 += n;
+}
+static void
+occlusion_predicate_accumulate_result(struct fd_context *ctx,
+                const void *start, const void *end,
+                union pipe_query_result *result)
+{
+        uint64_t n = count_samples(start, end);
+        result->b |= (n > 0);
+}
+static const struct fd_hw_sample_provider occlusion_counter = {
+                .query_type = PIPE_QUERY_OCCLUSION_COUNTER,
+                .active = FD_STAGE_DRAW,
+                .get_sample = occlusion_get_sample,
+                .accumulate_result = occlusion_counter_accumulate_result,
+};
+static const struct fd_hw_sample_provider occlusion_predicate = {
+                .query_type = PIPE_QUERY_OCCLUSION_PREDICATE,
+                .active = FD_STAGE_DRAW,
+                .get_sample = occlusion_get_sample,
+                .accumulate_result = occlusion_predicate_accumulate_result,
+};
+void fd3_query_context_init(struct pipe_context *pctx)
+{
+        fd_hw_query_register_provider(pctx, &occlusion_counter);
+        fd_hw_query_register_provider(pctx, &occlusion_predicate);
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_query.h
 ,0 → 1,36
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_QUERY_H_
+#define FD3_QUERY_H_
+#include "pipe/p_context.h"
+void fd3_query_context_init(struct pipe_context *pctx);
+#endif /* FD3_QUERY_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.c
 ,0 → 1,104
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_state.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "fd3_rasterizer.h"
+#include "fd3_context.h"
+#include "fd3_format.h"
+void *
+fd3_rasterizer_state_create(struct pipe_context *pctx,
+                const struct pipe_rasterizer_state *cso)
+{
+        struct fd3_rasterizer_stateobj *so;
+        float psize_min, psize_max;
+        so = CALLOC_STRUCT(fd3_rasterizer_stateobj);
+        if (!so)
+                return NULL;
+        so->base = *cso;
+        if (cso->point_size_per_vertex) {
+                psize_min = util_get_min_point_size(cso);
+                psize_max = 4092;
+        } else {
+                /* Force the point size to be as if the vertex output was disabled. */
+                psize_min = cso->point_size;
+                psize_max = cso->point_size;
+        }
+/*
+        if (cso->line_stipple_enable) {
+                ??? TODO line stipple
+        }
+        TODO cso->half_pixel_center
+        if (cso->multisample)
+                TODO
+*/
+        so->gras_cl_clip_cntl = A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER; /* ??? */
+        so->gras_su_point_minmax =
+                        A3XX_GRAS_SU_POINT_MINMAX_MIN(psize_min) |
+                        A3XX_GRAS_SU_POINT_MINMAX_MAX(psize_max);
+        so->gras_su_point_size   = A3XX_GRAS_SU_POINT_SIZE(cso->point_size);
+        so->gras_su_poly_offset_scale =
+                        A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(cso->offset_scale);
+        so->gras_su_poly_offset_offset =
+                        A3XX_GRAS_SU_POLY_OFFSET_OFFSET(cso->offset_units);
+        so->gras_su_mode_control =
+                        A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(cso->line_width/2.0);
+        so->pc_prim_vtx_cntl =
+                A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(fd_polygon_mode(cso->fill_front)) |
+                A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(fd_polygon_mode(cso->fill_back));
+        if (cso->fill_front != PIPE_POLYGON_MODE_FILL ||
+                cso->fill_back != PIPE_POLYGON_MODE_FILL)
+                so->pc_prim_vtx_cntl |= A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE;
+        if (cso->cull_face & PIPE_FACE_FRONT)
+                so->gras_su_mode_control |= A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT;
+        if (cso->cull_face & PIPE_FACE_BACK)
+                so->gras_su_mode_control |= A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK;
+        if (!cso->front_ccw)
+                so->gras_su_mode_control |= A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW;
+        if (!cso->flatshade_first)
+                so->pc_prim_vtx_cntl |= A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST;
+        if (cso->offset_tri)
+                so->gras_su_mode_control |= A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET;
+        if (!cso->depth_clip)
+                so->gras_cl_clip_cntl |= A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE;
+        return so;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.h
 ,0 → 1,56
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_RASTERIZER_H_
+#define FD3_RASTERIZER_H_
+#include "pipe/p_state.h"
+#include "pipe/p_context.h"
+struct fd3_rasterizer_stateobj {
+        struct pipe_rasterizer_state base;
+        uint32_t gras_su_point_minmax;
+        uint32_t gras_su_point_size;
+        uint32_t gras_su_poly_offset_scale;
+        uint32_t gras_su_poly_offset_offset;
+        uint32_t gras_su_mode_control;
+        uint32_t gras_cl_clip_cntl;
+        uint32_t pc_prim_vtx_cntl;
+};
+static INLINE struct fd3_rasterizer_stateobj *
+fd3_rasterizer_stateobj(struct pipe_rasterizer_state *rast)
+{
+        return (struct fd3_rasterizer_stateobj *)rast;
+}
+void * fd3_rasterizer_state_create(struct pipe_context *pctx,
+                const struct pipe_rasterizer_state *cso);
+#endif /* FD3_RASTERIZER_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_screen.c
 ,0 → 1,109
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_screen.h"
+#include "util/u_format.h"
+#include "fd3_screen.h"
+#include "fd3_context.h"
+#include "fd3_format.h"
+static boolean
+fd3_screen_is_format_supported(struct pipe_screen *pscreen,
+                enum pipe_format format,
+                enum pipe_texture_target target,
+                unsigned sample_count,
+                unsigned usage)
+{
+        unsigned retval = 0;
+        if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
+                        (sample_count > 1) || /* TODO add MSAA */
+                        !util_format_is_supported(format, usage)) {
+                DBG("not supported: format=%s, target=%d, sample_count=%d, usage=%x",
+                                util_format_name(format), target, sample_count, usage);
+                return FALSE;
+        }
+        if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+                        (fd3_pipe2vtx(format) != ~0)) {
+                retval |= PIPE_BIND_VERTEX_BUFFER;
+        }
+        if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+                        (fd3_pipe2tex(format) != ~0)) {
+                retval |= PIPE_BIND_SAMPLER_VIEW;
+        }
+        if ((usage & (PIPE_BIND_RENDER_TARGET |
+                                PIPE_BIND_DISPLAY_TARGET |
+                                PIPE_BIND_SCANOUT |
+                                PIPE_BIND_SHARED |
+                                PIPE_BIND_BLENDABLE)) &&
+                        (fd3_pipe2color(format) != ~0) &&
+                        (fd3_pipe2tex(format) != ~0)) {
+                retval |= usage & (PIPE_BIND_RENDER_TARGET |
+                                PIPE_BIND_DISPLAY_TARGET |
+                                PIPE_BIND_SCANOUT |
+                                PIPE_BIND_SHARED);
+                if (!util_format_is_pure_integer(format))
+                        retval |= usage & PIPE_BIND_BLENDABLE;
+        }
+        if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+                        (fd_pipe2depth(format) != ~0) &&
+                        (fd3_pipe2tex(format) != ~0)) {
+                retval |= PIPE_BIND_DEPTH_STENCIL;
+        }
+        if ((usage & PIPE_BIND_INDEX_BUFFER) &&
+                        (fd_pipe2index(format) != ~0)) {
+                retval |= PIPE_BIND_INDEX_BUFFER;
+        }
+        if (usage & PIPE_BIND_TRANSFER_READ)
+                retval |= PIPE_BIND_TRANSFER_READ;
+        if (usage & PIPE_BIND_TRANSFER_WRITE)
+                retval |= PIPE_BIND_TRANSFER_WRITE;
+        if (retval != usage) {
+                DBG("not supported: format=%s, target=%d, sample_count=%d, "
+                                "usage=%x, retval=%x", util_format_name(format),
+                                target, sample_count, usage, retval);
+        }
+        return retval == usage;
+}
+void
+fd3_screen_init(struct pipe_screen *pscreen)
+{
+        fd_screen(pscreen)->max_rts = 4;
+        pscreen->context_create = fd3_context_create;
+        pscreen->is_format_supported = fd3_screen_is_format_supported;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_screen.h
 ,0 → 1,36
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_SCREEN_H_
+#define FD3_SCREEN_H_
+#include "pipe/p_screen.h"
+void fd3_screen_init(struct pipe_screen *pscreen);
+#endif /* FD3_SCREEN_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
 ,0 → 1,306
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_state.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "util/u_inlines.h"
+#include "util/u_format.h"
+#include "fd3_texture.h"
+#include "fd3_format.h"
+static enum a3xx_tex_clamp
+tex_clamp(unsigned wrap, bool clamp_to_edge)
+{
+        /* Hardware does not support _CLAMP, but we emulate it: */
+        if (wrap == PIPE_TEX_WRAP_CLAMP) {
+                wrap = (clamp_to_edge) ?
+                        PIPE_TEX_WRAP_CLAMP_TO_EDGE : PIPE_TEX_WRAP_CLAMP_TO_BORDER;
+        }
+        switch (wrap) {
+        case PIPE_TEX_WRAP_REPEAT:
+                return A3XX_TEX_REPEAT;
+        case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+                return A3XX_TEX_CLAMP_TO_EDGE;
+        case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+                return A3XX_TEX_CLAMP_TO_BORDER;
+        case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+                /* only works for PoT.. need to emulate otherwise! */
+                return A3XX_TEX_MIRROR_CLAMP;
+        case PIPE_TEX_WRAP_MIRROR_REPEAT:
+                return A3XX_TEX_MIRROR_REPEAT;
+        case PIPE_TEX_WRAP_MIRROR_CLAMP:
+        case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+                /* these two we could perhaps emulate, but we currently
+                 * just don't advertise PIPE_CAP_TEXTURE_MIRROR_CLAMP
+                 */
+        default:
+                DBG("invalid wrap: %u", wrap);
+                return 0;
+        }
+}
+static enum a3xx_tex_filter
+tex_filter(unsigned filter, bool aniso)
+{
+        switch (filter) {
+        case PIPE_TEX_FILTER_NEAREST:
+                return A3XX_TEX_NEAREST;
+        case PIPE_TEX_FILTER_LINEAR:
+                return aniso ? A3XX_TEX_ANISO : A3XX_TEX_LINEAR;
+        default:
+                DBG("invalid filter: %u", filter);
+                return 0;
+        }
+}
+static void *
+fd3_sampler_state_create(struct pipe_context *pctx,
+                const struct pipe_sampler_state *cso)
+{
+        struct fd3_sampler_stateobj *so = CALLOC_STRUCT(fd3_sampler_stateobj);
+        unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));
+        bool miplinear = false;
+        bool clamp_to_edge;
+        if (!so)
+                return NULL;
+        if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR)
+                miplinear = true;
+        so->base = *cso;
+        /*
+         * For nearest filtering, _CLAMP means _CLAMP_TO_EDGE;  for linear
+         * filtering, _CLAMP means _CLAMP_TO_BORDER while additionally
+         * clamping the texture coordinates to [0.0, 1.0].
+         *
+         * The clamping will be taken care of in the shaders.  There are two
+         * filters here, but let the minification one has a say.
+         */
+        clamp_to_edge = (cso->min_img_filter == PIPE_TEX_FILTER_NEAREST);
+        if (!clamp_to_edge) {
+                so->saturate_s = (cso->wrap_s == PIPE_TEX_WRAP_CLAMP);
+                so->saturate_t = (cso->wrap_t == PIPE_TEX_WRAP_CLAMP);
+                so->saturate_r = (cso->wrap_r == PIPE_TEX_WRAP_CLAMP);
+        }
+        so->texsamp0 =
+                        COND(!cso->normalized_coords, A3XX_TEX_SAMP_0_UNNORM_COORDS) |
+                        COND(miplinear, A3XX_TEX_SAMP_0_MIPFILTER_LINEAR) |
+                        A3XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |
+                        A3XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |
+                        A3XX_TEX_SAMP_0_ANISO(aniso) |
+                        A3XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s, clamp_to_edge)) |
+                        A3XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t, clamp_to_edge)) |
+                        A3XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r, clamp_to_edge));
+        if (cso->compare_mode)
+                so->texsamp0 |= A3XX_TEX_SAMP_0_COMPARE_FUNC(cso->compare_func); /* maps 1:1 */
+        if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
+                so->texsamp1 =
+                                A3XX_TEX_SAMP_1_LOD_BIAS(cso->lod_bias) |
+                                A3XX_TEX_SAMP_1_MIN_LOD(cso->min_lod) |
+                                A3XX_TEX_SAMP_1_MAX_LOD(cso->max_lod);
+        } else {
+                so->texsamp1 = 0x00000000;
+        }
+        return so;
+}
+static void
+fd3_sampler_states_bind(struct pipe_context *pctx,
+                unsigned shader, unsigned start,
+                unsigned nr, void **hwcso)
+{
+        struct fd_context *ctx = fd_context(pctx);
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        uint16_t saturate_s = 0, saturate_t = 0, saturate_r = 0;
+        unsigned i;
+        for (i = 0; i < nr; i++) {
+                if (hwcso[i]) {
+                        struct fd3_sampler_stateobj *sampler =
+                                        fd3_sampler_stateobj(hwcso[i]);
+                        if (sampler->saturate_s)
+                                saturate_s |= (1 << i);
+                        if (sampler->saturate_t)
+                                saturate_t |= (1 << i);
+                        if (sampler->saturate_r)
+                                saturate_r |= (1 << i);
+                }
+        }
+        fd_sampler_states_bind(pctx, shader, start, nr, hwcso);
+        if (shader == PIPE_SHADER_FRAGMENT) {
+                fd3_ctx->fsaturate =
+                        (saturate_s != 0) ||
+                        (saturate_t != 0) ||
+                        (saturate_r != 0);
+                fd3_ctx->fsaturate_s = saturate_s;
+                fd3_ctx->fsaturate_t = saturate_t;
+                fd3_ctx->fsaturate_r = saturate_r;
+        } else if (shader == PIPE_SHADER_VERTEX) {
+                fd3_ctx->vsaturate =
+                        (saturate_s != 0) ||
+                        (saturate_t != 0) ||
+                        (saturate_r != 0);
+                fd3_ctx->vsaturate_s = saturate_s;
+                fd3_ctx->vsaturate_t = saturate_t;
+                fd3_ctx->vsaturate_r = saturate_r;
+        }
+}
+static enum a3xx_tex_type
+tex_type(unsigned target)
+{
+        switch (target) {
+        default:
+                assert(0);
+        case PIPE_BUFFER:
+        case PIPE_TEXTURE_1D:
+        case PIPE_TEXTURE_1D_ARRAY:
+                return A3XX_TEX_1D;
+        case PIPE_TEXTURE_RECT:
+        case PIPE_TEXTURE_2D:
+        case PIPE_TEXTURE_2D_ARRAY:
+                return A3XX_TEX_2D;
+        case PIPE_TEXTURE_3D:
+                return A3XX_TEX_3D;
+        case PIPE_TEXTURE_CUBE:
+        case PIPE_TEXTURE_CUBE_ARRAY:
+                return A3XX_TEX_CUBE;
+        }
+}
+static struct pipe_sampler_view *
+fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
+                const struct pipe_sampler_view *cso)
+{
+        struct fd3_pipe_sampler_view *so = CALLOC_STRUCT(fd3_pipe_sampler_view);
+        struct fd_resource *rsc = fd_resource(prsc);
+        unsigned lvl = cso->u.tex.first_level;
+        unsigned miplevels = cso->u.tex.last_level - lvl;
+        uint32_t sz2 = 0;
+        if (!so)
+                return NULL;
+        so->base = *cso;
+        pipe_reference(NULL, &prsc->reference);
+        so->base.texture = prsc;
+        so->base.reference.count = 1;
+        so->base.context = pctx;
+        so->texconst0 =
+                        A3XX_TEX_CONST_0_TYPE(tex_type(prsc->target)) |
+                        A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(cso->format)) |
+                        A3XX_TEX_CONST_0_MIPLVLS(miplevels) |
+                        fd3_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g,
+                                                cso->swizzle_b, cso->swizzle_a);
+        if (util_format_is_srgb(cso->format))
+                so->texconst0 |= A3XX_TEX_CONST_0_SRGB;
+        so->texconst1 =
+                        A3XX_TEX_CONST_1_FETCHSIZE(fd3_pipe2fetchsize(cso->format)) |
+                        A3XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
+                        A3XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
+        /* when emitted, A3XX_TEX_CONST_2_INDX() must be OR'd in: */
+        so->texconst2 =
+                        A3XX_TEX_CONST_2_PITCH(rsc->slices[lvl].pitch * rsc->cpp);
+        switch (prsc->target) {
+        case PIPE_TEXTURE_1D_ARRAY:
+        case PIPE_TEXTURE_2D_ARRAY:
+                so->texconst3 =
+                                A3XX_TEX_CONST_3_DEPTH(prsc->array_size - 1) |
+                                A3XX_TEX_CONST_3_LAYERSZ1(rsc->slices[0].size0);
+                break;
+        case PIPE_TEXTURE_3D:
+                so->texconst3 =
+                                A3XX_TEX_CONST_3_DEPTH(u_minify(prsc->depth0, lvl)) |
+                                A3XX_TEX_CONST_3_LAYERSZ1(rsc->slices[lvl].size0);
+                while (lvl < cso->u.tex.last_level && sz2 != rsc->slices[lvl+1].size0)
+                        sz2 = rsc->slices[++lvl].size0;
+                so->texconst3 |= A3XX_TEX_CONST_3_LAYERSZ2(sz2);
+                break;
+        default:
+                so->texconst3 = 0x00000000;
+                break;
+        }
+        return &so->base;
+}
+static void
+fd3_set_sampler_views(struct pipe_context *pctx, unsigned shader,
+                                          unsigned start, unsigned nr,
+                                          struct pipe_sampler_view **views)
+{
+        struct fd_context *ctx = fd_context(pctx);
+        struct fd3_context *fd3_ctx = fd3_context(ctx);
+        struct fd_texture_stateobj *tex;
+        uint16_t integer_s = 0, *ptr;
+        int i;
+        fd_set_sampler_views(pctx, shader, start, nr, views);
+        switch (shader) {
+        case PIPE_SHADER_FRAGMENT:
+                tex = &ctx->fragtex;
+                ptr = &fd3_ctx->finteger_s;
+                break;
+        case PIPE_SHADER_VERTEX:
+                tex = &ctx->verttex;
+                ptr = &fd3_ctx->vinteger_s;
+                break;
+        default:
+                return;
+        }
+        for (i = 0; i < tex->num_textures; i++)
+                if (util_format_is_pure_integer(tex->textures[i]->format))
+                        integer_s |= 1 << i;
+        *ptr = integer_s;
+}
+void
+fd3_texture_init(struct pipe_context *pctx)
+{
+        pctx->create_sampler_state = fd3_sampler_state_create;
+        pctx->bind_sampler_states = fd3_sampler_states_bind;
+        pctx->create_sampler_view = fd3_sampler_view_create;
+        pctx->set_sampler_views = fd3_set_sampler_views;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_texture.h
 ,0 → 1,68
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_TEXTURE_H_
+#define FD3_TEXTURE_H_
+#include "pipe/p_context.h"
+#include "freedreno_texture.h"
+#include "freedreno_resource.h"
+#include "fd3_context.h"
+#include "fd3_format.h"
+struct fd3_sampler_stateobj {
+        struct pipe_sampler_state base;
+        uint32_t texsamp0, texsamp1;
+        bool saturate_s, saturate_t, saturate_r;
+};
+static INLINE struct fd3_sampler_stateobj *
+fd3_sampler_stateobj(struct pipe_sampler_state *samp)
+{
+        return (struct fd3_sampler_stateobj *)samp;
+}
+struct fd3_pipe_sampler_view {
+        struct pipe_sampler_view base;
+        uint32_t texconst0, texconst1, texconst2, texconst3;
+};
+static INLINE struct fd3_pipe_sampler_view *
+fd3_pipe_sampler_view(struct pipe_sampler_view *pview)
+{
+        return (struct fd3_pipe_sampler_view *)pview;
+}
+unsigned fd3_get_const_idx(struct fd_context *ctx,
+                struct fd_texture_stateobj *tex, unsigned samp_id);
+void fd3_texture_init(struct pipe_context *pctx);
+#endif /* FD3_TEXTURE_H_ */

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_zsa.c
 ,0 → 1,104
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#include "pipe/p_state.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "fd3_zsa.h"
+#include "fd3_context.h"
+#include "fd3_format.h"
+void *
+fd3_zsa_state_create(struct pipe_context *pctx,
+                const struct pipe_depth_stencil_alpha_state *cso)
+{
+        struct fd3_zsa_stateobj *so;
+        so = CALLOC_STRUCT(fd3_zsa_stateobj);
+        if (!so)
+                return NULL;
+        so->base = *cso;
+        so->rb_depth_control |=
+                        A3XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
+        if (cso->depth.enabled)
+                so->rb_depth_control |=
+                        A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
+                        A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE;
+        if (cso->depth.writemask)
+                so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;
+        if (cso->stencil[0].enabled) {
+                const struct pipe_stencil_state *s = &cso->stencil[0];
+                so->rb_stencil_control |=
+                        A3XX_RB_STENCIL_CONTROL_STENCIL_READ |
+                        A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
+                        A3XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
+                        A3XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
+                        A3XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
+                        A3XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
+                so->rb_stencilrefmask |=
+xff000000 | /* ??? */
+                        A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
+                        A3XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);
+                if (cso->stencil[1].enabled) {
+                        const struct pipe_stencil_state *bs = &cso->stencil[1];
+                        so->rb_stencil_control |=
+                                A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
+                                A3XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
+                                A3XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
+                                A3XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
+                                A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
+                        so->rb_stencilrefmask_bf |=
+xff000000 | /* ??? */
+                                A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |
+                                A3XX_RB_STENCILREFMASK_STENCILMASK(bs->valuemask);
+                }
+        }
+        if (cso->alpha.enabled) {
+                so->rb_render_control =
+                        A3XX_RB_RENDER_CONTROL_ALPHA_TEST |
+                        A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(cso->alpha.func);
+                so->rb_alpha_ref =
+                        A3XX_RB_ALPHA_REF_UINT(cso->alpha.ref_value * 255.0) |
+                        A3XX_RB_ALPHA_REF_FLOAT(cso->alpha.ref_value);
+                so->rb_depth_control |=
+                        A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
+        }
+        return so;
+}

 /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/freedreno/a3xx/fd3_zsa.h
 ,0 → 1,57
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+/*
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+#ifndef FD3_ZSA_H_
+#define FD3_ZSA_H_
+#include "pipe/p_state.h"
+#include "pipe/p_context.h"
+#include "freedreno_util.h"
+struct fd3_zsa_stateobj {
+        struct pipe_depth_stencil_alpha_state base;
+        uint32_t rb_render_control;
+        uint32_t rb_alpha_ref;
+        uint32_t rb_depth_control;
+        uint32_t rb_stencil_control;
+        uint32_t rb_stencilrefmask;
+        uint32_t rb_stencilrefmask_bf;
+};
+static INLINE struct fd3_zsa_stateobj *
+fd3_zsa_stateobj(struct pipe_depth_stencil_alpha_state *zsa)
+{
+        return (struct fd3_zsa_stateobj *)zsa;
+}
+void * fd3_zsa_state_create(struct pipe_context *pctx,
+                const struct pipe_depth_stencil_alpha_state *cso);
+#endif /* FD3_ZSA_H_ */

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