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Regard whitespace Rev 4348 → Rev 4349

/contrib/sdk/fasm/include/swresample-0.inc
0,0 → 1,93
import swresample-0, \
ff_float_to_int16_a_sse2,'ff_float_to_int16_a_sse2',\,'ff_float_to_int16_a_sse2',\
ff_float_to_int16_u_sse2,'ff_float_to_int16_u_sse2',\,'ff_float_to_int16_u_sse2',\
ff_float_to_int32_a_sse2,'ff_float_to_int32_a_sse2',\,'ff_float_to_int32_a_sse2',\
ff_float_to_int32_u_sse2,'ff_float_to_int32_u_sse2',\,'ff_float_to_int32_u_sse2',\
ff_int16_to_float_a_sse2,'ff_int16_to_float_a_sse2',\,'ff_int16_to_float_a_sse2',\
ff_int16_to_float_u_sse2,'ff_int16_to_float_u_sse2',\,'ff_int16_to_float_u_sse2',\
ff_int16_to_int32_a_mmx,'ff_int16_to_int32_a_mmx',\,'ff_int16_to_int32_a_mmx',\
ff_int16_to_int32_a_sse2,'ff_int16_to_int32_a_sse2',\,'ff_int16_to_int32_a_sse2',\
ff_int16_to_int32_u_mmx,'ff_int16_to_int32_u_mmx',\,'ff_int16_to_int32_u_mmx',\
ff_int16_to_int32_u_sse2,'ff_int16_to_int32_u_sse2',\,'ff_int16_to_int32_u_sse2',\
ff_int32_to_float_a_sse2,'ff_int32_to_float_a_sse2',\,'ff_int32_to_float_a_sse2',\
ff_int32_to_float_u_sse2,'ff_int32_to_float_u_sse2',\,'ff_int32_to_float_u_sse2',\
ff_int32_to_int16_a_mmx,'ff_int32_to_int16_a_mmx',\,'ff_int32_to_int16_a_mmx',\
ff_int32_to_int16_a_sse2,'ff_int32_to_int16_a_sse2',\,'ff_int32_to_int16_a_sse2',\
ff_int32_to_int16_u_mmx,'ff_int32_to_int16_u_mmx',\,'ff_int32_to_int16_u_mmx',\
ff_int32_to_int16_u_sse2,'ff_int32_to_int16_u_sse2',\,'ff_int32_to_int16_u_sse2',\
ff_log2_tab,'ff_log2_tab',\,'ff_log2_tab',\
ff_mix_1_1_a_float_sse,'ff_mix_1_1_a_float_sse',\,'ff_mix_1_1_a_float_sse',\
ff_mix_1_1_a_int16_mmx,'ff_mix_1_1_a_int16_mmx',\,'ff_mix_1_1_a_int16_mmx',\
ff_mix_1_1_a_int16_sse2,'ff_mix_1_1_a_int16_sse2',\,'ff_mix_1_1_a_int16_sse2',\
ff_mix_1_1_u_float_sse,'ff_mix_1_1_u_float_sse',\,'ff_mix_1_1_u_float_sse',\
ff_mix_1_1_u_int16_mmx,'ff_mix_1_1_u_int16_mmx',\,'ff_mix_1_1_u_int16_mmx',\
ff_mix_1_1_u_int16_sse2,'ff_mix_1_1_u_int16_sse2',\,'ff_mix_1_1_u_int16_sse2',\
ff_mix_2_1_a_float_sse,'ff_mix_2_1_a_float_sse',\,'ff_mix_2_1_a_float_sse',\
ff_mix_2_1_a_int16_mmx,'ff_mix_2_1_a_int16_mmx',\,'ff_mix_2_1_a_int16_mmx',\
ff_mix_2_1_a_int16_sse2,'ff_mix_2_1_a_int16_sse2',\,'ff_mix_2_1_a_int16_sse2',\
ff_mix_2_1_u_float_sse,'ff_mix_2_1_u_float_sse',\,'ff_mix_2_1_u_float_sse',\
ff_mix_2_1_u_int16_mmx,'ff_mix_2_1_u_int16_mmx',\,'ff_mix_2_1_u_int16_mmx',\
ff_mix_2_1_u_int16_sse2,'ff_mix_2_1_u_int16_sse2',\,'ff_mix_2_1_u_int16_sse2',\
ff_pack_2ch_float_to_int16_a_sse2,'ff_pack_2ch_float_to_int16_a_sse2',\,'ff_pack_2ch_float_to_int16_a_sse2',\
ff_pack_2ch_float_to_int16_u_sse2,'ff_pack_2ch_float_to_int16_u_sse2',\,'ff_pack_2ch_float_to_int16_u_sse2',\
ff_pack_2ch_float_to_int32_a_sse2,'ff_pack_2ch_float_to_int32_a_sse2',\,'ff_pack_2ch_float_to_int32_a_sse2',\
ff_pack_2ch_float_to_int32_u_sse2,'ff_pack_2ch_float_to_int32_u_sse2',\,'ff_pack_2ch_float_to_int32_u_sse2',\
ff_pack_2ch_int16_to_float_a_sse2,'ff_pack_2ch_int16_to_float_a_sse2',\,'ff_pack_2ch_int16_to_float_a_sse2',\
ff_pack_2ch_int16_to_float_u_sse2,'ff_pack_2ch_int16_to_float_u_sse2',\,'ff_pack_2ch_int16_to_float_u_sse2',\
ff_pack_2ch_int16_to_int16_a_sse2,'ff_pack_2ch_int16_to_int16_a_sse2',\,'ff_pack_2ch_int16_to_int16_a_sse2',\
ff_pack_2ch_int16_to_int16_u_sse2,'ff_pack_2ch_int16_to_int16_u_sse2',\,'ff_pack_2ch_int16_to_int16_u_sse2',\
ff_pack_2ch_int16_to_int32_a_sse2,'ff_pack_2ch_int16_to_int32_a_sse2',\,'ff_pack_2ch_int16_to_int32_a_sse2',\
ff_pack_2ch_int16_to_int32_u_sse2,'ff_pack_2ch_int16_to_int32_u_sse2',\,'ff_pack_2ch_int16_to_int32_u_sse2',\
ff_pack_2ch_int32_to_float_a_sse2,'ff_pack_2ch_int32_to_float_a_sse2',\,'ff_pack_2ch_int32_to_float_a_sse2',\
ff_pack_2ch_int32_to_float_u_sse2,'ff_pack_2ch_int32_to_float_u_sse2',\,'ff_pack_2ch_int32_to_float_u_sse2',\
ff_pack_2ch_int32_to_int16_a_sse2,'ff_pack_2ch_int32_to_int16_a_sse2',\,'ff_pack_2ch_int32_to_int16_a_sse2',\
ff_pack_2ch_int32_to_int16_u_sse2,'ff_pack_2ch_int32_to_int16_u_sse2',\,'ff_pack_2ch_int32_to_int16_u_sse2',\
ff_pack_2ch_int32_to_int32_a_sse2,'ff_pack_2ch_int32_to_int32_a_sse2',\,'ff_pack_2ch_int32_to_int32_a_sse2',\
ff_pack_2ch_int32_to_int32_u_sse2,'ff_pack_2ch_int32_to_int32_u_sse2',\,'ff_pack_2ch_int32_to_int32_u_sse2',\
ff_pack_6ch_float_to_float_a_mmx,'ff_pack_6ch_float_to_float_a_mmx',\,'ff_pack_6ch_float_to_float_a_mmx',\
ff_pack_6ch_float_to_float_a_sse4,'ff_pack_6ch_float_to_float_a_sse4',\,'ff_pack_6ch_float_to_float_a_sse4',\
ff_pack_6ch_float_to_float_u_mmx,'ff_pack_6ch_float_to_float_u_mmx',\,'ff_pack_6ch_float_to_float_u_mmx',\
ff_pack_6ch_float_to_float_u_sse4,'ff_pack_6ch_float_to_float_u_sse4',\,'ff_pack_6ch_float_to_float_u_sse4',\
ff_pack_6ch_float_to_int32_a_sse4,'ff_pack_6ch_float_to_int32_a_sse4',\,'ff_pack_6ch_float_to_int32_a_sse4',\
ff_pack_6ch_float_to_int32_u_sse4,'ff_pack_6ch_float_to_int32_u_sse4',\,'ff_pack_6ch_float_to_int32_u_sse4',\
ff_pack_6ch_int32_to_float_a_sse4,'ff_pack_6ch_int32_to_float_a_sse4',\,'ff_pack_6ch_int32_to_float_a_sse4',\
ff_pack_6ch_int32_to_float_u_sse4,'ff_pack_6ch_int32_to_float_u_sse4',\,'ff_pack_6ch_int32_to_float_u_sse4',\
ff_resample_int16_rounder,'ff_resample_int16_rounder',\,'ff_resample_int16_rounder',\
ff_unpack_2ch_float_to_int16_a_sse2,'ff_unpack_2ch_float_to_int16_a_sse2',\,'ff_unpack_2ch_float_to_int16_a_sse2',\
ff_unpack_2ch_float_to_int16_u_sse2,'ff_unpack_2ch_float_to_int16_u_sse2',\,'ff_unpack_2ch_float_to_int16_u_sse2',\
ff_unpack_2ch_float_to_int32_a_sse2,'ff_unpack_2ch_float_to_int32_a_sse2',\,'ff_unpack_2ch_float_to_int32_a_sse2',\
ff_unpack_2ch_float_to_int32_u_sse2,'ff_unpack_2ch_float_to_int32_u_sse2',\,'ff_unpack_2ch_float_to_int32_u_sse2',\
ff_unpack_2ch_int16_to_float_a_sse2,'ff_unpack_2ch_int16_to_float_a_sse2',\,'ff_unpack_2ch_int16_to_float_a_sse2',\
ff_unpack_2ch_int16_to_float_a_ssse3,'ff_unpack_2ch_int16_to_float_a_ssse3',\,'ff_unpack_2ch_int16_to_float_a_ssse3',\
ff_unpack_2ch_int16_to_float_u_sse2,'ff_unpack_2ch_int16_to_float_u_sse2',\,'ff_unpack_2ch_int16_to_float_u_sse2',\
ff_unpack_2ch_int16_to_float_u_ssse3,'ff_unpack_2ch_int16_to_float_u_ssse3',\,'ff_unpack_2ch_int16_to_float_u_ssse3',\
ff_unpack_2ch_int16_to_int16_a_sse2,'ff_unpack_2ch_int16_to_int16_a_sse2',\,'ff_unpack_2ch_int16_to_int16_a_sse2',\
ff_unpack_2ch_int16_to_int16_a_ssse3,'ff_unpack_2ch_int16_to_int16_a_ssse3',\,'ff_unpack_2ch_int16_to_int16_a_ssse3',\
ff_unpack_2ch_int16_to_int16_u_sse2,'ff_unpack_2ch_int16_to_int16_u_sse2',\,'ff_unpack_2ch_int16_to_int16_u_sse2',\
ff_unpack_2ch_int16_to_int16_u_ssse3,'ff_unpack_2ch_int16_to_int16_u_ssse3',\,'ff_unpack_2ch_int16_to_int16_u_ssse3',\
ff_unpack_2ch_int16_to_int32_a_sse2,'ff_unpack_2ch_int16_to_int32_a_sse2',\,'ff_unpack_2ch_int16_to_int32_a_sse2',\
ff_unpack_2ch_int16_to_int32_a_ssse3,'ff_unpack_2ch_int16_to_int32_a_ssse3',\,'ff_unpack_2ch_int16_to_int32_a_ssse3',\
ff_unpack_2ch_int16_to_int32_u_sse2,'ff_unpack_2ch_int16_to_int32_u_sse2',\,'ff_unpack_2ch_int16_to_int32_u_sse2',\
ff_unpack_2ch_int16_to_int32_u_ssse3,'ff_unpack_2ch_int16_to_int32_u_ssse3',\,'ff_unpack_2ch_int16_to_int32_u_ssse3',\
ff_unpack_2ch_int32_to_float_a_sse2,'ff_unpack_2ch_int32_to_float_a_sse2',\,'ff_unpack_2ch_int32_to_float_a_sse2',\
ff_unpack_2ch_int32_to_float_u_sse2,'ff_unpack_2ch_int32_to_float_u_sse2',\,'ff_unpack_2ch_int32_to_float_u_sse2',\
ff_unpack_2ch_int32_to_int16_a_sse2,'ff_unpack_2ch_int32_to_int16_a_sse2',\,'ff_unpack_2ch_int32_to_int16_a_sse2',\
ff_unpack_2ch_int32_to_int16_u_sse2,'ff_unpack_2ch_int32_to_int16_u_sse2',\,'ff_unpack_2ch_int32_to_int16_u_sse2',\
ff_unpack_2ch_int32_to_int32_a_sse2,'ff_unpack_2ch_int32_to_int32_a_sse2',\,'ff_unpack_2ch_int32_to_int32_a_sse2',\
ff_unpack_2ch_int32_to_int32_u_sse2,'ff_unpack_2ch_int32_to_int32_u_sse2',\,'ff_unpack_2ch_int32_to_int32_u_sse2',\
swr_alloc,'swr_alloc',\,'swr_alloc',\
swr_alloc_set_opts,'swr_alloc_set_opts',\,'swr_alloc_set_opts',\
swr_convert,'swr_convert',\,'swr_convert',\
swr_drop_output,'swr_drop_output',\,'swr_drop_output',\
swr_free,'swr_free',\,'swr_free',\
swr_get_class,'swr_get_class',\,'swr_get_class',\
swr_get_delay,'swr_get_delay',\,'swr_get_delay',\
swr_init,'swr_init',\,'swr_init',\
swr_inject_silence,'swr_inject_silence',\,'swr_inject_silence',\
swr_next_pts,'swr_next_pts',\,'swr_next_pts',\
swr_set_channel_mapping,'swr_set_channel_mapping',\,'swr_set_channel_mapping',\
swr_set_compensation,'swr_set_compensation',\,'swr_set_compensation',\
swr_set_matrix,'swr_set_matrix',\,'swr_set_matrix',\
swresample_configuration,'swresample_configuration',\,'swresample_configuration',\
swresample_license,'swresample_license',\,'swresample_license',\
swresample_version,'swresample_version',\,'swresample_version'