BlueGreycalmElegant

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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /kernel @ 369

  → /kernel/ @ 373

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 369 → Rev 373

/kernel/trunk/build.bat
52,7 → 52,7
if not exist bin mkdir bin
echo lang fix %lang% > lang.inc
fasm kernel.asm bin\kernel.mnt
fasm -m 65536 kernel.asm bin\kernel.mnt
if not %errorlevel%==0 goto :Error_FasmFailed
erase lang.inc
goto :eof
72,7 → 72,7
if not exist bin\drivers mkdir bin\drivers
cd drivers
for %%a in (%drivers%) do (
fasm %%a.asm ..\bin\drivers\%%a.obj
fasm -m 65536 %%a.asm ..\bin\drivers\%%a.obj
if not %errorlevel%==0 goto :Error_FasmFailed
)
cd ..
84,7 → 84,7
if not exist bin\skins mkdir bin\skins
cd skin
fasm default.asm ..\bin\skins\default.skn
fasm -m 65536 default.asm ..\bin\skins\default.skn
if not %errorlevel%==0 goto :Error_FasmFailed
cd ..
goto :eof

/kernel/trunk/kernel.asm
4374,7 → 4374,7
ret
uglobal
msg_board_data: times 512 db 0
msg_board_data: times 4096 db 0
msg_board_count dd 0x0
endg
4390,7 → 4390,7
mov [msg_board_data+ecx],bl
inc ecx
and ecx, 511
and ecx, 4095
mov [msg_board_count], ecx
mov [check_idle_semaphore], 5
ret

/kernel/trunk/kernel32.inc
75,30 → 75,30
}
; \end{diamond}[29.09.2006]
struc db [a] { common . db a
if ~used .
display 'not used db: ',`.,13,10
end if }
struc dw [a] { common . dw a
if ~used .
display 'not used dw: ',`.,13,10
end if }
struc dd [a] { common . dd a
if ~used .
display 'not used dd: ',`.,13,10
end if }
struc dp [a] { common . dp a
if ~used .
display 'not used dp: ',`.,13,10
end if }
struc dq [a] { common . dq a
if ~used .
display 'not used dq: ',`.,13,10
end if }
struc dt [a] { common . dt a
if ~used .
display 'not used dt: ',`.,13,10
end if }
;struc db [a] { common . db a
; if ~used .
; display 'not used db: ',`.,13,10
; end if }
;struc dw [a] { common . dw a
; if ~used .
; display 'not used dw: ',`.,13,10
; end if }
;struc dd [a] { common . dd a
; if ~used .
; display 'not used dd: ',`.,13,10
; end if }
;struc dp [a] { common . dp a
; if ~used .
; display 'not used dp: ',`.,13,10
; end if }
;struc dq [a] { common . dq a
; if ~used .
; display 'not used dq: ',`.,13,10
; end if }
;struc dt [a] { common . dt a
; if ~used .
; display 'not used dt: ',`.,13,10
; end if }
struc RECT {
.left dd ?

/kernel/trunk/network/eth_drv/drivers/rtl8139.inc
177,7 → 177,7
uglobal
align 4
rtl8139_rx_buff_offset: dd 0
curr_tx_desc: dd 0
curr_tx_desc dd 0
endg
iglobal
442,8 → 442,8
; Transmits a packet of data via the ethernet card
; Pointer to 48 bit destination address in edi
; Type of packet in bx
; size of packet in ecx
; pointer to packet data in esi
; Size of packet in ecx
; Pointer to packet data in esi
; Destroyed registers
; eax, edx, esi, edi
; ToDo

/kernel/trunk/network/eth_drv/drivers/rtl8169.inc
0,0 → 1,1204
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; RTL8169.INC ;;
;; ;;
;; Ethernet driver for Menuet OS ;;
;; ;;
;; Version 0.1 11 February 2007 ;;
;; ;;
;; Driver for chips of RealTek 8169 family ;;
;; References: ;;
;; r8169.c - linux driver (etherboot project) ;;
;; ethernet driver template by Mike Hibbett ;;
;; ;;
;; The copyright statement is ;;
;; ;;
;; GNU GENERAL PUBLIC LICENSE ;;
;; Version 2, June 1991 ;;
;; ;;
;; Copyright 2007 mike.dld, ;;
;; mike.dld@gmail.com ;;
;; ;;
;; See file COPYING for details ;;
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ETH_ALEN equ 6
ETH_HLEN equ (2 * ETH_ALEN + 2)
ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for
; mininmum 64bytes frame length
RTL8169_REG_MAC0 equ 0x0 ; Ethernet hardware address
RTL8169_REG_MAR0 equ 0x8 ; Multicast filter
RTL8169_REG_TxDescStartAddr equ 0x20
RTL8169_REG_TxHDescStartAddr equ 0x28
RTL8169_REG_FLASH equ 0x30
RTL8169_REG_ERSR equ 0x36
RTL8169_REG_ChipCmd equ 0x37
RTL8169_REG_TxPoll equ 0x38
RTL8169_REG_IntrMask equ 0x3C
RTL8169_REG_IntrStatus equ 0x3E
RTL8169_REG_TxConfig equ 0x40
RTL8169_REG_RxConfig equ 0x44
RTL8169_REG_RxMissed equ 0x4C
RTL8169_REG_Cfg9346 equ 0x50
RTL8169_REG_Config0 equ 0x51
RTL8169_REG_Config1 equ 0x52
RTL8169_REG_Config2 equ 0x53
RTL8169_REG_Config3 equ 0x54
RTL8169_REG_Config4 equ 0x55
RTL8169_REG_Config5 equ 0x56
RTL8169_REG_MultiIntr equ 0x5C
RTL8169_REG_PHYAR equ 0x60
RTL8169_REG_TBICSR equ 0x64
RTL8169_REG_TBI_ANAR equ 0x68
RTL8169_REG_TBI_LPAR equ 0x6A
RTL8169_REG_PHYstatus equ 0x6C
RTL8169_REG_RxMaxSize equ 0xDA
RTL8169_REG_CPlusCmd equ 0xE0
RTL8169_REG_RxDescStartAddr equ 0xE4
RTL8169_REG_ETThReg equ 0xEC
RTL8169_REG_FuncEvent equ 0xF0
RTL8169_REG_FuncEventMask equ 0xF4
RTL8169_REG_FuncPresetState equ 0xF8
RTL8169_REG_FuncForceEvent equ 0xFC
; InterruptStatusBits
RTL8169_ISB_SYSErr equ 0x8000
RTL8169_ISB_PCSTimeout equ 0x4000
RTL8169_ISB_SWInt equ 0x0100
RTL8169_ISB_TxDescUnavail equ 0x80
RTL8169_ISB_RxFIFOOver equ 0x40
RTL8169_ISB_LinkChg equ 0x20
RTL8169_ISB_RxOverflow equ 0x10
RTL8169_ISB_TxErr equ 0x08
RTL8169_ISB_TxOK equ 0x04
RTL8169_ISB_RxErr equ 0x02
RTL8169_ISB_RxOK equ 0x01
; RxStatusDesc
RTL8169_SD_RxRES equ 0x00200000
RTL8169_SD_RxCRC equ 0x00080000
RTL8169_SD_RxRUNT equ 0x00100000
RTL8169_SD_RxRWT equ 0x00400000
; ChipCmdBits
RTL8169_CMD_Reset equ 0x10
RTL8169_CMD_RxEnb equ 0x08
RTL8169_CMD_TxEnb equ 0x04
RTL8169_CMD_RxBufEmpty equ 0x01
; Cfg9346Bits
RTL8169_CFG_9346_Lock equ 0x00
RTL8169_CFG_9346_Unlock equ 0xC0
; rx_mode_bits
RTL8169_RXM_AcceptErr equ 0x20
RTL8169_RXM_AcceptRunt equ 0x10
RTL8169_RXM_AcceptBroadcast equ 0x08
RTL8169_RXM_AcceptMulticast equ 0x04
RTL8169_RXM_AcceptMyPhys equ 0x02
RTL8169_RXM_AcceptAllPhys equ 0x01
; RxConfigBits
RTL8169_RXC_FIFOShift equ 13
RTL8169_RXC_DMAShift equ 8
; TxConfigBits
RTL8169_TXC_InterFrameGapShift equ 24
RTL8169_TXC_DMAShift equ 8 ; DMA burst value (0-7) is shift this many bits
; rtl8169_PHYstatus
RTL8169_PHYS_TBI_Enable equ 0x80
RTL8169_PHYS_TxFlowCtrl equ 0x40
RTL8169_PHYS_RxFlowCtrl equ 0x20
RTL8169_PHYS_1000bpsF equ 0x10
RTL8169_PHYS_100bps equ 0x08
RTL8169_PHYS_10bps equ 0x04
RTL8169_PHYS_LinkStatus equ 0x02
RTL8169_PHYS_FullDup equ 0x01
; GIGABIT_PHY_registers
RTL8169_PHY_CTRL_REG equ 0
RTL8169_PHY_STAT_REG equ 1
RTL8169_PHY_AUTO_NEGO_REG equ 4
RTL8169_PHY_1000_CTRL_REG equ 9
; GIGABIT_PHY_REG_BIT
RTL8169_PHY_Restart_Auto_Nego equ 0x0200
RTL8169_PHY_Enable_Auto_Nego equ 0x1000
; PHY_STAT_REG = 1;
RTL8169_PHY_Auto_Neco_Comp equ 0x0020
; PHY_AUTO_NEGO_REG = 4;
RTL8169_PHY_Cap_10_Half equ 0x0020
RTL8169_PHY_Cap_10_Full equ 0x0040
RTL8169_PHY_Cap_100_Half equ 0x0080
RTL8169_PHY_Cap_100_Full equ 0x0100
; PHY_1000_CTRL_REG = 9;
RTL8169_PHY_Cap_1000_Full equ 0x0200
RTL8169_PHY_Cap_1000_Half equ 0x0100
RTL8169_PHY_Cap_PAUSE equ 0x0400
RTL8169_PHY_Cap_ASYM_PAUSE equ 0x0800
RTL8169_PHY_Cap_Null equ 0x0
; _MediaType
RTL8169_MT_10_Half equ 0x01
RTL8169_MT_10_Full equ 0x02
RTL8169_MT_100_Half equ 0x04
RTL8169_MT_100_Full equ 0x08
RTL8169_MT_1000_Full equ 0x10
; _TBICSRBit
RTL8169_TBI_LinkOK equ 0x02000000
; _DescStatusBit
RTL8169_DSB_OWNbit equ 0x80000000
RTL8169_DSB_EORbit equ 0x40000000
RTL8169_DSB_FSbit equ 0x20000000
RTL8169_DSB_LSbit equ 0x10000000
; MAC address length
MAC_ADDR_LEN equ 6
; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
MAX_ETH_FRAME_SIZE equ 1536
TX_FIFO_THRESH equ 256 ; In bytes
RX_FIFO_THRESH equ 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
RX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024
TX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024
ETTh equ 0x3F ; 0x3F means NO threshold
EarlyTxThld equ 0x3F ; 0x3F means NO early transmit
RxPacketMaxSize equ 0x0800 ; Maximum size supported is 16K-1
InterFrameGap equ 0x03 ; 3 means InterFrameGap = the shortest one
NUM_TX_DESC equ 1 ; Number of Tx descriptor registers
NUM_RX_DESC equ 4 ; Number of Rx descriptor registers
RX_BUF_SIZE equ 1536 ; Rx Buffer size
HZ equ 1000
RTL_MIN_IO_SIZE equ 0x80
TX_TIMEOUT equ (6*HZ)
RTL8169_TIMER_EXPIRE_TIME equ 100
ETH_HDR_LEN equ 14
DEFAULT_MTU equ 1500
DEFAULT_RX_BUF_LEN equ 1536
;#ifdef RTL8169_JUMBO_FRAME_SUPPORT
;#define MAX_JUMBO_FRAME_MTU ( 10000 )
;#define MAX_RX_SKBDATA_SIZE ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
;#else
MAX_RX_SKBDATA_SIZE equ 1600
;#endif //end #ifdef RTL8169_JUMBO_FRAME_SUPPORT
;#ifdef RTL8169_USE_IO
;!!!#define RTL_W8(reg, val8) outb ((val8), ioaddr + (reg))
macro RTL_W8 reg,val8 {
if ~reg eq dx
mov dx,word[rtl8169_tpc.mmio_addr]
add dx,reg
end if
if ~val8 eq al
mov al,val8
end if
out dx,al
}
;!!!#define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg))
macro RTL_W16 reg,val16 {
if ~reg eq dx
mov dx,word[rtl8169_tpc.mmio_addr]
add dx,reg
end if
if ~val16 eq ax
mov ax,val16
end if
out dx,ax
}
;!!!#define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg))
macro RTL_W32 reg,val32 {
if ~reg eq dx
mov dx,word[rtl8169_tpc.mmio_addr]
add dx,reg
end if
if ~val32 eq eax
mov eax,val32
end if
out dx,eax
}
;!!!#define RTL_R8(reg) inb (ioaddr + (reg))
macro RTL_R8 reg {
if ~reg eq dx
mov dx,word[rtl8169_tpc.mmio_addr]
add dx,reg
end if
in al,dx
}
;!!!#define RTL_R16(reg) inw (ioaddr + (reg))
macro RTL_R16 reg {
if ~reg eq dx
mov dx,word[rtl8169_tpc.mmio_addr]
add dx,reg
end if
in ax,dx
}
;!!!#define RTL_R32(reg) ((unsigned long) inl (ioaddr + (reg)))
macro RTL_R32 reg {
if ~reg eq dx
mov dx,word[rtl8169_tpc.mmio_addr]
add dx,reg
end if
in eax,dx
}
;#else
; write/read MMIO register
;#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
;#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
;#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
;#define RTL_R8(reg) readb (ioaddr + (reg))
;#define RTL_R16(reg) readw (ioaddr + (reg))
;#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
;#endif
MCFG_METHOD_01 equ 0x01
MCFG_METHOD_02 equ 0x02
MCFG_METHOD_03 equ 0x03
MCFG_METHOD_04 equ 0x04
MCFG_METHOD_05 equ 0x05
MCFG_METHOD_11 equ 0x0b
MCFG_METHOD_12 equ 0x0c
MCFG_METHOD_13 equ 0x0d
MCFG_METHOD_14 equ 0x0e
MCFG_METHOD_15 equ 0x0f
PCFG_METHOD_1 equ 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
PCFG_METHOD_2 equ 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
PCFG_METHOD_3 equ 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
PCI_COMMAND_IO equ 0x1 ; Enable response in I/O space
PCI_COMMAND_MEM equ 0x2 ; Enable response in mem space
PCI_COMMAND_MASTER equ 0x4 ; Enable bus mastering
PCI_LATENCY_TIMER equ 0x0d ; 8 bits
PCI_COMMAND_SPECIAL equ 0x8 ; Enable response to special cycles
PCI_COMMAND_INVALIDATE equ 0x10 ; Use memory write and invalidate
PCI_COMMAND_VGA_PALETTE equ 0x20 ; Enable palette snooping
PCI_COMMAND_PARITY equ 0x40 ; Enable parity checking
PCI_COMMAND_WAIT equ 0x80 ; Enable address/data stepping
PCI_COMMAND_SERR equ 0x100 ; Enable SERR
PCI_COMMAND_FAST_BACK equ 0x200 ; Enable back-to-back writes
struc rtl8169_TxDesc {
.status dd ?
.vlan_tag dd ?
.buf_addr dd ?
.buf_Haddr dd ?
}
virtual at 0
rtl8169_TxDesc rtl8169_TxDesc
sizeof.rtl8169_TxDesc = $ - rtl8169_TxDesc
end virtual
struc rtl8169_RxDesc {
.status dd ?
.vlan_tag dd ?
.buf_addr dd ?
.buf_Haddr dd ?
}
virtual at 0
rtl8169_RxDesc rtl8169_RxDesc
sizeof.rtl8169_RxDesc = $ - rtl8169_RxDesc
end virtual
virtual at eth_data_start
; Define the TX Descriptor
align 256
rtl8169_tx_ring rb NUM_TX_DESC * sizeof.rtl8169_TxDesc
; Create a static buffer of size RX_BUF_SZ for each
; TX Descriptor. All descriptors point to a
; part of this buffer
align 256
rtl8169_txb rb NUM_TX_DESC * RX_BUF_SIZE
; Define the RX Descriptor
align 256
rtl8169_rx_ring rb NUM_RX_DESC * sizeof.rtl8169_TxDesc
; Create a static buffer of size RX_BUF_SZ for each
; RX Descriptor All descriptors point to a
; part of this buffer
align 256
rtl8169_rxb rb NUM_RX_DESC * RX_BUF_SIZE
rtl8169_tpc:
.mmio_addr dd ? ; memory map physical address
.chipset dd ?
.pcfg dd ?
.mcfg dd ?
.cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt
.cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt
.TxDescArrays dd ? ; Index of Tx Descriptor buffer
.RxDescArrays dd ? ; Index of Rx Descriptor buffer
.TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer
.RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer
.RxBufferRing rd NUM_RX_DESC ; Index of Rx Buffer array
.Tx_skbuff rd NUM_TX_DESC
end virtual
rtl8169_intr_mask = RTL8169_ISB_LinkChg or RTL8169_ISB_RxOverflow or RTL8169_ISB_RxFIFOOver or RTL8169_ISB_TxErr or RTL8169_ISB_TxOK or RTL8169_ISB_RxErr or RTL8169_ISB_RxOK
rtl8169_rx_config = (RX_FIFO_THRESH shl RTL8169_RXC_FIFOShift) or (RX_DMA_BURST shl RTL8169_RXC_DMAShift) or 0x0000000E
iglobal
;static struct {
; const char *name;
; u8 mcfg; /* depend on RTL8169 docs */
; u32 RxConfigMask; /* should clear the bits supported by this chip */
;}
rtl_chip_info dd \
MCFG_METHOD_01, 0xff7e1880, \ ; RTL8169
MCFG_METHOD_02, 0xff7e1880, \ ; RTL8169s/8110s
MCFG_METHOD_03, 0xff7e1880, \ ; RTL8169s/8110s
MCFG_METHOD_04, 0xff7e1880, \ ; RTL8169sb/8110sb
MCFG_METHOD_05, 0xff7e1880, \ ; RTL8169sc/8110sc
MCFG_METHOD_11, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E
MCFG_METHOD_12, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E
MCFG_METHOD_13, 0xff7e1880, \ ; RTL8101e // PCI-E 8139
MCFG_METHOD_14, 0xff7e1880, \ ; RTL8100e // PCI-E 8139
MCFG_METHOD_15, 0xff7e1880 ; RTL8100e // PCI-E 8139
mac_info dd \
0x38800000, MCFG_METHOD_15, \
0x38000000, MCFG_METHOD_12, \
0x34000000, MCFG_METHOD_13, \
0x30800000, MCFG_METHOD_14, \
0x30000000, MCFG_METHOD_11, \
0x18000000, MCFG_METHOD_05, \
0x10000000, MCFG_METHOD_04, \
0x04000000, MCFG_METHOD_03, \
0x00800000, MCFG_METHOD_02, \
0x00000000, MCFG_METHOD_01 ; catch-all
endg
PCI_COMMAND_IO equ 0x1 ; Enable response in I/O space
PCI_COMMAND_MEM equ 0x2 ; Enable response in mem space
PCI_COMMAND_MASTER equ 0x4 ; Enable bus mastering
PCI_LATENCY_TIMER equ 0x0d ; 8 bits
PCI_COMMAND_SPECIAL equ 0x8 ; Enable response to special cycles
PCI_COMMAND_INVALIDATE equ 0x10 ; Use memory write and invalidate
PCI_COMMAND_VGA_PALETTE equ 0x20 ; Enable palette snooping
PCI_COMMAND_PARITY equ 0x40 ; Enable parity checking
PCI_COMMAND_WAIT equ 0x80 ; Enable address/data stepping
PCI_COMMAND_SERR equ 0x100 ; Enable SERR
PCI_COMMAND_FAST_BACK equ 0x200 ; Enable back-to-back writes
PCI_VENDOR_ID equ 0x00 ; 16 bits
PCI_DEVICE_ID equ 0x02 ; 16 bits
PCI_COMMAND equ 0x04 ; 16 bits
PCI_BASE_ADDRESS_0 equ 0x10 ; 32 bits
PCI_BASE_ADDRESS_1 equ 0x14 ; 32 bits
PCI_BASE_ADDRESS_2 equ 0x18 ; 32 bits
PCI_BASE_ADDRESS_3 equ 0x1c ; 32 bits
PCI_BASE_ADDRESS_4 equ 0x20 ; 32 bits
PCI_BASE_ADDRESS_5 equ 0x24 ; 32 bits
PCI_BASE_ADDRESS_MEM_TYPE_MASK equ 0x06
PCI_BASE_ADDRESS_MEM_TYPE_32 equ 0x00 ; 32 bit address
PCI_BASE_ADDRESS_MEM_TYPE_1M equ 0x02 ; Below 1M [obsolete]
PCI_BASE_ADDRESS_MEM_TYPE_64 equ 0x04 ; 64 bit address
PCI_BASE_ADDRESS_IO_MASK equ (not 0x03)
PCI_BASE_ADDRESS_MEM_MASK equ (not 0x0f)
PCI_BASE_ADDRESS_SPACE_IO equ 0x01
PCI_ROM_ADDRESS equ 0x30 ; 32 bits
proc CONFIG_CMD,where:byte
movzx eax,byte[pci_bus]
shl eax,8
mov al,[pci_dev]
shl eax,8
mov al,[where]
and al,not 3
or eax,0x80000000
ret
endp
proc pci_read_config_byte,where:dword
push edx
stdcall CONFIG_CMD,[where]
mov dx,0xCF8
out dx,eax
mov edx,[where]
and edx,3
add edx,0xCFC
in al,dx
pop edx
ret
endp
proc pci_read_config_word,where:dword
push edx
stdcall CONFIG_CMD,[where]
mov dx,0xCF8
out dx,eax
mov edx,[where]
and edx,2
add edx,0xCFC
in ax,dx
pop edx
ret
endp
proc pci_read_config_dword,where:dword
push edx
stdcall CONFIG_CMD,[where]
mov edx,0xCF8
out dx,eax
mov edx,0xCFC
in eax,dx
pop edx
ret
endp
proc pci_write_config_byte,where:dword,value:byte
push edx
stdcall CONFIG_CMD,[where]
mov dx,0xCF8
out dx,eax
mov edx,[where]
and edx,3
add edx,0xCFC
mov al,[value]
out dx,al
pop edx
ret
endp
proc pci_write_config_word,where:dword,value:word
push edx
stdcall CONFIG_CMD,[where]
mov dx,0xCF8
out dx,eax
mov edx,[where]
and edx,2
add edx,0xCFC
mov ax,[value]
out dx,ax
pop edx
ret
endp
proc pci_write_config_dword,where:dword,value:dword
push edx
stdcall CONFIG_CMD,[where]
mov edx,0xCF8
out dx,eax
mov edx,0xCFC
mov eax,[value]
out dx,eax
pop edx
ret
endp
; Set device to be a busmaster in case BIOS neglected to do so.
; Also adjust PCI latency timer to a reasonable value, 32.
proc adjust_pci_device
DEBUGF 1,"K : adjust_pci_device\n"
stdcall pci_read_config_word,PCI_COMMAND
mov bx,ax
or bx,PCI_COMMAND_MASTER or PCI_COMMAND_IO
cmp ax,bx
je @f
DEBUGF 1,"K : adjust_pci_device: The PCI BIOS has not enabled this device!\nK : Updating PCI command %x->%x. pci_bus %x pci_device_fn %x\n",ax,bx,[pci_bus]:2,[pci_dev]:2
stdcall pci_write_config_word,PCI_COMMAND,ebx
@@:
stdcall pci_read_config_byte,PCI_LATENCY_TIMER
cmp al,32
jae @f
DEBUGF 1,"K : adjust_pci_device: PCI latency timer (CFLT) is unreasonably low at %d.\nK : Setting to 32 clocks.\n",al
stdcall pci_write_config_byte,PCI_LATENCY_TIMER,32
@@:
ret
endp
; Find the start of a pci resource
proc pci_bar_start,index:dword
stdcall pci_read_config_dword,[index]
test eax,PCI_BASE_ADDRESS_SPACE_IO
jz @f
and eax,PCI_BASE_ADDRESS_IO_MASK
jmp .exit
@@: push eax
and eax,PCI_BASE_ADDRESS_MEM_TYPE_MASK
cmp eax,PCI_BASE_ADDRESS_MEM_TYPE_64
jne .not64
mov eax,[index]
add eax,4
stdcall pci_read_config_dword,eax
or eax,eax
jz .not64
DEBUGF 1,"K : pci_bar_start: Unhandled 64bit BAR\n"
add esp,4
or eax,-1
ret
.not64:
pop eax
and eax,PCI_BASE_ADDRESS_MEM_MASK
.exit:
ret
endp
proc rtl8169_init_board
DEBUGF 1,"K : rtl8169_init_board\n"
call adjust_pci_device
stdcall pci_bar_start,PCI_BASE_ADDRESS_0
mov [rtl8169_tpc.mmio_addr],eax
; Soft reset the chip
RTL_W8 RTL8169_REG_ChipCmd,RTL8169_CMD_Reset
; Check that the chip has finished the reset
mov ecx,1000
@@: RTL_R8 RTL8169_REG_ChipCmd
test al,RTL8169_CMD_Reset
jz @f
stdcall udelay,10
loop @b
@@:
; identify config method
RTL_R32 RTL8169_REG_TxConfig
and eax,0x7c800000
DEBUGF 1,"K : rtl8169_init_board: TxConfig & 0x7c800000 = 0x%x\n",eax
mov esi,mac_info-8
@@: add esi,8
mov ecx,eax
and ecx,[esi]
cmp ecx,[esi]
jne @b
mov eax,[esi+4]
mov [rtl8169_tpc.mcfg],eax
mov [rtl8169_tpc.pcfg],PCFG_METHOD_3