Subversion Repositories Kolibri OS

Compare Revisions

Regard whitespace Rev 3037 → Rev 3033

/drivers/video/drm/i915/bitmap.c
16,11 → 16,13
extern struct drm_device *main_device;
 
 
 
void __attribute__((regparm(1))) destroy_bitmap(bitmap_t *bitmap)
{
dma_addr_t *pages = bitmap->obj->allocated_pages;
dma_addr_t *pages = bitmap->obj->allocated_pages;;
int i;
 
printf("destroy bitmap %d\n", bitmap->handle);
free_handle(&bm_mm, bitmap->handle);
bitmap->handle = 0;
bitmap->obj->base.read_domains = I915_GEM_DOMAIN_GTT;
27,7 → 29,6
bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 
mutex_lock(&main_device->struct_mutex);
 
drm_gem_object_unreference(&bitmap->obj->base);
mutex_unlock(&main_device->struct_mutex);
 
36,8 → 37,6
for (i = 0; i < bitmap->page_count; i++)
FreePage(pages[i]);
 
DRM_DEBUG("%s freec %d pages\n", __FUNCTION__, bitmap->page_count);
 
free(pages);
};
UserFree(bitmap->uaddr);
213,8 → 212,6
bitmap->max_count = max_count;
};
 
DRM_DEBUG("%s alloc %d pages\n", __FUNCTION__, page_count);
 
obj = i915_gem_alloc_object(dev, size);
if (obj == NULL)
goto err4;
246,7 → 243,7
pbitmap->pitch = pitch;
 
 
DRM_DEBUG("%s handle: %d pitch: %d gpu_addr: %x user_addr: %x\n",
printf("%s handle: %d pitch: %d gpu_addr: %x user_addr: %x\n",
__FUNCTION__, handle, pitch, obj->gtt_offset, uaddr);
 
return 0;
285,9 → 282,7
if(unlikely(bitmap==NULL))
return -1;
 
mutex_lock(&main_device->struct_mutex);
ret = i915_gem_object_set_to_cpu_domain(bitmap->obj, true);
mutex_unlock(&main_device->struct_mutex);
 
if(ret != 0 )
{
343,7 → 338,7
 
void __attribute__((regparm(1))) destroy_context(struct context *context)
{
DRM_DEBUG("destroy context %x\n", context);
printf("destroy context %x\n", context);
 
context_map[context->slot] = NULL;
 
370,7 → 365,7
return context;
 
context = CreateObject(GetPid(), sizeof(*context));
 
printf("context %x\n", context);
if( context != NULL)
{
drm_i915_private_t *dev_priv = dev->dev_private;
/drivers/video/drm/i915/i915_irq.c
2518,6 → 2518,7
 
void irq_handler_kms()
{
printf("%s\n",__FUNCTION__);
ironlake_irq_handler(irq_device);
}
 
2526,6 → 2527,8
int irq_line;
int ret = 0;
 
ENTER();
 
mutex_lock(&dev->struct_mutex);
 
/* Driver must have been initialized */
2571,7 → 2574,10
 
PciWrite16(dev->pdev->busnr, dev->pdev->devfn, 4, cmd);
 
DRM_DEBUG("i915: irq initialized.\n");
dbgprintf("PCI_CMD: %04x\n", cmd);
 
DRM_INFO("i915: irq initialized.\n");
LEAVE();
return ret;
}
 
/drivers/video/drm/i915/kms_display.c
142,7 → 142,7
};
};
 
DRM_ERROR("%s failed\n", __FUNCTION__);
printf("%s failed\n", __FUNCTION__);
 
return -1;
 
202,7 → 202,7
 
sysSetScreen(fb->width, fb->height, fb->pitches[0]);
 
DRM_DEBUG_KMS("new mode %d x %d pitch %d\n",
dbgprintf("new mode %d x %d pitch %d\n",
fb->width, fb->height, fb->pitches[0]);
}
else
249,7 → 249,7
 
crtc = encoder->crtc;
 
DRM_DEBUG_KMS("CONNECTOR %x ID: %d status %d encoder %x\n crtc %x",
dbgprintf("CONNECTOR %x ID: %d status %d encoder %x\n crtc %x",
connector, connector->base.id,
connector->status, connector->encoder,
crtc);
278,6 → 278,8
u32_t ifl;
int err;
 
// ENTER();
 
list_for_each_entry(connector, &dev->mode_config.connector_list, head)
{
if( connector->status != connector_status_connected)
287,7 → 289,7
encoder = connector_funcs->best_encoder(connector);
if( encoder == NULL)
{
DRM_DEBUG_KMS("CONNECTOR %x ID: %d no active encoders\n",
dbgprintf("CONNECTOR %x ID: %d no active encoders\n",
connector, connector->base.id);
continue;
}
294,7 → 296,7
connector->encoder = encoder;
crtc = encoder->crtc;
 
DRM_DEBUG_KMS("CONNECTOR %x ID:%d status:%d ENCODER %x CRTC %x ID:%d\n",
dbgprintf("CONNECTOR %x ID:%d status:%d ENCODER %x CRTC %x ID:%d\n",
connector, connector->base.id,
connector->status, connector->encoder,
crtc, crtc->base.id );
304,7 → 306,7
 
if(connector == NULL)
{
DRM_ERROR("No active connectors!\n");
dbgprintf("No active connectors!\n");
return -1;
};
 
327,7 → 329,7
 
if(crtc == NULL)
{
DRM_ERROR("No CRTC for encoder %d\n", encoder->base.id);
dbgprintf("No CRTC for encoder %d\n", encoder->base.id);
return -1;
};
 
369,7 → 371,14
main_device = dev;
 
err = init_bitmaps();
if( !err )
{
printf("Initialize bitmap manager\n");
};
 
 
// LEAVE();
 
return 0;
};
 
378,6 → 387,8
{
int err = -1;
 
// ENTER();
 
// dbgprintf("mode %x count %d\n", mode, *count);
 
if( *count == 0 )
409,6 → 420,7
*count = i;
err = 0;
};
// LEAVE();
return err;
};
 
416,6 → 428,8
{
int err = -1;
 
// ENTER();
 
// dbgprintf("width %d height %d vrefresh %d\n",
// mode->width, mode->height, mode->freq);
 
430,19 → 444,17
err = 0;
};
 
// LEAVE();
return err;
};
 
void __attribute__((regparm(1))) destroy_cursor(cursor_t *cursor)
{
/* FIXME synchronization */
 
list_del(&cursor->list);
 
i915_gem_object_unpin(cursor->cobj);
 
mutex_lock(&main_device->struct_mutex);
drm_gem_object_unreference(&cursor->cobj->base);
mutex_unlock(&main_device->struct_mutex);
 
// radeon_bo_unpin(cursor->robj);
// KernelFree(cursor->data);
__DestroyObject(cursor);
};
 
452,11 → 464,12
struct drm_i915_gem_object *obj;
uint32_t *bits;
uint32_t *src;
void *mapped;
 
int i,j;
int ret;
 
// ENTER();
 
if (dev_priv->info->cursor_needs_physical)
{
bits = (uint32_t*)KernelAlloc(CURSOR_WIDTH*CURSOR_HEIGHT*4);
479,7 → 492,7
/* You don't need to worry about fragmentation issues.
* GTT space is continuous. I guarantee it. */
 
mapped = bits = (u32*)MapIoMem(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
bits = (u32*)MapIoMem(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
CURSOR_WIDTH*CURSOR_HEIGHT*4, PG_SW);
 
if (unlikely(bits == NULL))
503,8 → 516,6
for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)
*bits++ = 0;
 
FreeKernelSpace(mapped);
 
// release old cursor
 
KernelFree(cursor->data);
512,6 → 523,7
cursor->data = bits;
 
cursor->header.destroy = destroy_cursor;
// LEAVE();
 
return 0;
}
667,19 → 679,37
typedef int v4si __attribute__ ((vector_size (16)));
 
 
 
static void
i915_gem_execbuffer_retire_commands(struct drm_device *dev,
struct drm_file *file,
struct intel_ring_buffer *ring)
{
/* Unconditionally force add_request to emit a full flush. */
ring->gpu_caches_dirty = true;
struct drm_i915_gem_request *request;
u32 invalidate;
u32 req;
/*
* Ensure that the commands in the batch buffer are
* finished before the interrupt fires.
*
* The sampler always gets flushed on i965 (sigh).
*/
invalidate = I915_GEM_DOMAIN_COMMAND;
if (INTEL_INFO(dev)->gen >= 4)
invalidate |= I915_GEM_DOMAIN_SAMPLER;
if (ring->flush(ring, invalidate, 0)) {
i915_gem_next_request_seqno(ring);
return;
}
 
/* Add a breadcrumb for the completion of the batch buffer */
(void)i915_add_request(ring, file, NULL);
if (request == NULL || i915_add_request(ring, NULL, &req)) {
i915_gem_next_request_seqno(ring);
}
}
 
 
 
 
 
int blit_video(u32 hbitmap, int dst_x, int dst_y,
int src_x, int src_y, u32 w, u32 h)
{
698,7 → 728,6
u32_t offset;
u8 slot;
int n=0;
int ret;
 
if(unlikely(hbitmap==0))
return -1;
884,56 → 913,18
 
context->cmd_buffer+= n*4;
 
context->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
// i915_gem_object_set_to_gtt_domain(bitmap->obj, false);
 
 
mutex_lock(&main_device->struct_mutex);
 
i915_gem_object_set_to_gtt_domain(bitmap->obj, false);
 
if (HAS_BLT(main_device))
{
u32 seqno;
int i;
int ret;
 
ring = &dev_priv->ring[BCS];
// printf("dispatch... ");
 
i915_gem_object_sync(bitmap->obj, ring);
intel_ring_invalidate_all_caches(ring);
 
seqno = i915_gem_next_request_seqno(ring);
// printf("seqno = %d\n", seqno);
 
for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
if (seqno < ring->sync_seqno[i]) {
/* The GPU can not handle its semaphore value wrapping,
* so every billion or so execbuffers, we need to stall
* the GPU in order to reset the counters.
*/
DRM_DEBUG("wrap seqno\n");
 
ret = i915_gpu_idle(main_device);
if (ret)
goto fail;
i915_gem_retire_requests(main_device);
 
BUG_ON(ring->sync_seqno[i]);
}
}
 
ret = ring->dispatch_execbuffer(ring, offset, n*4);
if (ret)
goto fail;
ring->dispatch_execbuffer(ring, offset, n*4);
// printf("done\n");
 
bitmap->obj->base.read_domains = bitmap->obj->base.pending_read_domains;
bitmap->obj->base.write_domain = bitmap->obj->base.pending_write_domain;
bitmap->obj->fenced_gpu_access = bitmap->obj->pending_fenced_gpu_access;
 
i915_gem_object_move_to_active(bitmap->obj, ring, seqno);
 
i915_gem_execbuffer_retire_commands(main_device, NULL, ring);
i915_gem_execbuffer_retire_commands(main_device, ring);
// printf("retire\n");
}
else
943,12 → 934,12
ring->flush(ring, 0, I915_GEM_DOMAIN_RENDER);
};
 
// bitmap->obj->base.read_domains = I915_GEM_DOMAIN_CPU;
// bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU;
bitmap->obj->base.read_domains = I915_GEM_DOMAIN_CPU;
bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 
mutex_unlock(&main_device->struct_mutex);
return 0;
fail:
return ret;
return -1;
};
 
 
1326,6 → 1317,7
struct work_struct *work)
{
unsigned long flags;
// ENTER();
 
// dbgprintf("wq: %x, work: %x\n",
// wq, work );
1344,11 → 1336,13
// dbgprintf("wq: %x head %x, next %x\n",
// wq, &wq->worklist, wq->worklist.next);
 
// LEAVE();
return 1;
};
 
void __stdcall delayed_work_timer_fn(unsigned long __data)
{
// ENTER();
struct delayed_work *dwork = (struct delayed_work *)__data;
struct workqueue_struct *wq = dwork->work.data;
 
1356,6 → 1350,7
// wq, &dwork->work );
 
__queue_work(wq, &dwork->work);
// LEAVE();
}
 
 
1373,6 → 1368,7
struct delayed_work *dwork, unsigned long delay)
{
u32 flags;
// ENTER();
 
// dbgprintf("wq: %x, work: %x\n",
// wq, &dwork->work );
/drivers/video/drm/i915/Gtt/intel-gtt.c
431,9 → 431,12
u32 gtt_map_size;
int ret;
 
ENTER();
 
ret = intel_private.driver->setup();
if (ret != 0)
{
LEAVE();
return ret;
};
 
491,6 → 494,8
 
intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 
LEAVE();
 
return 0;
}
 
/drivers/video/drm/i915/i915_dma.c
1297,6 → 1297,8
int ret = 0, mmio_bar, mmio_size;
uint32_t aperture_size;
 
ENTER();
 
info = (struct intel_device_info *) flags;
 
#if 0
1382,9 → 1384,17
aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
 
DRM_INFO("gtt_base_addr %x aperture_size %d\n",
dbgprintf("gtt_base_addr %x aperture_size %d\n",
dev_priv->mm.gtt_base_addr, aperture_size );
 
// dev_priv->mm.gtt_mapping =
// io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
// aperture_size);
// if (dev_priv->mm.gtt_mapping == NULL) {
// ret = -EIO;
// goto out_rmmap;
// }
 
// i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
// aperture_size);
 
1479,6 → 1489,8
if (IS_GEN5(dev))
intel_gpu_ips_init(dev_priv);
 
LEAVE();
 
return 0;
 
out_gem_unload:
/drivers/video/drm/i915/i915_drv.c
455,7 → 455,7
return -ENODEV;
}
 
DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
dbgprintf("device %x:%x\n", device.pci_dev.vendor,
device.pci_dev.device);
 
if (intel_info->gen != 3) {
475,6 → 475,8
struct drm_device *dev;
int ret;
 
ENTER();
 
dev = kzalloc(sizeof(*dev), 0);
if (!dev)
return -ENOMEM;
513,6 → 515,8
if (ret)
goto err_g4;
 
LEAVE();
 
return 0;
 
err_g4:
525,6 → 529,8
//err_g1:
free(dev);
 
LEAVE();
 
return ret;
}
 
/drivers/video/drm/i915/i915_gem.c
1409,7 → 1409,6
for (i = 0; i < obj->pages.nents; i++)
FreePage(obj->pages.page[i]);
 
DRM_DEBUG_KMS("%s free %d pages\n", __FUNCTION__, obj->pages.nents);
obj->dirty = 0;
kfree(obj->pages.page);
}
1466,7 → 1465,7
 
obj->pages.page[i] = page;
};
DRM_DEBUG_KMS("%s alloc %d pages\n", __FUNCTION__, page_count);
 
obj->pages.nents = page_count;
 
 
1836,6 → 1835,8
bool idle;
int i;
 
// ENTER();
 
dev_priv = container_of(work, drm_i915_private_t,
mm.retire_work.work);
dev = dev_priv->dev;
1843,6 → 1844,7
/* Come back later if the device is busy... */
if (!mutex_trylock(&dev->struct_mutex)) {
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
// LEAVE();
return;
}
 
1865,6 → 1867,7
intel_mark_idle(dev);
 
mutex_unlock(&dev->struct_mutex);
// LEAVE();
}
 
/**
/drivers/video/drm/i915/intel_display.c
1821,6 → 1821,7
 
I915_WRITE(reg, val & ~PIPECONF_ENABLE);
intel_wait_for_pipe_off(dev_priv->dev, pipe);
 
}
 
/*
2215,6 → 2216,7
intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
mutex_unlock(&dev->struct_mutex);
DRM_ERROR("failed to update base address\n");
LEAVE();
return ret;
}
 
3355,6 → 3357,7
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
mutex_unlock(&dev->struct_mutex);
 
}
 
static void ironlake_crtc_off(struct drm_crtc *crtc)
7483,7 → 7486,7
 
drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
 
DRM_DEBUG_KMS("CRTC %d mode %x FB %x enable %d\n",
dbgprintf("CRTC %d mode %x FB %x enable %d\n",
intel_crtc->base.base.id, intel_crtc->base.mode,
intel_crtc->base.fb, intel_crtc->base.enabled);
 
/drivers/video/drm/i915/intel_fb.c
240,6 → 240,8
drm_i915_private_t *dev_priv = dev->dev_private;
int ret;
 
ENTER();
 
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
if (!ifbdev)
return -ENOMEM;
258,6 → 260,7
drm_fb_helper_single_add_all_connectors(&ifbdev->helper);
drm_fb_helper_initial_config(&ifbdev->helper, 32);
 
LEAVE();
return 0;
}
 
/drivers/video/drm/i915/intel_i2c.c
34,6 → 34,7
#include <drm/i915_drm.h>
#include "i915_drv.h"
 
 
struct gmbus_port {
const char *name;
int reg;
/drivers/video/drm/i915/intel_panel.c
33,6 → 33,7
#include <linux/moduleparam.h>
#include "intel_drv.h"
 
 
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
 
void
/drivers/video/drm/i915/intel_pm.c
1104,13 → 1104,24
int *cursor_wm)
{
struct drm_crtc *crtc;
 
int htotal, hdisplay, clock, pixel_size;
int line_time_us, line_count;
int entries, tlb_miss;
 
// ENTER();
 
// dbgprintf("plane %d display %x cursor %x \n", plane, display, cursor);
// dbgprintf("plane_wm %x cursor_wm %x \n", plane_wm, cursor_wm);
 
crtc = intel_get_crtc_for_plane(dev, plane);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
// dbgprintf("CRTC %d\n, fb %x, enabled %d\n",
// crtc->base.id, crtc->fb, crtc->enabled );
 
 
 
if (crtc->fb == NULL || !crtc->enabled || !intel_crtc->active) {
*cursor_wm = cursor->guard_size;
*plane_wm = display->guard_size;
1122,6 → 1133,8
clock = crtc->mode.clock;
pixel_size = crtc->fb->bits_per_pixel / 8;
 
// dbgprintf("mark 1\n");
 
/* Use the small buffer method to calculate plane watermark */
entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1132,18 → 1145,37
if (*plane_wm > (int)display->max_wm)
*plane_wm = display->max_wm;
 
// dbgprintf("clock %d line_time_us %d\n",clock, line_time_us );
 
/* Use the large buffer method to calculate cursor watermark */
line_time_us = ((htotal * 1000) / clock);
line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 
entries = line_count * 64 * pixel_size;
 
// dbgprintf("mark 3\n");
 
// dbgprintf("fifo size %d line size %d\n",
// cursor->fifo_size, cursor->cacheline_size);
 
tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 
if (tlb_miss > 0)
entries += tlb_miss;
 
// dbgprintf("mark 4\n");
 
entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 
// dbgprintf("entries %d \n",entries);
 
*cursor_wm = entries + cursor->guard_size;
 
if (*cursor_wm > (int)cursor->max_wm)
*cursor_wm = (int)cursor->max_wm;
 
// LEAVE();
 
return true;
}
 
1908,6 → 1940,7
(fbc_wm << WM1_LP_FBC_SHIFT) |
(plane_wm << WM1_LP_SR_SHIFT) |
cursor_wm);
 
}
 
static void
2130,6 → 2163,7
 
if (dev_priv->display.update_wm)
dev_priv->display.update_wm(dev);
 
}
 
void intel_update_linetime_watermarks(struct drm_device *dev,
/drivers/video/drm/i915/intel_ringbuffer.c
1178,6 → 1178,8
uint32_t __iomem *virt;
int rem = ring->size - ring->tail;
 
ENTER();
 
if (ring->space < rem) {
int ret = intel_wait_ring_buffer(ring, rem);
if (ret)
1192,6 → 1194,7
ring->tail = 0;
ring->space = ring_space(ring);
 
LEAVE();
return 0;
}