1338,6 → 1338,7 |
sumo_update_current_ps(rdev, new_ps); |
} |
|
#if 0 |
void sumo_dpm_reset_asic(struct radeon_device *rdev) |
{ |
sumo_program_bootup_state(rdev); |
1349,6 → 1350,7 |
sumo_set_forced_mode_enabled(rdev); |
sumo_set_forced_mode_disabled(rdev); |
} |
#endif |
|
void sumo_dpm_setup_asic(struct radeon_device *rdev) |
{ |
1537,6 → 1539,7 |
return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; |
} |
|
#if 0 |
u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev, |
struct sumo_vid_mapping_table *vid_mapping_table, |
u32 vid_7bit) |
1550,6 → 1553,7 |
|
return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit; |
} |
#endif |
|
static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev, |
u32 vid_2bit) |
1833,6 → 1837,34 |
} |
} |
|
u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev) |
{ |
struct sumo_power_info *pi = sumo_get_pi(rdev); |
struct radeon_ps *rps = &pi->current_rps; |
struct sumo_ps *ps = sumo_get_ps(rps); |
struct sumo_pl *pl; |
u32 current_index = |
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >> |
CURR_INDEX_SHIFT; |
|
if (current_index == BOOST_DPM_LEVEL) { |
pl = &pi->boost_pl; |
return pl->sclk; |
} else if (current_index >= ps->num_levels) { |
return 0; |
} else { |
pl = &ps->levels[current_index]; |
return pl->sclk; |
} |
} |
|
u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev) |
{ |
struct sumo_power_info *pi = sumo_get_pi(rdev); |
|
return pi->sys_info.bootup_uma_clk; |
} |
|
void sumo_dpm_fini(struct radeon_device *rdev) |
{ |
int i; |