| 1366,6 → 1366,7 |
|---|
| void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
| { |
| struct radeon_ring *ring = &rdev->ring[ib->ring]; |
| unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; |
| u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | |
| PACKET3_SH_ACTION_ENA; |
| |
| 1388,8 → 1389,7 |
|---|
| #endif |
| (ib->gpu_addr & 0xFFFFFFFC)); |
| radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
| radeon_ring_write(ring, ib->length_dw | |
| (ib->vm ? (ib->vm->id << 24) : 0)); |
| radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); |
| |
| /* flush read cache over gart for this vmid */ |
| radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 1396,7 → 1396,7 |
|---|
| radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); |
| radeon_ring_write(ring, 0xFFFFFFFF); |
| radeon_ring_write(ring, 0); |
| radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */ |
| radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */ |
| } |
| |
| static void cayman_cp_enable(struct radeon_device *rdev, bool enable) |
| 1672,7 → 1672,7 |
|---|
| } |
| |
| if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) |
| radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
| radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
| |
| return 0; |
| } |
| 1903,7 → 1903,7 |
|---|
| if (reset_mask) |
| evergreen_gpu_pci_config_reset(rdev); |
| |
| r600_set_bios_scratch_engine_hung(rdev, false); |
| r600_set_bios_scratch_engine_hung(rdev, false); |
| |
| return 0; |
| } |
| 1943,17 → 1943,17 |
|---|
| /* scratch needs to be initialized before MC */ |
| r = r600_vram_scratch_init(rdev); |
| if (r) |
| return r; |
| return r; |
| |
| evergreen_mc_program(rdev); |
| |
| if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { |
| r = ni_mc_load_microcode(rdev); |
| if (r) { |
| DRM_ERROR("Failed to load MC firmware!\n"); |
| return r; |
| r = ni_mc_load_microcode(rdev); |
| if (r) { |
| DRM_ERROR("Failed to load MC firmware!\n"); |
| return r; |
| } |
| } |
| } |
| |
| r = cayman_pcie_gart_enable(rdev); |
| if (r) |
| 2379,7 → 2379,7 |
|---|
| default: |
| block = "unknown"; |
| break; |
| } |
| } |
| |
| printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", |
| protections, vmid, addr, |
| 2395,16 → 2395,12 |
|---|
| * Update the page table base and flush the VM TLB |
| * using the CP (cayman-si). |
| */ |
| void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) |
| void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| unsigned vm_id, uint64_t pd_addr) |
| { |
| struct radeon_ring *ring = &rdev->ring[ridx]; |
| radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); |
| radeon_ring_write(ring, pd_addr >> 12); |
| |
| if (vm == NULL) |
| return; |
| |
| radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0)); |
| radeon_ring_write(ring, vm->pd_gpu_addr >> 12); |
| |
| /* flush hdp cache */ |
| radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); |
| radeon_ring_write(ring, 0x1); |
| 2411,7 → 2407,7 |
|---|
| |
| /* bits 0-7 are the VM contexts0-7 */ |
| radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); |
| radeon_ring_write(ring, 1 << vm->id); |
| radeon_ring_write(ring, 1 << vm_id); |
| |
| /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
| radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |