1816,8 → 1816,8 |
} |
|
offset = reloc->gpu_offset + |
(idx_value & 0xfffffff0) + |
((u64)(tmp & 0xff) << 32); |
(idx_value & 0xfffffff0) + |
((u64)(tmp & 0xff) << 32); |
|
ib[idx + 0] = offset; |
ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); |
1862,8 → 1862,8 |
} |
|
offset = reloc->gpu_offset + |
idx_value + |
((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
idx_value + |
((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
|
ib[idx+0] = offset; |
ib[idx+1] = upper_32_bits(offset) & 0xff; |
1897,8 → 1897,8 |
} |
|
offset = reloc->gpu_offset + |
idx_value + |
((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
idx_value + |
((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
|
ib[idx+0] = offset; |
ib[idx+1] = upper_32_bits(offset) & 0xff; |
1925,8 → 1925,8 |
} |
|
offset = reloc->gpu_offset + |
radeon_get_ib_value(p, idx+1) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
radeon_get_ib_value(p, idx+1) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
|
ib[idx+1] = offset; |
ib[idx+2] = upper_32_bits(offset) & 0xff; |
2098,8 → 2098,8 |
} |
|
offset = reloc->gpu_offset + |
(radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
(radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
|
ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); |
ib[idx+2] = upper_32_bits(offset) & 0xff; |
2239,8 → 2239,8 |
return -EINVAL; |
} |
offset = reloc->gpu_offset + |
(radeon_get_ib_value(p, idx+1) & 0xfffffff8) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
(radeon_get_ib_value(p, idx+1) & 0xfffffff8) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
|
ib[idx+1] = offset & 0xfffffff8; |
ib[idx+2] = upper_32_bits(offset) & 0xff; |
2261,8 → 2261,8 |
} |
|
offset = reloc->gpu_offset + |
(radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
(radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
|
ib[idx+1] = offset & 0xfffffffc; |
ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); |
2283,8 → 2283,8 |
} |
|
offset = reloc->gpu_offset + |
(radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
(radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
|
ib[idx+1] = offset & 0xfffffffc; |
ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); |