| 37,8 → 37,6 |
|---|
| |
| #include <linux/module.h> |
| #include <linux/pm_runtime.h> |
| #include <linux/vgaarb.h> |
| #include <linux/vga_switcheroo.h> |
| #include <drm/drm_crtc_helper.h> |
| |
| #include <syscall.h> |
| 574,7 → 572,13 |
|---|
| |
| intel_suspend_gt_powersave(dev); |
| |
| /* |
| * Disable CRTCs directly since we want to preserve sw state |
| * for _thaw. Also, power gate the CRTC power wells. |
| */ |
| drm_modeset_lock_all(dev); |
| intel_display_suspend(dev); |
| drm_modeset_unlock_all(dev); |
| |
| intel_dp_mst_suspend(dev); |
| |
| 729,10 → 733,12 |
|---|
| dev_priv->display.hpd_irq_setup(dev); |
| spin_unlock_irq(&dev_priv->irq_lock); |
| |
| drm_modeset_lock_all(dev); |
| intel_display_resume(dev); |
| drm_modeset_unlock_all(dev); |
| |
| intel_dp_mst_resume(dev); |
| |
| intel_display_resume(dev); |
| |
| /* |
| * ... but also need to make sure that hotplug processing |
| * doesn't cause havoc. Like in the driver load code we don't |
| 852,7 → 858,6 |
|---|
| |
| return i915_drm_resume(dev); |
| } |
| #endif |
| |
| /** |
| * i915_reset - reset chip after a hang |
| 905,7 → 910,7 |
|---|
| return ret; |
| } |
| |
| // intel_overlay_reset(dev_priv); |
| intel_overlay_reset(dev_priv); |
| |
| /* Ok, now get things going again... */ |
| |
| 947,7 → 952,6 |
|---|
| return 0; |
| } |
| |
| #if 0 |
| static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
| { |
| struct intel_device_info *intel_info = |
| 1077,6 → 1081,7 |
|---|
| */ |
| broxton_init_cdclk(dev); |
| broxton_ddi_phy_init(dev); |
| intel_prepare_ddi(dev); |
| |
| return 0; |
| } |
| 1336,7 → 1341,7 |
|---|
| return 0; |
| |
| DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", |
| onoff(wait_for_on), |
| wait_for_on ? "on" : "off", |
| I915_READ(VLV_GTLC_PW_STATUS)); |
| |
| /* |
| 1346,7 → 1351,7 |
|---|
| err = wait_for(COND, 3); |
| if (err) |
| DRM_ERROR("timeout waiting for GT wells to go %s\n", |
| onoff(wait_for_on)); |
| wait_for_on ? "on" : "off"); |
| |
| return err; |
| #undef COND |
| 1357,7 → 1362,7 |
|---|
| if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) |
| return; |
| |
| DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); |
| DRM_ERROR("GT register access while GT waking disabled\n"); |
| I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
| } |
| |
| 1501,10 → 1506,6 |
|---|
| |
| enable_rpm_wakeref_asserts(dev_priv); |
| WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); |
| |
| if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) |
| DRM_ERROR("Unclaimed access detected prior to suspending\n"); |
| |
| dev_priv->pm.suspended = true; |
| |
| /* |
| 1553,8 → 1554,6 |
|---|
| |
| intel_opregion_notify_adapter(dev, PCI_D0); |
| dev_priv->pm.suspended = false; |
| if (intel_uncore_unclaimed_mmio(dev_priv)) |
| DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); |
| |
| intel_guc_resume(dev); |
| |