/drivers/video/drm/radeon/cik_sdma.c |
---|
610,19 → 610,16 |
{ |
unsigned i; |
int r; |
unsigned index; |
void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
u32 tmp; |
u64 gpu_addr; |
if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
index = R600_WB_DMA_RING_TEST_OFFSET; |
else |
index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; |
if (!ptr) { |
DRM_ERROR("invalid vram scratch pointer\n"); |
return -EINVAL; |
} |
gpu_addr = rdev->wb.gpu_addr + index; |
tmp = 0xCAFEDEAD; |
rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
writel(tmp, ptr); |
r = radeon_ring_lock(rdev, ring, 5); |
if (r) { |
630,14 → 627,14 |
return r; |
} |
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); |
radeon_ring_write(ring, lower_32_bits(gpu_addr)); |
radeon_ring_write(ring, upper_32_bits(gpu_addr)); |
radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); |
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); |
radeon_ring_write(ring, 1); /* number of DWs to follow */ |
radeon_ring_write(ring, 0xDEADBEEF); |
radeon_ring_unlock_commit(rdev, ring, false); |
for (i = 0; i < rdev->usec_timeout; i++) { |
tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
tmp = readl(ptr); |
if (tmp == 0xDEADBEEF) |
break; |
DRM_UDELAY(1); |
/drivers/video/drm/radeon/kv_dpm.c |
---|
2725,10 → 2725,6 |
pi->sram_end = SMC_RAM_END; |
/* Enabling nb dpm on an asrock system prevents dpm from working */ |
if (rdev->pdev->subsystem_vendor == 0x1849) |
pi->enable_nb_dpm = false; |
else |
pi->enable_nb_dpm = true; |
pi->caps_power_containment = true; |
2744,19 → 2740,10 |
pi->caps_sclk_ds = true; |
pi->enable_auto_thermal_throttling = true; |
pi->disable_nb_ps3_in_battery = false; |
if (radeon_bapm == -1) { |
/* There are stability issues reported on with |
* bapm enabled on an asrock system. |
*/ |
if (rdev->pdev->subsystem_vendor == 0x1849) |
if (radeon_bapm == 0) |
pi->bapm_enable = false; |
else |
pi->bapm_enable = true; |
} else if (radeon_bapm == 0) { |
pi->bapm_enable = false; |
} else { |
pi->bapm_enable = true; |
} |
pi->voltage_drop_t = 0; |
pi->caps_sclk_throttle_low_notification = false; |
pi->caps_fps = false; /* true? */ |
/drivers/video/drm/radeon/r600_dma.c |
---|
232,19 → 232,16 |
{ |
unsigned i; |
int r; |
unsigned index; |
void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
u32 tmp; |
u64 gpu_addr; |
if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
index = R600_WB_DMA_RING_TEST_OFFSET; |
else |
index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; |
if (!ptr) { |
DRM_ERROR("invalid vram scratch pointer\n"); |
return -EINVAL; |
} |
gpu_addr = rdev->wb.gpu_addr + index; |
tmp = 0xCAFEDEAD; |
rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
writel(tmp, ptr); |
r = radeon_ring_lock(rdev, ring, 4); |
if (r) { |
252,13 → 249,13 |
return r; |
} |
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
radeon_ring_write(ring, lower_32_bits(gpu_addr)); |
radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); |
radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); |
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); |
radeon_ring_write(ring, 0xDEADBEEF); |
radeon_ring_unlock_commit(rdev, ring, false); |
for (i = 0; i < rdev->usec_timeout; i++) { |
tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
tmp = readl(ptr); |
if (tmp == 0xDEADBEEF) |
break; |
DRM_UDELAY(1); |
/drivers/video/drm/radeon/r600.c |
---|
3715,17 → 3715,17 |
wptr = RREG32(IH_RB_WPTR); |
if (wptr & RB_OVERFLOW) { |
wptr &= ~RB_OVERFLOW; |
/* When a ring buffer overflow happen start parsing interrupt |
* from the last not overwritten vector (wptr + 16). Hopefully |
* this should allow us to catchup. |
*/ |
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", |
wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); |
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", |
wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); |
rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; |
tmp = RREG32(IH_RB_CNTL); |
tmp |= IH_WPTR_OVERFLOW_CLEAR; |
WREG32(IH_RB_CNTL, tmp); |
wptr &= ~RB_OVERFLOW; |
} |
return (wptr & rdev->ih.ptr_mask); |
} |
3963,9 → 3963,9 |
/* wptr/rptr are in bytes! */ |
rptr += 16; |
rptr &= rdev->ih.ptr_mask; |
WREG32(IH_RB_RPTR, rptr); |
} |
rdev->ih.rptr = rptr; |
WREG32(IH_RB_RPTR, rdev->ih.rptr); |
atomic_set(&rdev->ih.lock, 0); |
/* make sure wptr hasn't changed while processing */ |
/drivers/video/drm/radeon/radeon_device.c |
---|
71,8 → 71,8 |
int radeon_use_pflipirq = 2; |
int irq_override = 0; |
int radeon_bapm = -1; |
int radeon_backlight = 0; |
extern display_t *os_display; |
extern struct drm_device *main_device; |
extern videomode_t usermode; |
183,10 → 183,6 |
* https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
*/ |
{ PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, |
/* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU |
* https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
*/ |
{ PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, |
/* macbook pro 8.2 */ |
{ PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, |
{ 0, 0, 0, 0, 0 }, |
1176,7 → 1172,7 |
if (radeon_vm_block_size == -1) { |
/* Total bits covered by PD + PTs */ |
unsigned bits = ilog2(radeon_vm_size) + 18; |
unsigned bits = ilog2(radeon_vm_size) + 17; |
/* Make sure the PD is 4K in size up to 8GB address space. |
Above that split equal between PD and PTs */ |
/drivers/video/drm/radeon/cik.c |
---|
4803,7 → 4803,7 |
*/ |
static int cik_cp_compute_resume(struct radeon_device *rdev) |
{ |
int r, i, j, idx; |
int r, i, idx; |
u32 tmp; |
bool use_doorbell = true; |
u64 hqd_gpu_addr; |
4922,7 → 4922,7 |
mqd->queue_state.cp_hqd_pq_wptr= 0; |
if (RREG32(CP_HQD_ACTIVE) & 1) { |
WREG32(CP_HQD_DEQUEUE_REQUEST, 1); |
for (j = 0; j < rdev->usec_timeout; j++) { |
for (i = 0; i < rdev->usec_timeout; i++) { |
if (!(RREG32(CP_HQD_ACTIVE) & 1)) |
break; |
udelay(1); |
7751,17 → 7751,17 |
wptr = RREG32(IH_RB_WPTR); |
if (wptr & RB_OVERFLOW) { |
wptr &= ~RB_OVERFLOW; |
/* When a ring buffer overflow happen start parsing interrupt |
* from the last not overwritten vector (wptr + 16). Hopefully |
* this should allow us to catchup. |
*/ |
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", |
wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); |
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", |
wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); |
rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; |
tmp = RREG32(IH_RB_CNTL); |
tmp |= IH_WPTR_OVERFLOW_CLEAR; |
WREG32(IH_RB_CNTL, tmp); |
wptr &= ~RB_OVERFLOW; |
} |
return (wptr & rdev->ih.ptr_mask); |
} |
8225,9 → 8225,9 |
/* wptr/rptr are in bytes! */ |
rptr += 16; |
rptr &= rdev->ih.ptr_mask; |
WREG32(IH_RB_RPTR, rptr); |
} |
rdev->ih.rptr = rptr; |
WREG32(IH_RB_RPTR, rdev->ih.rptr); |
atomic_set(&rdev->ih.lock, 0); |
/* make sure wptr hasn't changed while processing */ |
/drivers/video/drm/radeon/dce3_1_afmt.c |
---|
49,8 → 49,8 |
sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); |
if (sad_count < 0) { |
DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
sad_count = 0; |
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
return; |
} |
/* program the speaker allocation */ |
/drivers/video/drm/radeon/dce6_afmt.c |
---|
176,9 → 176,9 |
} |
sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); |
if (sad_count < 0) { |
DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
sad_count = 0; |
if (sad_count <= 0) { |
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
return; |
} |
/* program the speaker allocation */ |
/drivers/video/drm/radeon/evergreen.c |
---|
4749,17 → 4749,17 |
wptr = RREG32(IH_RB_WPTR); |
if (wptr & RB_OVERFLOW) { |
wptr &= ~RB_OVERFLOW; |
/* When a ring buffer overflow happen start parsing interrupt |
* from the last not overwritten vector (wptr + 16). Hopefully |
* this should allow us to catchup. |
*/ |
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", |
wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); |
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", |
wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); |
rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; |
tmp = RREG32(IH_RB_CNTL); |
tmp |= IH_WPTR_OVERFLOW_CLEAR; |
WREG32(IH_RB_CNTL, tmp); |
wptr &= ~RB_OVERFLOW; |
} |
return (wptr & rdev->ih.ptr_mask); |
} |
/drivers/video/drm/radeon/evergreen_hdmi.c |
---|
118,9 → 118,9 |
} |
sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); |
if (sad_count < 0) { |
DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
sad_count = 0; |
if (sad_count <= 0) { |
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
return; |
} |
/* program the speaker allocation */ |
/drivers/video/drm/radeon/radeon.h |
---|
114,7 → 114,6 |
extern int radeon_deep_color; |
extern int radeon_use_pflipirq; |
extern int radeon_bapm; |
extern int radeon_backlight; |
typedef struct pm_message { |
1141,8 → 1140,6 |
#define R600_WB_EVENT_OFFSET 3072 |
#define CIK_WB_CP1_WPTR_OFFSET 3328 |
#define CIK_WB_CP2_WPTR_OFFSET 3584 |
#define R600_WB_DMA_RING_TEST_OFFSET 3588 |
#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 |
/** |
* struct radeon_pm - power management datas |
/drivers/video/drm/radeon/radeon_encoders.c |
---|
158,43 → 158,10 |
return ret; |
} |
static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder, |
struct drm_connector *connector) |
{ |
struct drm_device *dev = radeon_encoder->base.dev; |
struct radeon_device *rdev = dev->dev_private; |
bool use_bl = false; |
if (!(radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))) |
return; |
if (radeon_backlight == 0) { |
return; |
} else if (radeon_backlight == 1) { |
use_bl = true; |
} else if (radeon_backlight == -1) { |
/* Quirks */ |
/* Amilo Xi 2550 only works with acpi bl */ |
if ((rdev->pdev->device == 0x9583) && |
(rdev->pdev->subsystem_vendor == 0x1734) && |
(rdev->pdev->subsystem_device == 0x1107)) |
use_bl = false; |
else |
use_bl = true; |
} |
if (use_bl) { |
if (rdev->is_atom_bios) |
radeon_atom_backlight_init(radeon_encoder, connector); |
else |
radeon_legacy_backlight_init(radeon_encoder, connector); |
rdev->mode_info.bl_encoder = radeon_encoder; |
} |
} |
void |
radeon_link_encoder_connector(struct drm_device *dev) |
{ |
struct radeon_device *rdev = dev->dev_private; |
struct drm_connector *connector; |
struct radeon_connector *radeon_connector; |
struct drm_encoder *encoder; |
207,12 → 174,17 |
radeon_encoder = to_radeon_encoder(encoder); |
if (radeon_encoder->devices & radeon_connector->devices) { |
drm_mode_connector_attach_encoder(connector, encoder); |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
radeon_encoder_add_backlight(radeon_encoder, connector); |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
if (rdev->is_atom_bios) |
radeon_atom_backlight_init(radeon_encoder, connector); |
else |
radeon_legacy_backlight_init(radeon_encoder, connector); |
rdev->mode_info.bl_encoder = radeon_encoder; |
} |
} |
} |
} |
} |
void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
{ |
/drivers/video/drm/radeon/si.c |
---|
6316,17 → 6316,17 |
wptr = RREG32(IH_RB_WPTR); |
if (wptr & RB_OVERFLOW) { |
wptr &= ~RB_OVERFLOW; |
/* When a ring buffer overflow happen start parsing interrupt |
* from the last not overwritten vector (wptr + 16). Hopefully |
* this should allow us to catchup. |
*/ |
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", |
wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); |
dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", |
wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); |
rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; |
tmp = RREG32(IH_RB_CNTL); |
tmp |= IH_WPTR_OVERFLOW_CLEAR; |
WREG32(IH_RB_CNTL, tmp); |
wptr &= ~RB_OVERFLOW; |
} |
return (wptr & rdev->ih.ptr_mask); |
} |
6662,11 → 6662,11 |
/* wptr/rptr are in bytes! */ |
rptr += 16; |
rptr &= rdev->ih.ptr_mask; |
WREG32(IH_RB_RPTR, rptr); |
} |
// if (queue_hotplug) |
// schedule_work(&rdev->hotplug_work); |
rdev->ih.rptr = rptr; |
WREG32(IH_RB_RPTR, rdev->ih.rptr); |
atomic_set(&rdev->ih.lock, 0); |
/* make sure wptr hasn't changed while processing */ |
/drivers/video/drm/radeon/si_dpm.c |
---|
6255,7 → 6255,7 |
if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && |
index == 0) { |
/* XXX disable for A0 tahiti */ |
si_pi->ulv.supported = false; |
si_pi->ulv.supported = true; |
si_pi->ulv.pl = *pl; |
si_pi->ulv.one_pcie_lane_in_ulv = false; |
si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; |